ertek. SY6500 8-Bit Microprocessor Family Features Single 5 V +5% Power Supply N Channel, Silicon Gate, Depletion Load Technology Eight Bit Parallel Processing 56 Instructions Decimal and Binary Arithmetic Thirteen Addressing Modes True Indexing Capability Programmable Stack Pointer Variable Length Stack Interrupt Capability Non-maskable Interrupt Use with Any Type or Speed Memory Bi-directional Data Bus Instruction Decoding and Control ‘Addressable Memory Range of up to 65K Bytes Ready” Input Direct Memory Access Capability Bus Compatible with MC6800 Choice of External or On-board Clocks 1 MHz, 2 MHz Operation. (On-chip Clock Options — External Single Clock Input ‘— Crystal Time Base Input 40 and 28 Pin Package Versions. Pipeline Architecture Description The SY6500 Series Microprocessors represent the first totally software compatible microprocessor family. This fam- ily of products includes 2 range of software compatible microprocessors which provide a selection of addressable memory range, interrupt input options and on-chip clock oscillators and drivers. All of the microprocessors in the ‘S¥6500 family are software compatible within the group and are bus compatible with the MC6800 product offering, Members of the Family Pa Number | Clocks |Pins | 1Ra| NMI|RYD | Addressing ‘sy6502 | On-cnip] 40, V | V | Vv aK S¥8507 “| 2B v 8k sv6512 | External] 40] Vv | Vv | Vv 64k ‘The family includes six microprocessors with on-board clock oscillators and drivers for four microprocessors driven by ‘external clocks. The on-chip clock versions are aimed at high performance, low cost applications where single phase inputs or crystals provide the time base. The external clock versions are geared for the multi-processor system applic tions where maximum timing control is mandatory. All versions of the microprocessors are available in 1 MHz, 2 Miz, 3 MHz and 4 MHz maximum operating frequencies. Ordering Information SY P6502A Teveeo SYNERTEK INC— (No Suffix = 1 MHz ‘A= 2MHz PACKAGE TYPE P= Molded DIP SPECIFIC TYPE 02.07 65x FAMILY ————J 12aumerick, SY6500 ‘Comments on the Data Sheet ‘The data shest is constructed to review the basic “Common Characteristics" — those features which are common to the general family of microprocessors. Subsequent to a review of the family characteristics will be sections devoted to each member of the group with specific features of each. $Y6500 Internal Architecture eee | ! sa 7 o Ei . i : i 8 =I ee ep ane a on poe nim 1 Slack GeneRaron is Nor mcLUDED QW s¥EstXSunertek, sY6500 Absolute Maximum Ratings* Comment ‘This device contains input protection against damage due to Rating Symbol | Value __| Unit _| high static voltages or electric fields; however, precautions [Supply Voltage Vec_|=0.3t0 470] V_| should be akon to avold application of voltages higher than Input Voltage Vin_| -0.3t0+7.0| V ‘the maximum rating Operating Temperature) T, | Oto+70 | °C Storage Temperature | Tgrg | -56t0+160| °C D.C. Characteristics (Voo= 5.0V 25%, Ty = 0-70°C) (©;, 02 applies to SYG5IX, On) applies to SYB5OX) Symbol Characteristic Min. Max. Unit Vin | Input High Vottage Laagars noe} {iagme | ze Yee v all 650X devices ale 433 Yee v 8, and 0 only for all 651X devices. Losie All Speeds | Voc-0.8 | Voc +0.28 v as 650X Viv] put Cow Vorioge Logic, Oyj (650X) -0.3 40.8 4,,0, (51x) -03 102 v 7 Tapat Loading (Wg, = OV. Veg = 5.25 V) -10 -300 HA ADY,S.0 Tnput Leakage Current (Wj, =0 10 8.25 V, Veg = 0) Logic (Excl. RY, $.0.) - 25 HA 6,0, (651x) . 100 HA Isto (650x) 10.0 uA Ts) Three-State (Off State) Input Current (Wy, = 0.4 10 2.4 V, Veg = 5.25 V) | 080.087 410 uA Vou | Output High Voltage (gap = “1O0HAdE, Veg" 4.75.) 1,2 MHz 24 - v SYNC. DB0.087, AO-AIS, R/T Vou | Outbut Low Voltage gap = VEMAd, Veg" 4.75 V1, 2MHz . 04 v SYNC, DBO-DB7, AO-AIS, R/W Po | Power Dissipation TMHz and 2 Miz = 700 mn (ec = 5.25V) t Capacitance Wig 7 0, Ty = 28°C, f= 1 MHZ} c, AES, NMii, RDY, TRO, S.0., OBE - 10 080-087 . 15 ce AO-A15, R/i, SYNC - 12 pF c ee (50x) : 15 oy, a (51x) - 80Sunertek, SY6500 Dynamic Operating Characteristics Wee = 5.0 * 5%, Ta = 0° to 70°C) TMi 2M Parameter Symbot_| Min. Min. | Max_| Units 51x Cycle Time tere | 100] 40 | 050} 40 | us 8 Pulse width Towne, | 430 | — | 215 | — | as 8, Pulse Width es [ao | | leo Delay Betwoen 9; andy To o | — | o | — Jos 8; and 8 Rise aad Fall Times! tet | o | 2 | o | 20 | ae 650x Cycle Time Tee | 100] 40 | 050] 40 | us B.gq Low Timol2 ty, | 40 | — | 20 | — | ne 8.gy High Time? tw, | 460} — | 240 | — | ne 0, Neg to 8, Pos Delay) i | 0 | | | wm | oe 0, Nog to 0; Neg Delay®! Tae || S| oe 65 | ns 8, Pos 1 8; Neg Delays to | 5 | 68 65 | ne 8, Posto 0, Pos Delay) Tou | 18 | 75 75 | ns gu Riso and Fall Time? Trotro | 0 | 30 20 | ne @,(oun Pulse Wieth Towra, T9520] Tra, Tuy | 08 Bun Pulse Width Twists (Tra,40 | Tre,-10 Tags 10 | ns Delay Between Oy and 0, To 5 | — — | os 8, and B, Rise and Fall Times rs GS Ls 50K, 651X RAW Setup Time tows | — | 225 | — | 140 | os RAW Hola Time ie | | | ‘Aadross Setup Time Twos | — | 225 | — | 140 | ne ‘Ades Hold Time Trou | 30 | — | 30 | — | ns Read Access Time Tae | — | 080 | — | 310 | ne ead Data Setup Time Tou | 100] — | 50 | — | ns Read Data Hold Time ta | 10 | ~ | 0 | — Jos ‘Waite Date Setup Time Twos | 20 | 175 | 20 | 100 | as Write Data Hold Time tw | 60 | 150 | 60 | 150 | ne Syne Setup Time tos | — | 380 | — | 175 | ns Syne Hold Time ee fe | oe DY Setup Time”) Trs__| 200 | — | 200 | — | ns Ne 1. Messured between 10% and 90% points Timing Diagram Note: 2) Measured at 50% points Because the clock generation for the SYB5OX and SY651X is dit 3. Load 1 TTL load +20 pF. ferent, the two clock timing sections are referenced to the main 44. ROY must never switch states within Tas to end afd. timing diagram by three reference lines marked REF A, REF ‘8 5. Load = 100 pF. and REF ‘C’ Roferance between the two sets of clock timings is 6. The 2 MHs devices are identified by an “A” suttix. ‘without meaning, Timing parameters are referred to these lines {nd Scale variations in the diagrams are of no consequence.Sunetick, SY6500 Pin Functions Clocks (43. da) ‘The SY651X requires a two phase non-overlapping clock that runs at the Vcc voltage level ‘The SYB5OX clocks are supplied with an internal clock gen- erator. The frequency of these clocks is externally ‘controlled. Clock generator circuits are shown elsewhere in this data sheet. ‘Address Bus Ag-Ars) (See sections on each micro for respective address lines on those devices.) ‘These outputs are TTL compatible, capable of driving one standard TTL load and 130 pF. Data Bus (DBp-D8;) Eight pins are used for the data bus. This is a bi-directional bus, transferring data to and from the device and peripher- als, The outputs are three-state buffers, capable of driving fone standard TTL (oad and 130 pF. Data Bus Enable (DBE) This TTL compatible input allows external control of the three-state data output buffers and will enable the micro- processor bus driver when in the high state. In normal operation DBE would be driven by the phase two (¢2) clock, thus allowing date output from microprocessor only during é, During the read eycle, the data bus drivers are internally disebled, becoming essentially an open circuit. To disable data bus drivers externally, DBE should be held low. This signal is available on the SY6512, only. Ready (RDY) This input signal allows the user to halt the microprocessor on all cycles except write cycles. A negative transition to the low state during or coincident with phase one, (dy) will halt the microprocessor with the output address lines reflecting the current address being fetched. This condition will femain through a subsequent phase two (dz) in which the Ready signal is low. This feature allows microprocessor interfacing with low speed PROMS as well as fast (max. 2 cycle) Direct Memory Access (DMA). If ready is low during a ‘write cycle, itis ignored until the following read opeation Ready transitions must not be permitted during da time. Interrupt Request (iG) This TTL level input requests that an interrupt sequence begin within the microprocessor. The microprocessor will complete the current instruction being executed before rec- ‘ognizing the request. At the time, the interrupt mask bit in the Status Code Register wil be examined. Ifthe interrupt mask flag is not set, the microprocessor will begin an intor- rupt sequence. The Program Counter and Processor Status Rogister are stored in the stack The microprocessor will then set the interrupt mask flag high so that no futher inter- rupts may occur. At the end of this cycle, the program ‘counter low willbe loaded from address FFE, and program counter high from location FFFF, therefore transferring pro- ‘gram control to the memory vector located at these ‘addrosses. The RDY signal must be in the high state for any interrupt to be recognized. A 3K external resistor should be used for proper wire-OR operation. ‘Non-Maskable Interrupt (TT) A negative going transition on this input requests that @ ron-maskable interrupt sequence be generated within the ‘mieroprocessor NMI is an unconditional interrupt. Following completion of the current instruction, the sequence of operations defined for IRC will be performed, regardless of the state interrupt mask flag. The vector address loaded into the program counter, low and high, are locations FFA and FFF respec: tively, thereby transferring program contol tothe memory vector located at these addresses. The instructions loaded at these locations cause the microprocessor to branch toa ron-maskable interrupt routine in memory. FIM aso requires an external 3KA resistor to Vec for proper wice-OR operations. Inputs IRG and NMI are hardware interrupts lines that are sampled during 2 (phase 2) and wil begin the appropriate interrupt routine on the 4; (phase 1) following the comple- tion ofthe current instruction, ‘Set Overflow Flag (S.0.) [A NEGATIVE going edge on this input sets the overtow bit in the Status Code Register. This signal is sampled on the traing edge of 1 SYNC This output line is provided to identity those cycles in which the mictoprocessor is doing an OP CODE fetch. The SYNC line goes high during 4 of an OP CODE fetch and stays high forthe remainder ofthat eyle. the RDY line is pulled low during the & clock pulse in which SYNC went high, the processor wil stop in ts current state and wil remain inthe stato until the RDY line goes high In this manner, the SYNC signal can be used fo control RDY to cause singe instruc- tion execution Reset (RES) This input is used to reset or stan the microprocessor from power down condition. During the time that this line is held low. writing to of from the microprocessor is inhibited. When a positive edge is detected on the input, the microp- rocessor wil immediately begin the reset sequence After a system initialization time of six clock cycles, the mask interrupt lag wil be set and the microprocessor wil toad the program counter from the memory vector locations FFEC and FFFD. This Is the star location for program contr Atter Vec reaches 4.75 volts in a power up routine, reset ‘must be held low for atleast two clock cycles. At this time the B/W and SYNC signal will become valid When the reset signal oes high following these two clock cyeles, the microprocessor will proceed with the normal reset procedure detailed above Read/Write (R/W) This output signal is used to control the direction of data transfers between the processor and other cicults on the data bus. A high level on R/W signifies data into the pro- cessor low i forthe data transfer out of the processor.Sumertek, SY6500 Programming Characteristics INSTRUCTION SET — ALPHABETIC SEQUENCE ADC Add Memory to Accumulator with Carry AND “AND” Memory with Accumulator ASL. Shift left One Bit Memory or Accumulator) BCC. Branch on Carry Clear BCS Branch on Carry Set BEQ_ Branch on Result Zero BIT Test Bits in Memory with Accumulator BMI Branch on Result Minus BNE Branch on Result not Zero BPL_ Branch on Result Plus BRK Force Break BVC Branch on Overflow Clear BVS Branch on Overflow Set CLC. Clear Carry Flag CLD Clear Decimal Mode CLI Clear interrupt Disable Bit CLV Clear Overfiow Flag CMP Compare Memory and Accumulator GPX Compare Memory and Index X PY Compare Memory and Index Y DEC Decrement Memory by One DEX Decrement Index X by One DEY Decrement Index ¥ by One EOR “Exclusi INC Increment Memory by One IN. Increment Index X by One INY Increment index ¥ by One IMP Jump to New Location JSR Jump to New Location Saving Return Address " Memory with Accumulator LOA. Load Accumulator with Memory LOX Load Index X with Memory LDY Load Index Y with Memory LSR_ Shift One Bit Right (Memory or Accumulator) NOP No Operation ‘ORA “OR" Memory with Accumulator PHA Push Accumulator on Stack PHP Push Processor Status on Stack PLA Pull Accumulator from Stack PLP Pull Processor Status from Stack ROL Rotate One Bit Left (Memory or Accumulator) ROR Rotate One Bit Right (Memory of Accumulator) RTL Return from Interrupt RTS. Return from Subroutine SBC Subtract Memory from Accumulator with Borrow SEC Set Carry Flag SED Set Decimal Mode SEI Set Interrupt Disable Status ‘STA Store Accumulator in Memory STX. Store index X in Memory STY Store Index ¥ in Memory TAX Transfer Accumulator to Index X TAY Transfer Accumulator to Index Y ‘TSX Transfer Stack Pointer to Index X TXA Transfer Index X to Accumulator TXS. Transfer Index X to Stack Pointer TVA Transfer Index Y to Accumulator ADDRESSING MODES. ‘Accumulator Addressing This form of addressing is represented with a one byte instruction, implying an operation on the accumulator. Immediate Addressing In immediate addressing, the operand is contained in the second byte of the instruction, with no further memory addressing required. Absolute Addressing In absolute addressing. the second byte of the instruction ‘specifies the eight low order bits of the effective address while the third byte specifies the eight high order bits. ‘Thus, the absolute addressing mode allows access to the entire 65K bytes of addressable memory. Zero page Addressing ‘The zero page instructions allow for shorter cqde and execution times by only fetching the second byte of the instruction and assuming azero high address byte. Careful use of the zero page can result in significant increase in code efficiency. Indexed Zero Page Addressing — (X. ¥ indexing) ‘This form of addressing is used in conjunction with the index register andis referred toas "Zero Page, X" or "Zero Page, Y.” The effective address is calculated by adding the ‘second byte to the contents of the index register. Since this is 2 form of “Zero Page” addressing, the content of the ‘second byte references. location in page zero. Additionally due to the "Zero Page” addressing nature of this mode, no carty is added to the high order 8 bits of memory and ‘crossing of page boundaries does not occur. Indexed Absolute Addressing — (X, ¥ indexing) This form of addressing is usedin conjunction with X and ¥ index register and is referred to as “Absolute, X,” and ‘Absolute, Y." The effective address is formed by adding the contents of X or ¥ to the address contained in the second and third bytes of the instruction. This mode allows the index register to contain the index or count value and ‘the instruction to contain the base address. This type of indexing allows any location referencing and the index to modify multiple fields resulting in reduced coding and execution time, Implied Addressing Inthe implied addressing mode, the address containing the operand is implicitly stated in the operation code of the instruction.Supetieh, S¥6500 Relative Addressing Relative addressing is used only with branch instructions ‘and establishes a destination for the conditional branch. The second byte of the instruction becomes the operand which is an “Offset” added to the contents of the lower ‘eight bits of the program counter when the counter is set at ‘the next instruction, The range of the offset is -128 to +127 bytes from the next instruction. Indexed Indirect Addressing In indexed indirect addressing (referred to as [Indirect, XI), ‘the second byte of the instruction is added to the contents of the X index register, discarding the carry. The result of this addition points to a memory location on page zero Whose contents is the low order eight bits of the effective address. The next memory location in page zero contains the high order eight bits of the effective address. Both memory locations specifying the high and low order bytes of the effective address must be in page zero. Programming Characteristics PROGRAMMING MODEL eee ree) Co (=F moonanconsen [ETF stece ronan Indirect Indexed Addressing In indirect indexed addressing (referred to as [Indirect], Y), the second byte of the instruction points to a memory loca- tion in page zero. The contents of this memory location is added to the contents of the Y index register, the result being the low order eight bits of the effective address. The carry from this addition is added to the contents of the next page zero memory location, the result being hte high order eight bits of the effective address. Absolute Indirect ‘The second byte of the instruction contains the Iwo order ight bits of a memory location. The high order eight bits of that memory location is contained in the third byte of the instruction. The contents of the fully specified memory loca~ tion is the low order byte of the effective address. The next memory location contains the high order byte of the effec- tive address which is loaded into the sixteen bits of the program counter. ovenriow 1 TRUE [RECTETEEEE) rrocessonsrarus neamumeriek, SY6500 INSTRUCTION SET — OP CODES, EXECUTION TIME, MEMORY REQUIREMENTS faa biel dalle fart mmo | aamoa ofan (afae| a] | a at 17 eels posed Wi ! 7 rrr RTE Hee feof ese of ese teint ||| t a i Maeronensoe | | | fects} || | we dala alc alas asf fers foe «|>fool|ofos| «fof _| i wees for]u [fore] elorls] elor]yTolor]u | dor] elorle| alors] elorls] elon] olor] fl sloelelabnlal(|L LET | lose ate [a fees deal ele sfea|a| | | [TET Yee fe fe feof fale eel LP a fala 1] praleee | a2 i HUE 00 2 To ws iF ananw Occurs To SFERENT pace tN Laon hoo ReemaSunertek, SY6500 eee $6502 — 40 Pin Package Features © 65K Addressable Bytes of Memory © IRQ Interrupt © NMI Intercupt * On-the-chip Clock V TTL Level Single Phase Input V Crystal Time Base Input ‘* SYNC Signal (can be used for singe instruction execution) ‘» ROY Signal (can be used for single cycle execution) ‘* Two Phase Output Clock for Timing of Support Chips SY6503 — 28 Pin Package seg 7 hs.oun Features vat? 2 bso mac]> apew sonic] 2s brows Yeet = Boe ‘© 4K Addressable Bytes of Memory (ABOO-AB11) anes fie woe epee ‘* On-the-chip Clock seqfe nifpoee TAG interna qe ape + TRO Interrupt aac 10 ‘ig Shee © NMI Interrupt 06] va fioer aoe 2 vas + 8 Bit Bi-Directional Date Bus aarq}na sePawe anche sp SY6504 & SY6507 — 28 Pin Package rei a vs qz a RB nov 3 2s| YeeQ 4 2 Features + IRG Interrupt (6504 only) wotfs «ROY Sigal (6507 ony) sap 8 «04 Addressable Bytes of Memory (ABOO-A12) ap '* On-the-chip Clock © 8 Bit Bi-Directional Data BusSynertek, SY6500 SY6505 — 28 Pin Package ssf, aban ny vt]? Bain rors xp wma « freee 4 4K Addressable Bytes of Memory (ABOO-AB1 1) aoc] plows + On-the-chip Clock seit] z pow — ass a = © IRQ Interrupt Pp Ale « ROY signal og “per + 8 Git Bi-Directional Data Bus SY6506 — 28 Pin Package weqr aa his, our) Features vast}2 mfascin eee em . iressable Bytes of Memory wary s 25 Hioeo 4K Addressable Bytes of Memory (ABOO-AB11} Nec® 2s Foes ¢ On-the-chip Clock aoc fiowe awd]? 22 Poss « TRO interrupt aset]e Bowe mt sac] Prose + Two phates off aude lowe restfn sa oer + 8 Bit Bi-Directional Data Bus sone Baan wis ean SY6512 — 40 Package vacft Ya pres nov]? ae 118, our) Features nds xPeo wore Bt + 65K Addressable Bytes of Memory waits enc. © TRG Interrupt sweed> sein i wee slow + A interrupt ede eae ‘= RDY Signal a » fas © 8 Bit Bi-Directional Data Bus pt pow + SYNC Signal weg 7 pow + Two phase input anne as Panis ¢ Data Bus Enable wen xeBanu sut}e aplasia wont}e athe tn» apySynertek, SY6500 SY6513 — 26 Pin Package bar ps Features Baa Bow Bos fons Bows Bose Bross Boss «NMI Interruy aesC] 1 18 Posy CM se weeds a Eiaers + 8 Bit BiDirectional Date Bus er a SP secu saw ‘© 4K Addressable Bytes of Memory (ABO0-AB11) ‘# Two phase clock input «© TAO interrupt SY6514 — 28 Pin Package a Features mods pnw 7 + 8K Addressable Bytes of Memory (ABDO-AB12) ame Blow aed) ios + Two phase clock input seats 2 foee auc] flow + TRG tntoreune sest{re ——tpoes ‘etfs spoon sede frame + 8Bit Bi Directional Date Bus wets tepaarn rte is paso SY6515 — 28 Pin Package Features qa ase macs 25 foto # 4K Addressable Bytes of Memory (ABO0-AB11) Yee» 2s Poor ade ene # Two phase clock input, 02] a 2» fos aaatfo 20 Pows + TRG interrupt asatfo io Foee asst] 18 oer se cha 8 Bit Bi Directional Data Bus serq}is 1s frase aseChie 1s fraseSynertek, S¥6500 Clock Generation Circuits* refer to Synertek SY6500 Applicat (CTS Knight MP Series or equivalents. Information Note AN2, Most [7 =x. oseiaroncncur TT “awiotavzonscmeor 7 tone THLPatKAGe REQUIRED) {one #7 PACKAGE REQUIRED) 1 ! i sp ies00) BT er ieste cavera_[_OvT#UT FREQUENCY racaueney [2 4ertel SY65C02 k CMOS 8-Bit Microprocessor Family PRELIMINARY Features + High Performance nell HCMOS Family of ExernolSingle-Phase Clock Input an RC Network, Microprocessors or 8 Crystal Grcuit, + Low Power Consumption, 4 mA at 1 Mie, 10 uA in + 12,3 or MHz Operation ‘Standby Operation Allowing Battery Operation '* Advanced Memory Access Timing Option * Pin and Software Compatible with the NMOS 6500 — Early Address Valid Allows High Speed + Improved Sottware Ponarmance Microprocéssor Use with Slow Memories 27 New Operation Codes —_ Early Wite Data for Dynamic Memories = 16 Addressing Modes + Decimal and Binary arithmetic - 66 Microprocessor Instructions. © Programmable Stack Pointer — 178 Total Operation Codes © Variable Length Stack + External of On-Board Clock Generation + Improved Operational Cepabiities =" On-Board Clock Generator can be Driven by an Description The CMOS 65CO2 microprocessor is compatible with the Not only isthe 65CD2 a tow power version of the popular NMOS 6500 family of microprocessors This 8-bit micropro. 6500 microprocessor also hes these new Yeates, Abit cessor unit designed in Synertek’s proprietary high to sate the RW line, adress and data us for DMA performance Nowell slcon gate technology offers higher applications. Improved Tace specs allowing use with slower performance than the original NMOS 6502. The design memory devices. A new optional output enhancing mult allows for operating frequencies up to 4 MHz. and below || processing capabliyies Two new addressing modes, an Me further reducing it already low power consumption. larger instruction set providing the user with more compact ; programming capabiiies, Pin Configuration Block Diagram svescoz el = T mean it tor od — e 7 | AE eI a] | | LLEeT bk se Aly 2 ae if =i cy El : iL Tis a FigureSynertek, SY65C02 Absolute Maximum Ratings ‘Comment* (Wop = 5.0V # 5%, Vsg = OV, Ta = 0°C t0 70°C) ‘Stresses above those listed under “Absolute Maximum Rat Supply Voltage (Voo} +++ "0.310+7.0V ngs” may cause permanent damage to the device. This is a Input Voitage (Vin) + -0.310+7.0V stress rating only and functional operation of the device at Operating Temperature (Ta) «+ - 0°C10+70°C these or at any other condition above those indicated in the Storage Temperature (Tra) « “55°C to+150°C operational sections of this specification is not implied Pin Function Pin Function Pin Function AoAve ‘Adaress Bus 50" ‘Set Overfiow Do-Dy Data Bus, NC No Connection 7 ig Interrupt Request RAW Read/Write ROY" Ready Voo Power Supply (*8V) ic ‘Memory Lock Vss. Internal Logic Ground Na Non-Maskable Interrupt 0 Clock Input ‘SYNC ‘Synchronize ude Clock Output eS Reset “This pin has an optional internal pullup for a No Connect condition DC Characteristics ‘Symbol Min, Typ. Max. Unit input High Voltage ‘0 (IN) Vin Vg +24 = Vo v AES, NMI, RDY, IO, Data, $.0. Vss+2.0 = = v Input Low Voltage 0 (IN) Va Vos 0.3 = Vs +04 v RES, NMI, ROY, iRG, Data, S.0. = = Vss +08 v Input Leakage Current (Win= 0 t0 8.25V, Voo = 5.25V) Iw With Pullups -30 - +10 uA Without Pultlups = = 1.0 uA Three State (Off Stato) Input Current (Win = 0.4 t0 2.4V, Vec = 5.25V) Data Lines rst = = 10. 2A ‘Output High Voltage lou = =100 wAde, Vop = 4.78V, SYNC, Data, AprArs, R/W) Vou Ves +24 = = v ‘Output Low Voltage (lo. = 1.6 mAde, Vo SYNC, Data, AgrArs, R/W) You = = Vss +04 v Supply Current f= 1 MHz Top = = a mA Supply Current f=2 MHz too. = = 8 mA Capacitance c pF Cw - - 5 - 2 10 Ags. B/W, SYNC Cour = = 10 (IN) Co (IND = = 10ynertek. SY65C02 Microprocessor Operational Enhancements Function NMOS 6502 Microprocessor ‘SY65C02 Microprocessor Indexed addressing across page boundary. Extra read of invalid address. Extra read of last instruction byte Execution of invalid op codes. ‘Some terminate only by reset, Results are undefined. ‘All are NOPS (reserved for future use) Op Code Bytes Cycles x2 2 X3, X7, XB, XF 1 44 2 54, D4, Fa. 2 8c 3 Dc, Fe 3 PORO=N ‘Jump indireet, operané XxFF. Page address does not increment Page address increments and adds one additional cycle. Read/modify/write instructions at effective address, (One read and two write cycles Two read and one write eyele. Decimal fag Indeterminate after reset, Initialized to binary mode (D = 0) after reset and interrupts, Flags after decimal operation, Invalid N, V andZ flags. Valid flag adds one additional cycle. Interrupt after fetch of BRK instruc: tion Interrupt vector is loaded, BRK vector is ignored, BAK is executed, then interrupt is executed, Microprocessor Hardware Enhancements Function NMOS 6502 sY6sC02 ‘Assertion of Ready ROY during write operations. Tgnored, ‘Stops processor during &. ‘only pins (IR, NMI, ‘Must be connected to low impedance signal to avoid noise problems. Connected internally by a high resistance to Vpp (approximately 250K ohm) New Instruction Mnemonics HEX Mnemonic Description 80 BRA Branch relative always [Relative] 3A DEA Decrement accumulator [Accum] 1A INA Increment accumulator [Accum] DA PHX Push X on stack [Implied] 5A PHY Push Y on stack [Implied] Fa PLX Pull X from stack [Implied] 7A PLY Pull ¥ from stack [Implied] 9c siz ‘Store zero (Absolute) 9€ siz Store zero (ABS, XI 64 siz Store zero (Zero Page] 74 st Store zero [ZPG, x] 1c TRB Test and reset memory bits with accumulator [Absolute] 14 TRE Test and reset memory bits with accumulator [Zero page] oc TSB Test and set memory bits with accumulator [Absolute] 04 TSB Test and set memory bits with accumulator [Zero page] 89 BIT Test immediate with accumulator (IMMEDIATE]Dumerick, sY65C02 Additional Instruction Addressing Modes HEX ‘Mnemonic 72 ‘ADC ‘Add memory to accumulator with carry (2PG}| 32 AND ‘AND" memory with accumulator [ZPG)} 3c Bir Test memory bits with accumulator ABS, X) 34 Bir Test memory bits with accumulator [ZPG, X] bz cmp ‘Compare memory and accumulator (Z2PG)) 52 OR “Exclusive OR” memory with accumulator (ZPG)} 7c MP Jump (New addressing mode) [ABS(IND, X)} 82 LDA Load accumulator with memory [(ZPG)} 12 ORA “OR memory with accumulator (ZPG)) F2 sec Subtract memory from accumulator with borrow [(2PG}] 92 STA Store accumulator in memory {(ZPG)] a Ty REF €5C02 chy e2our REF GSCIZ 62m scr Aacag, sweat WRITE DATA Figure 2. AC Characteristics, SY65C02Sumertek, SY65C02 AC Characteristics, S¥65C02 Vpp = 5.0 v + 5%, Ta= 40°C to 485°C 1 MHz 2 MHz ‘3 MHz ‘4 MHz Parameter Symbol_[ Min. | Max. | Min. [ Max. | Min. | Max. | Min. | Max. | Unit Delay Time, 20 (IN) to #2 (OUT) tooo | — | 100 | — | 100 too [ — [100 [ns Delay Time, #2 (IN) to 62 (OUT) tow | — | 75 | — | 7 7% | — | 7% | 1s Delay Time, #1 (OUT) to 62 (OUT) tor | — | 50 | — [50 | — | 50 | — [50 | as Cycle Time torean_| 10 | bc [oso| oc [oss] oc foas| oc | us Clock Pulse Width Low tewamno | 470 | — | 240 | — [160 — [115] — | ns Clock Pulse Width High temas | 470 | — [240 | — [ie0[ — [115] — | ns [Fall Time, Rise Time tron teow | — | 25 [| — | 25 | — [is [ — [16 | as ‘Address Hold Time w | 30 [— | 30[— [iw f—][0] — | os ‘Address Setup Time twos | — | 225 | — [tao [ — [10| — | 90 | ws ‘Access Time tcc | 650[ — |310| — [170] — [110[ — | ws Read Data Hold Time tom | 10 | — | 10 | — [| —|[10|— | os Read Data Setup Time tosa_| 100[ — [ 50 | — | 50 | — | 80 | — | ws Write Data Delay Time twos | — | 175] — | 100] — | 7 | — | 70 | ve Write Data Hold Time tom | 30 | — | 30 | — [ 30] — | 30] — | ns 50 Setup Time tso__| 100] — | 60 as [ — [25 | — [os Processor Control Setup Time tecs__| 200[ — | 200 iso] — [120] — | nsSY65C02 | ACCUMULATOR A INDEX REGISTER x 9 PROCESSOR STATUS REQ" [cesne {___ ra orsaave 1 -o1sao.e PROGRAM COUNTER PC Leach Aa J BRK comAaND 1 = BAK OVERFLow = rnUE s Goedel) NEGATIVE 1 = NEG. Figure 4, Microprocessor Programming Model Functional Description Timing Control The timing control unit keeps track of the instruction cycle being monitored. The unit is set to zero each time an instruction fetch is executed and is advanced at the begin- ning of each phase one clock pulse for as many cycles as is required to complete the instruction. Each data transfer which takes place between the registers depends upon decoding the contents of both the instruction register and the timing contro! unit. Program Counter The 16-bit program counter provides the addresses which step the microprocessor through sequential instructions in a program, Each time the microprocessor fetches an instruction from program memory, the lower byte of the program counter (PCL) is placed on the low-order bits of the address bus and the higher byte of the program counter (PCH) is placed on the high-order 8 bits. The counter is incremented each time an instruction or data is fetched from program memory. Instruction Register and Decode Instructions fetched from memory are gated onto the inter- nal data bus. These instructions are latched into the instruction register, then decoded, along with timing and interrupt signals, to generate control signals for the various registers. Arithmetic and Logic Unit (ALU) All arithmetic and logic operations take place in the ALU including incrementing and decrementing internal registers (except the program counter), The ALU has no internal memory and is used only to perform logical and transient numerical operations. Accumulator ‘The accumulator is a general purpose 8-bit register that stores the results of most arithmetic and logic operations, and in addition, the accumulator usually contains one of the two data words used in these operations. Index Registers There are two 8-bit index registers (X and Y), which may be Used to count program steps or to provide an index value to bbe used in generating an effective address. When executing an instruction which specifies indexed addressing, the CPU fetches the op code and the base address, and modifies the address by adding the index reg- ister to it prior to performing the desired operation. Pre-or post-indexing of indirect addresses is possibla(see address- jing modes), Stack Pointer The stack pointer is an 8-bit register used to control the addressing of the variable-length stack on page one. The stack pointer is automatically incremented and decremented under control of the microprocessor to perform stack ‘manipulations under direction of either the program or interrupts (NMI and [RG). The stack allows simple imple~ mentation of nested subroutines and multiple level Interrupts. The stack pointer should be initialized before any interrupts or stack operations occur. Processor Status Register ‘The B-bit processor status register contains seven status flags. Some of the flags are controlled by the program, oth- ers may be controlled both by the program and the CPU. The 6500 instruction set contains 2 number of conditional branch instructions which are designed to allow testing of these flags (see microprocessor programming model), ‘CLK (INI OF 0 IN at mt @ 1 ch caester L {8C (oUT) OR gt 1OUT Figure 5 (a) Crystal Circuit for Internal Oscillator Figure 5 (b). Suggested RC Network Configuration for tnternal Oscillatorertek, SY65C02 ‘Addressing Modes Fifteen addressing modes are available to the user of the ‘SY65CO2 microprocessor. The addressing modes are des cribed in the following paragraphs: Implied Addressing (Implied) In the implied addressing mode, the address containing the operand is implicitly stated in the operation code of the instruction. Accumulator Addressing (Accum) This form of addressing is represented with a one byte instruction and implies an operation on the accumulator. Immediate Addressing (Immediate) With immediate addressing, the operand is contained in the ‘second byte of the instruction; no further memory address- ing is required Absolute Addressing (Absolute) For absolute addressing, the second byte of the instruction specifies the eight low-order bits of the effective address, while the third byte specifies the eight high-order bits. Therefore, this addressing mode allows access to the total 64K bytes of addressable memory. Zero Page Addressing (Zero Page} Zero page addressing allows shorter code and execution times by only fetching the second byte of the instruction ‘and assuming a zero high address byte. The careful use of zero page addressing can result in significant increase in code efficiency. Absolute Indexed Addressing (ABS, X or ABS, Y) Absolute indexed addressing is used in conjunction with X ‘or Y index register and is referred to as “Absolute, X," and “Absolute, Y." The effective address is formed by adding the contents of X or ¥ to the address contained in the second ‘and third bytes of the instruction. This mode allows the index register to contain the index or count value and the instruction to contain the base address. This type of index- ing allows any location referencing and the index to modify ‘multiple fields, resulting in reduced coding and execution time. Zero Page Indexed Addressing (ZPG, X or ZPG, ¥) Zero page absolute addressing is used in conjunction with the index register and is referred to as “Zero Page, X" or Zero Page, Y.” The effective address is calculated by adding the second byte to the contents of the index register. Since this is a form of “Zero Page” addressing, the content of the ‘second byte references a location in page zero. Additionally, due to the “Zero Page” addressing nature of this mode, no carry is added to the high-order eight bits of memory, and ‘crossing of page boundaries does not occur. Relative Addressing (Relative) Relative addressing is used only with branch instructions; it establishes a destination for the conditional branch. The second byte of the instruction becomes the operand which is an “Offset” added to the contents of the lower eight bits Of the program counter when the counter is set at the next instruction. The range of the offset is ~128 to +127 bytes from the next instruction. Zero Page Indexed Indirect Addressing [(IND, X)) With zero page indexed indirect addressing {usually referred to as indirect X) the second byte of the instruction is added to the contents of the X index register; the carry is dis. carded. The result of this addition points to @ memory location on page zero whose contents is the low-order eight bits of the effective address. The next memory location in page zero contains the high-order eight bits of the effective address. Both memory locations specifying the high- and low-order bytes of the effective address must be in page “Absolute Indexed Indirect Addressing [ABS(IND, XI] (Jump Instruction Only) With absolute indexed indirect addressing the contents of the second and third instruction bytes are added to the X register. The result of this addition, points to a memory loca~ tion containing the lower-order eight bits of the effective ‘address. The next memory location contains the higher ‘order eight bits of the effective address, Indirect Indexed Addressing [(IND), Y] This form of addressing is usually referred to as Indirect, . ‘The second byte of the instruction points to a memory loca- tion in page zero. The contents of this memory location are added to the contents of the Y index register, the result being the fow-order eight bits of the effective address. The carry from this addition is added to the contents of the next page zero memory location, the result being the high-order ‘eight bits of the effective address. "Zero Page Indirect Addressing [(2PG)] In the zero page indirect addressing mode, the second byte ‘of the instruction points to a memory location on page zero containing the low-order byte of the effective address. The next location on page zero contains the high-order byte of the effective address Absolute Indirect Addressing [(ABS)] (Jump Instruction Only) The second byte of the instruction contains the low-order eight bits of a memory location. The high-order eight bits of ‘that memory location is contained in the third byte of the instruction. The contents of the fully specified memory loce tion is the low-order byte of the effective address. The next memory location contains the high-order byte of the effec- tive address which is loaded into the 16 bit program counter. NOTE: * = Naw Adacese ModesSuneiick SY65C02 Signal Description Address Bus (Ag-Ays) Ag-Ais forms a 16-bit address bus for memory and 1/0 exchanges on the data bus. The output of each address line is TTL compatible, capable of driving one standard TTL load and 130 pF Clocks (do, 41, and 42) ‘40 is a TTL level input that is used to generate the internal clocks in the 6502. Two full level output clocks are gener- ated by the 6502. The #2 clock output is in phase with ¢o, The $1 output pin is 180° out of phase with go. (See timing diagram) Data Bus (Dg D7) The data lines (Do-Dz) constitute an 8-bit bidirectional data bus used for data exchanges to and from the device and peripherals. The outputs are three-state buffers capable of driving one TTL load and 130 pF. Interrupt Request (IF) This TTL compatible input requests that an interrupt sequence begin within the microprocessor. The IRQ is sampled during #2 operation; ifthe interrupt fag in the pro- cessor status register is zero, the current instruction is completed and the interrupt sequence begins during y The program counter and processor status register are stored in the stack, The microprocessor will then set the interrupt mask flag high so that no further Is may occur At the end of this eyele, the program counter low will be loaded from address FFFE, and program counter high from location FFFF, transferring program control to the memory vector located at these addresses. The RDY signal must be in the high state for any interrupt to be recognized. A 3K ‘ohm external resistor should be used for proper wire OR operation, Memory Lock (ML) Ina mutiprocessor system, the MAL output indicates the need to defer the rearbitration of the next bus cycle to fensure the integrity of read-modify-write instructions. Ric goes low during ASL, DEC, INC, LSR, ROL, ROR, TRB, TSB memory referencing instructions. This signal is low for the modify and write cytes. Non Maskable Interrupt (NTT) A negative-going edge on this input requests that @ non- maskable interrupt sequence be generated within the microprocessor. The AT is sampled during a: the currant inetruction is completed and the interrupt sequence begins during 65. The program counter is loaded with the interrupt vector from locations FFFA (low byte) and FFB (high byte, thereby transferring program control to the non-maskeble interrupt routine. NOTE: Since this interrupt is non-maskable, another WA can occur before the first is finished. Care should be taken when using NMI to avoid ths, Ready (RDY) This input allows the user to single-cycle the microproces- sor on all cycles including write cycles. A negetive transition to the low state, during or coincident with phase one (¢)), will halt the microprocessor with the output address lines reflecting the current address being fetched. This condition will remain through a subsequent phase two (¢2) in which the ready signal is tow. This feature allows microprocessor interfacing with low-speed memory as well as direct memory access (DMA), Reset (RES) This input is used to reset the microprocessor. Reset must be held low for at least two clock cycles after Vop reaches. ‘operating voltage from a power down. A positive transition ‘on this pin will then cause an initialization sequence to begin. Likewise, after the system has been operating, a low ‘on this line of at least two cycles will cease microprocessing ‘activity, followed by initialization after the positive edge on FES. When a positive edge is detected, there is an initialization ‘sequence lasting six clock eycles. Then the interrupt mask flag is set, the decimal mode is cleared, and the program counter is loaded with the restart vector from locations FFFC (low byte) and FFFD (high byte). This is the start loca- tion for program control. This input should be high in normal operation Read/Write (R/W) This signal is normally in the high state indicating that the ‘microprocessor is reading data from memory or 1/0 bus. In the low state the data bus has valid data from the microp cessor to be stored at the addressed memory location. Set Overflow (80) ‘A negative transition on this line sets the overflow bit in the status code register. The signal is sampled on the trailing edge of oy ‘Synchronize (SYNC) This output line is provided to identify those cycles during which the microprocessor is doing an OP CODE fetch. The SYNC line goes high during 41 of an OP CODE fetch and stays high for the remainder of that cycle. If the ROY line is pulled low during the ¢; clock pulse in which SYNC went high, the processor will stop in its current state and will remain in the state until the RDY line goes high. In this manner, the SYNC signal can be used to control RDY to ‘cause single instruction execution,Sunertek, SY65C02 Instruction Set — Alphabetical Sequence ADC Age Memory to Accumulator win Cary LOY Lote Indes ¥ wth Memory ND "AND" Memory wth Accumulator C&R ShitoOne Rane BSC Shona Cen NOP NG Operation BEC Branch sn Cary Clear Gia “Sa hrary win Accumuator 86S. Srancn on Gary Set BHR Puan Accumsatron Stack EQ Sranen on Rest Zoro PHP Puan Praconsor Status on Stack Sit” Test Memory Bt ih Accumstor Pix Planingor on Sack ML Grenem om osu inva 3 Phy Pash nex Yon Sack ENE Branch on Res Nt Zero PUA Paltaccumudstr om Stack 9, Srenen on Rest Pus PLP Pal rocarsr Stat trom Sack © BhA Branch Anwaye 1s PU Pal ingen rom Stak Shm Fores Beal PLY Palinces rom Stack VC Branen on Overton Cat ROL Rowena eet VS Branch on Overton Set ROA Rotate One Right Sle Ger cury rag nti om ra ECP Shar rrapn sabe Bi 36 _Suotact Memory tram Accumulator wth Soto GL Glee Sveiow Fag SEC Set cary fag Glue Compare Memory aed Accumulator SED. Sst Gavia Moo ex Compare Memery and index SED Setimerrapt Doable Gt SEC Secrement ty Ove STK Store ndex Xe Nemary Sey Becrement inter ¥ by One «SIE Stove Zaroin memory |G. incsement by One TAY raneer Accumulator t den IN Incremant inden by One 4¢ TRO Ton ang eset Memory is win Accumulator In Increment nox ¥ 69 Ons 158 Test ana Set amary Be wih Accumulator Me Jumpto New Locaton Sk Tansar Stace Ponterto Index JSR Jump o New Location Saving Return Adare THA Tana ngee to accumulntor ws o | ea s [6 |r] e |o la o tele o [ark | ona ona | ast pup | ona | Ast ona | ASL 3 in. x _ zo9_| 259 wmm [a ars_| abs | 1 [eee | ona ona | ASL cre | ona ona | ase 7 Lort_| ine 259. | 299. abs. abs, x_| abs, x 2 | ysr | AND ‘ano | ROL pup | aNd | ROL ‘ano | ROL 2 [ave ina, x zp9_| 29 im [oA ans_| abe 3 | em | AND ‘aN | ROL sec | ANO ‘ano | ROL 3 rat__| ing ¥ 200. | 2p9.x | a8.¥ ans. x | abs, x 4 [an | cor cor | isa | | era | cor | tsa up | con | 13h @ nd, x _ z9_| 200 acs | abs _| avs s [ave | cor cor | isa eu OR | ish 5 ret | soa. 709. | 209. abe. X_| abs. 6 [ats | aoc ‘aoc | ROR PLA amp | aoc | ROR 6 0. 209 | 209 ing | abs _| aps 7 [evs | aoc ‘aoc | ROR Ser ‘aoc | ROR 7 rel | ing. ¥ 09. | 299. aps. x_| as. x @ STA sta | stx DEY sty | sma | six a ind, x z09_| 209 avs | abs | abs @ [acc | sta sta | stx Ta | sta | 135 Fm sta ° re | indy 209. | 209, abs. Bowe os. x & [vor | toa | Lox toa | 10x Tay | toa | ax uoy | wpa | Lox a imm_| 9a. x_| im z09_| 29 imm abs_| ats abs 8 [secs | ton ey toa | Lox cw | ua | T3x tov | toa | 10x 8 | nay (AS zo9.X | 209. abs. ¥ abs, x | abs. x | ats, ¥ © | ory | cur comp | 06 iy [cmp | ex cpr | cmp | o€c c ievm_| ing. x z09_|_ 209 im aos_| abe _| abs 3 | ene | cur come | 0Ec co | cue emp | 0ec ° co_| inv z09.x | 209, abs. ¥ avs. x_| a8, & [orx | sec px | sec | inc wx | sac | NoP cx | ssc | inc = imm_| na. x zo9_| 209 | 200 irom av_| abe | abe * [sea | sec ‘sec | inc seo | sac ‘sec | Inc F ret_| oa. 209. | 299. abs. abs. x_| abs. of + [z{sts+[sfe«fr>se fs f[altsfe] of] ec lr Note: MD = New Op Codes Figure 6. Microprocessor Op Code TableSunertek, Operational Codes, Execution Time, and Memory Requirements IN bit equals memory bit? prior 4. V bit equals memory bit 6 prior to execution. execution, ee 3 elt aS 8 Eee set fades fe Aster nee er re eH rere Seite br el | | el moe Ba » pl || sb Rg |e ise Peal eeu a} | eeebasezes ae |] ee fk Jenn eel rv tot fe j es : ace lh Bes: now Tad 110 enous oe X Inder + 1g 9 Reso 2 Add to" teres omen Y Intent 5 Siteact Ro. Sre féd2t0"n aren curstoatereber.—-X Aetnuiio fed tig enor 2. Sta 110 cra ose ft femor pereecie ison mS Memon 9 Ms Memory per steck pointer 4 Exclusive orpynertek, SY65C02 Package Availability 40 Pin Molded DIP Ordering Information sy PREFIX P 65CKX x PACKAGE DEVICE TYPE SPEED RANGE P— Molded DIP No Designator—1 Miz a2 Mite BSH ena MieAPPENDIX A SUMMARY OF SINGLE CYCLE EXECUTION This section contains an outline of the data on both the address bus and the data bus for each cycle of the various processor instructions. It tells the system designer exactly what to expect while single cycling through a program. Note that the processor will not stop in any cycle where R/W is a 0 (write cycle). Instead, it will go right into the next read cycle and stop there. For this reason, some instructions may appear to be shorter than indicated here. All instructions begin with TO and the fetch of the OP CODE and continue through the required number of cycles until the next T0 and the fetch of the next OP CODE. While the basic terminology used in this appendix is discussed in the Pro- gramming Manual, it has been defined below for ease of reference while studying Single Cycle Execution. OP CODE--The first byte of the instruction containing the operator and mode of address. OPERAND--The data on which the operation specified in the OP CODE is performed. BASE ADDRESS--The address in Indexed addressing modes which specifies the loca~ tion in memory to which indexing is referenced. The high order of byte of the base address (ABO8 to AB15) is BAH (Base Address High) and the low order byte of the base address (ABOO to ABO7) is BAL (Base Address Low). EFFECTIVE ADDRESS--The destination in memory in which data is to be found. The effective address may be loaded directly as in the case of Page Zero and Absolute Addressing or may be calculated as in Indexing operations. The high order byte of the effective address (ABO8 to AB15) is ADH and the low order byte of the effective address (ABOO to ABO7) is ADL. INDIRECT ADDRESS-~The address found in the operand of instructions utilizing (Indirect) ,¥ which contains the low order byte of the base address. IAH and IAL represent the high and low order bytes. JUMP ADDRESS--The value to be loaded into Program Counter as a result of a Jump instruction.A. 1. SINGLE BYTE INSTRUCTIONS ASL DEX NOP TAX TYA cL DEY ROL TAY cLD INX SEC ‘TSX CLI INY SED TxA cLv LSR SEL Txs These single byte instructions require two cycles to execute. During the second cycle the address of the next instruction in program sequence will be placed on the address bus. However, the OP CODE which appears on the data bus during the second cycle will be ignored. This same instruction will be fetched on the following cycle at which time it will be decoded and executed. The ASL ROL and LSR instructions apply to the accumulator mode of address. Ta Address Bus Data Bus R/W Comments 70 PC OP CODE 1 Fetch OP CODE TL PC +1 OP CODE 1 (iscarded) T0 PC +1 OP CODE 1 Next Instruction A, 2, INTERNAL EXECUTION ON MEMORY DATA ADC cM EOR LDY AND CPX LDA ORA BIT cPY LDX SBC The instructions listed above will execute by performing operations in- side the microprocessor using data fetched from the effective address. This total operation requires three steps. The first step (one cycle) is the OP CODE fetch. The second (zero to four cycles) is the calculation of an effective address. The final step is the fetching of the data from the effective address Execution of the instruction takes place during the fetching and decoding of the next instruction.A. A. zine an AL 2.4, Immediate Addressing (2 cycles) In 70 TL 0 Address Bus PC PO+1 PC +2 Data Bus = R/W OP CODE L Data 1 OP CODE 1 Zero Page Addressing (3 cycles) In 70 TL 12 70 Address Bus PC PC +1 00, ADL PC +2 Data Bus R/W OP CODE 1 ADL 1L Data 1 OP CODE 1 Absolute Addressing (4 cycles) mn 70 TL 12 13 TO Address Bus PC PC+1 PC + 2 ADH, ADL PC +3 Data Bus R/W OP CODE 1 ADL, ADE L Data 1 OP CODE L Indirect, X Addressing (6 cycles) mn 10 TL 12 13 TH 15 TO Address Bus PC PC +1 00, BAL 00, BAL + X 00, BAL + X41 ADH, ADL PC +2 Data Bus R/W oP CODE 1 BAL 1 Data 1 (Discarded) ADL 1 ADH 1 Data 1 OP CODE 1 Comments. Fetch OP CODE Fetch Data Next Instruction Fetch OP CODE Fetch Effective Address Fetch Data Next Instruction Comments. Fetch OP CODE Fetch low order Effective Address byte Fetch high order Effective Address byte Fetch Data Next Instruction Comments Fetch OP CODE Fetch Page Zero Base Address Fetch low order byte of Effective Address Fetch high order byte of Effective Address Fetch Data Next InstructionA. 2.5. AL 2.6. Absolute, X or Absolute 12 13 14x 70 Address Bus Data Bus PC OP CODE Po +1 BAL PC +2 BAH ADL: BAL + Data* index register ADH: BAH + C ADL: BAL + index register Data ADH: BAH + 1 PC + 3 oP CODE ¥ Addressiny 4 or 5 cycles R/W 1 1 1 Comments Fetch OP CODE Fetch low order byte of Base Address Fetch high order byte of Base Address Fetch data (no page cross- ing) Carry is @ or 1 as re~ quired from previous add operation Fetch data from next page Next Instruction *I£ the page boundary is crossed in the indexing operation, the data fetched in T3 is ignored. cycle is bypassed. Zero Page, X or Zero Page, Y Addressing Modes Tn Address Bus Data Bus R/W 70 PC OP CODE 1 T1 PO +1 BAL 1 12 00, BAL, Data 1 (Discarded) 13 00, BAL + Data 1 index register 70 PC +2 OP CODE 1 I£ page boundary is not crossed, the T4 4 cycles Comments Fetch OP CODE Fetch Page Zero Base Address Fetch Data (no page cross- ing) Next InstructionA, 2.7. Indirect, Y Addressing Mode (5 or 6 cycles) In Address Bus Data Bus R/W Comments 0 PC OP CODE 1 Fetch OP CODE TL PO +1 TAL 1 Fetch Page Zero Indirect Address 12 00, IAL BAL 1 Fetch low order byte of Base Address 13 00, IAL +1 BAH 1 Fetch high order byte of Base Address 1% ADL: BAL + ¥ Data* 1 Fetch Data from same page ADH: BAH + C Carry is 0 or 1 as re- quired from previous add operation ‘Tse ADL: BAL + ¥ Data 1 Fetch Data from next page ADH: BAH + 1 10 PC +2 OP CODE 1 Next Instruction *If page boundary is crossed in indexing operation, the data fetch in T4 is ignored. If page boundary is not crossed, the TS cycle is by- passed. A. 3. STORE OPERATIONS STA STX STY The specific steps taken in the Store Operations are very similar to those taken in the previous group (Internal execution on memory data). However, in the Store Operation, the fetch of data is replaced by a WRITE (R/W = 0) cycle. No overlapping occurs and no shortening of the instruction time occurs on indexing operations. A. 3.1. Zero Page Addressing (3 cycles m Address Bus Data Bus R/W Comments. ‘10 PC OP CODE 1 Fetch OP CODE TL Po +1 ADL 1 Fetch Zero Page Effective Address 12 00, ADL Data oO Write internal register to memory TO PC +2 OP CODE 1 Next InstructionA. 3.2. A. 3.3. AL 3.4. Absolute Addressin, 4 cycles) Tn Address Bus Data Bus R/W Comments 0 PC OP CODE 1 Fetch OP CODE Tl PC +1 ADL 1 Fetch low order byte of Effective Address 12 PC +2 ADH 1 Fetch high order byte of Effective Address 13 ADH, ADL Data 0 Write internal register to memory T0 PC +3 OP CODE 1 Next Instruction Indirect, X Addressing (6 cycles) Tn Address Bus Data Bus R/W Comments 0 PC OP CODE 1 Fetch OP CODE TL PC +1 BAL 1 Fetch Page Zero Base Address 12 00, BAL Data 1 (Discarded) 13 00, BAL +X ADL 1 Fetch low order byte of Effective Address 4 00, BAL + ADE 1 Fetch high order byte of X+1 Effective Address 75 ADH, ADL Data 0 Write internal register to memory 70 PC +2 OP CODE 1 Next Instruction Absolute, X or Absolute, Y Addressing (5 cycles T Address Bus Data Bus R/W Comments 70 Pc OP CODE a Fetch OP CODE TL PC +1 BAL 1 Fetch low order byte of Base Address 12 PC + 2 BAH 1 Fetch high order byte of Base Address 13 ADL: BAL + Data 1 index (Discarded) register ADH: BAH + C 14 ADH, ADL Data 0 Write internal register to memory 70 PC + 3 OP CODE 1 Next InstructionA. 3.5. Zero Page, X or Zero Page, ¥ Addressing Modes (4 cycles) Tm 10 TL 72 13 10 A. 3.6. a) 10 TL 12 13 14 TS 10 Address Bus Data Bus PC OP CODE PC +1 BAL 00, BAL Data (Discarded) ADL: BAL + Data index register PC +2 OP CODE Address Bus Data Bus PC OP CODE PC +1 TAL 00, TAL BAL 00, IAL +1 BAH ADL: BAL + Y Data (Discarded) ADH: BAH ADH, ADL Data PC +2 OP CODE READ--MODIFY--WRITE OPERATIONS ASL DEC INC LSR ROL ROR R/W 1 Indirect, Y Addressing Mode (6 cycles) RW 1 1 Comments Fetch OP CODE Fetch Page Zero Base Address Write internal register to memory Next Instruction Comments. Fetch OP CODE Fetch Page Zero Indirect Address Fetch low order byte of Base Address Fetch high order byte of Base Address Write Internal Register to memory Next Instruction The Read--Modify--Write operations involve the loading of operands from the operand address, modification of the operand and the resulting modi- fied data being stored in the original location. Note: The ROR instruction will be available on MCS650X microprocessors after June, 1976,AL 4.1. AL 4.2, AL 43. Zero Page Addressing (5 cycles) mm 10 TL 12 13 14 10 Address Bus PC PC +1 00, ADL 00, ADL 00, ADL PC +2 Data Bus B/W OP CODE 1 ADL 1 Data Data 0 Modified 0 Data OP CODE 1 Absolute Addressing (6 cycles) To 10 T 12 13 TH 15 @ Address Bus PC PO +1 PC +2 ADH, ADL ADH, ADL ADH, ADL PC +3 Data Bus R/W OP CODE 1 ADL 1 ADH 1 Data Data Modified 0 Data OP CODE 1 Zero Page, X Addressing (6 cycles) mm 10 Tl 12 13 14 15 ™ Address Bus PC PC +1 00, BAL ADL: BAL + X (without carry) ADL: BAL + X (without carry) ADL: BAL + X (without carry) PC +2 Data Bus R/W OP CODE 1 BAL Data 1 (Discarded Data 1 Data 0 Modified 0 Data OP CODE 1 A=8 Comments Fetch OP CODE Fetch Page Zero Effective Address Fetch Data Write modified Data back to memory Next Instruction Comments Fetch OP CODE Fetch low order byte of Effective Address Fetch high order byte of Effective Address Write modified Data back into memory Next Instruction Comments Fetch OP CODE Fetch Page Zero Base Address Fetch Data Write modified Data back into memory Next InstructionA. 4.4. Absolute, X Addressing (7 cycles) Tm Address Bus Data Bus B/W Comments 10 PC OP CODE 1 Fetch OP CODE TL PC +1 BAL 1 Fetch low order byte of Base Address 12 PC +2 BAH 1 Fetch high order byte of Base Address 13 ADL: BAL +X Data 1 (Discarded) ADH: BAH + C 1% ADL: BAL +X Data al Fetch Data ADH: BAH + C TS ADH, ADL Data 0 16 ADH, ADL Modified 0 Write modified Data back Data into memory TO PC +3 OP CODE i New Instruction A. 5. MISCELLANEOUS OPERATIONS BCC BRK PHP BCS BYC PLA BEQ BVS PLP BMI IMP RII BNE ISR RTS BPL PHA A. 5.1. Push Operation--PHP, PHA (3 cycles) To Address Bus Data Bus R/W Comments TO PC OP CODE 1 Fetch OP CODE TL PC +1 OP CODE 1 (Discarded) 12 Stack Pointer* Data 0 Write Internal Register into Stack bu) Po+1 OP CODE 1 Next Instruction *Subsequently referred to as "Stack Ptr."A. 5.3. Pull Operations--PLP, PLA (4 cycles) Fetch Data from Stack Fetch low order byte of Subroutine Address Push high order byte of program counter to Stack Push low order byte of program counter to Stack Fetch high order byte of Subroutine Address Ta Address Bus Data Bus R/W Comments TO PC OP CODE 1 Fetch OP CODE Tl PC +1 OP CODE 1 (@iscarded) T2 Stack Ptr. Data 1 (Discarded) 13 Stack Ptr. +1 Data 1 TO are OP CODE 1 Next Instruction Jump to Subroutine--JSR (6 cycles) Th Address Bus Data Bus R/W Comments TO PC OP CODE 1 Fetch OP CODE Tl ta ae ADL 1 12 Stack Ptr. Data 1 (Discarded) 13 Stack Ptr. PCH 0 14 Stack Ptr. - 1 PCL 0 TS ae ADH a 10 Subroutine OP CODE 1 Next Instruction Address (ADH, ADL)AL 5.4, A. 5.5. Break Operation-~ (Hardware Interrupt)-BRK (7 cycles) mm 10 T 12 13 Th 15 16 10 Return from Interrupt-RIL In 0 Tl 12 13 14 1S 10 Address Bus PC Po +1 (PC on hard- ware inter~ rupt) Stack Ptr. Stack Ptr. - 1 Stack Ptr. - 2 FFFE (NMI-FFFA) (RES-FFFC) FFFF (NMI-FFFB) (RES-FFFD) Interrupt Vec~ tor (ADH, ADL) Address Bus PC PC +1 Stack Ptr. Stack Ptr. + 1 Stack Ptr. + 2 Stack Ptr. + 3 PCH, PCL Data Bus OP CODE Data (Discarded) PCH PCL ADL ADH OP CODE Data Bus OP CODE Data (Discarded) Data (Discarded) Data Data Data OP CODE 6 cycles BMW 1 aw 1 Comments Fetch BRK OP CODE (or force BRK) Push high order byte of program counter to Stack Push low order byte of program counter to Stack Push Status Register to Stack Fetch low order byte of interrupt vector Fetch high order byte of interrupt vector Next Instruction Comments Fetch OP CODE Pull P from Stack Pull PCL from Stack Pull PCH from Stack Next InstructionA. 5.6, Jump Operation--JMP A.5.6.1. Absols In Address Bus Data Bus R/W Comments 70 PC OP CODE 1 Fetch OP CODE Tl PC +1 ADL 1 Fetch low order byte of Jump Address 12 PC +2 ADH 1 Fetch high order byte of Jump Address TO ADH, ADL OP CODE 1 Next Instruction A.5.6.2. Indirect Addressing Mode (5 cycles) Tn Address Bus Data Bus R/W Comments 10 PC OP CODE 1 Fetch OP CODE Tl PC +1 TAL 1 Fetch low order byte of Indirect Address 12 PC +2 TAH 1 Fetch high order byte of Indirect Address 13 TAH, TAL ADL 1 Fetch low order byte of Jump Address TH TAH, TAL +1 © ADH 1 Fetch high order byte of Jump Address TO ADH, ADL OP CODE 1 Next Instruction A. 5.7. Return from Subroutine--RTS (6 cycles) Tm Address Bus Data Bus R/W Comments 70 PC OP CODE 1 Fetch OP CODE TL PC +1 Data 1 (Discarded) 12 Stack Ptr. Data 1 (Discarded) 13 Stack Ptr. +1 PCL 1 Pull PCL from Stack 14 Stack Ptr. +2 PCH 1 Pull PCH from Stack 15 PCH, PCL (from Data 1 Stack) (Discarded) 70 PCH, PCL+1 OP CODE a Next InstructionA. 5.8. Branch Operation-~BCC BCS, BEQ, BMI, BNE, BPL, BVC, BVS (2, 3, or 4 cycles) Fetch Branch Offset Offset Added to Program ™m Address Bus Data Bus R/W Comments TO PC OP CODE 1 Fetch OP CODE Tl PCat Offset 12 eeaPCetazec OP CODE a offset (w/o Counter carry) T3** PC +2 + OP CODE 1 offset (with carry) *Skip if branch not taken Carry Added **Skip if branch not taken; skip if branch operation doesn't cross page boundary.