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College of Engineering KIET, Karachi: I. Objectives

This document provides instructions for a lab assignment on advanced digital system design. Students are asked to: 1) Write a VHDL code for a BCD to 7-segment decoder and implement it on an FPGA development board using slide switches as input and a 7-segment display as output. 2) Explore using two 7-segment displays to show numbers greater than 9 as two-digit decimal numbers by using an advanced multiplexing technique as the data lines are only 8-bit. 3) Code snippets and hints are provided on clock division and multiplexing the output to drive multiple 7-segment displays. Help will also be available during the lab.

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Abdul Muqeet Ahmed Khan
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113 views2 pages

College of Engineering KIET, Karachi: I. Objectives

This document provides instructions for a lab assignment on advanced digital system design. Students are asked to: 1) Write a VHDL code for a BCD to 7-segment decoder and implement it on an FPGA development board using slide switches as input and a 7-segment display as output. 2) Explore using two 7-segment displays to show numbers greater than 9 as two-digit decimal numbers by using an advanced multiplexing technique as the data lines are only 8-bit. 3) Code snippets and hints are provided on clock division and multiplexing the output to drive multiple 7-segment displays. Help will also be available during the lab.

Uploaded by

Abdul Muqeet Ahmed Khan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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College of Engineering

KIET, Karachi

Advanced Digital
System Design

04

I. Objectives:

To write a BCD to 7-segment decoder


To describe the use and syntax of User ( Implementation) Constraint File
To extend the usage of Nexys2 board
II. Submission: submit by email within 5 days after the lab. Email subject format
should be Lab04_XXXX_YYYY_ZZZZ.

III. Background:

IV.

FPGA development board reference manual and lectures on VHDL

Procedure (part A)

Write VHDL code for BCD to seven segment decoder and implement it on
Nexys2 board making use of slide switches as input and one of the 7-segment display as
its output.

V.

Exploratory Exercises:
1. Use two seven segment displays to show numbers greater than 9 as two
digit decimal numbers.
2. To use more than one seven-segment displays you will have to use
advanced technique as data lines are only 8-bit and are multiplexed. Code
snippets are some hints are given in the following:
Help will also be given during the lab.

Code for Clock division:


-- clock division block
--divides the clock of 50MHz by 64K i.e. down to ~780 Hz
-- to avoid operating seven segment displays at high frequencies (in MHz range)
process (clk50)
begin
if clk50'event and clk50 = '1' then
khertz_count <= std_logic_vector(unsigned(khertz_count) + 1) ;
if khertz_count = "1000000000000000" then
khertz_en <= '1' ;
khertz_count <= (others => '0') ;
else
khertz_en <= '0' ;
end if ;
end if ;
end process ;
Hint!
To try out these single process or multi-process design files, you will have to create appropriate
entities and place the code in the architecture body and declare required signals or variables.

-- This block shows an example to illustrate multiplexing output to more than one 7segments
-- This block shows how to multiplex output to different 7-segments
process (khertz_en, ChangeDigit)
begin
if khertz_en'event and khertz_en = '1' then
ChangeDigit <=std_logic_vector(unsigned(ChangeDigit) + 1);
else
ChangeDigit <= ChangeDigit;
end if ;
case ChangeDigit is
when "00" => SSgSel <= "0111" ; curr <= BCDOut(11 downto 8);--curr <=OutPutToSSG1;
when "01"
=> SSgSel <= "1011" ;
curr <= BCDOut(7 downto 4);--curr <=
OutPutToSSG2;
when "10"
=> SSgSel <= "1101" ;
curr <= BCDOut(3 downto 0);--curr
<=OutPutToSSG3;
when others => SSgSel <= "1110" ; curr <= CandyCount;
--curr <=OutPutToSSG4;
end case;
--Binary to seven-segment decoder
case curr is
--.gfedbca
when "0000" => ssg <= "11000000" ;
when "0001" => ssg <= "11111001" ;
when "0010" => ssg <= "10100100" ;
when "0011" => ssg <= "10110000" ;
when "0100" => ssg <= "10011001" ;
when "0101" => ssg <= "10010010" ;
when "0110" => ssg <= "10000010" ;
when "0111" => ssg <= "11111000" ;
when "1000" => ssg <= "10000000" ;
when "1001" => ssg <= "10010000" ;
when "1010" => ssg <= "10001000" ;
when "1011" => ssg <= "10000011" ;
when "1100" => ssg <= "11000110" ;
when "1101" => ssg <= "10100001" ;
when "1110" => ssg <= "10000110" ;
when "1111" => ssg <= "10001110" ;
when others => ssg <= "11000000" ;
end case ;
end process ;

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