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Coding

This document contains definitions for several digital logic components including a full adder, multiplexer, and multiplier. It defines the components using VHDL code with structural, dataflow, and behavioral architectures. The full adder is defined using two XOR gates and three AND gates. The multiplexer is defined using logic expressions, conditional expressions, and structural components like AND gates. The multiplier contains a datapath component that performs addition and shifting and a controller component to sequence operations.

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bhawna
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107 views43 pages

Coding

This document contains definitions for several digital logic components including a full adder, multiplexer, and multiplier. It defines the components using VHDL code with structural, dataflow, and behavioral architectures. The full adder is defined using two XOR gates and three AND gates. The multiplexer is defined using logic expressions, conditional expressions, and structural components like AND gates. The multiplier contains a datapath component that performs addition and shifting and a controller component to sequence operations.

Uploaded by

bhawna
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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FULL ADDER

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
ENTITY full_adder IS
PORT (a, b, cin : IN std_logic; sum, cout : OUT std_logic);
END ENTITY full_adder;
-ARCHITECTURE expression OF full_adder IS
BEGIN
sum <= a XOR b XOR cin AFTER 0.3 NS;
cout <= (a AND b) OR (a AND cin) OR (b AND cin) AFTER 0.2 NS;
END ARCHITECTURE expression;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Full_Adder is
Port ( A : in std_logic;
B : in std_logic;
Cin : in std_logic;
S : out std_logic;
Cout : out std_logic);
end Full_Adder;
architecture Full_Adder_Architecture of Full_Adder is
-- component declaration
component OR_2
port(A,B: in std_logic;
C : out std_logic);
end component;
component Half_Adder
port(A,B: in std_logic;
S,C: out std_logic);
end component;
signal S1, C1, C2: std_logic;
-- component specification
--for U1,U2: Half_Adder use entity
work.Half_Adder(Half_Adder_Architecture);
--for U3 : OR_2 use entity work.OR_2(OR_2_Architecture);
begin
-- component instantiation
U1: Half_Adder port map(A=>A, B=>B, S=>S1, C=>C2);
U2: Half_Adder port map(A=>S1, B=>Cin, S=>S, C=>C1);

U3: OR_2 port map(A=>C1, B=>C2, C=>Cout);


end Full_Adder_Architecture;

ADD 1 BIT
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
ENTITY add_1bit IS
PORT (a, b, ci : IN std_logic; s, co : OUT std_logic);
END ENTITY add_1bit;
-ARCHITECTURE expression OF add_1bit IS
BEGIN
s <= a XOR b XOR ci AFTER 0.3 NS;
co <= (a AND b) OR (a AND ci) OR (b AND ci) AFTER 0.2 NS;
END ARCHITECTURE expression;

MULTIPLEXER
ENTITY multiplexer IS
PORT (a, b, s: IN BIT; w : OUT BIT);
END ENTITY;
-ARCHITECTURE expression OF multiplexer IS
BEGIN
w <= (a AND NOT s) OR (b AND s);
END ARCHITECTURE expression;
-ARCHITECTURE procedural OF multiplexer IS
BEGIN
PROCESS (a, b, s) BEGIN
IF (s = '0') THEN w <= a;
ELSE w <= b;
END IF;
END PROCESS;
END ARCHITECTURE procedural;
-ARCHITECTURE structural OF multiplexer IS
SIGNAL s_bar : BIT;
BEGIN
U1: ENTITY WORK.inv (expression) PORT MAP (s, s_bar);
U2: ENTITY WORK.andor (expression) PORT MAP (a, s_bar, s, b, w);
END ARCHITECTURE structural;

..
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY multiplexer_en IS
PORT (a, b, s, e : IN std_logic; w : OUT std_logic);
END ENTITY;
-ARCHITECTURE conditional OF multiplexer_en IS
BEGIN
w <= 'Z' WHEN e='0' ELSE
(a AND NOT s) OR (b AND s);
END ARCHITECTURE conditional;

..
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY multiplexer8std IS
PORT (sel : IN std_logic;
data1, data0 : IN std_logic_vector (7 DOWNTO 0);
bus1 : OUT std_logic_vector (7 DOWNTO 0));
END ENTITY;
-ARCHITECTURE conditional OF multiplexer8std IS
BEGIN
bus1 <= data1 WHEN sel='1' ELSE
data0 WHEN sel='0' ELSE
"UUUUUUUU";
END ARCHITECTURE conditional;

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY multiplexer_en IS
PORT (a, b, s, e : IN std_logic; w : OUT std_logic);
END ENTITY;
-ARCHITECTURE blocking OF multiplexer_en IS
SIGNAL t : std_logic BUS;
BEGIN
tri: BLOCK (e='1') BEGIN
t <= GUARDED (a AND NOT s) OR (b AND s);
w <= t;
END BLOCK tri;
END ARCHITECTURE blocking;
-ARCHITECTURE timedisconnect OF multiplexer_en IS
SIGNAL t : std_logic BUS;
DISCONNECT t : std_logic AFTER 3.25 NS;
BEGIN
tri: BLOCK (e='1') BEGIN
t <= GUARDED (a AND NOT s) OR (b AND s);
w <= t;
END BLOCK tri;

END ARCHITECTURE timedisconnect;

.
ENTITY multiplexer IS
PORT (a, b, s : IN BIT; w : OUT BIT);
END ENTITY;
--ARCHITECTURE expression OF multiplexer IS
BEGIN
w <= (a AND NOT s) OR (b AND s) AFTER 7 NS;
END ARCHITECTURE expression;
---w
--<=
--(a AND NOT s) OR (b AND s)
--AFTER 7 NS
--;
ARCHITECTURE conditional OF multiplexer IS
BEGIN
w <= a AFTER 7 NS WHEN s='0' ELSE
b AFTER 8 NS;
END ARCHITECTURE conditional;
---w
--<=
--a AFTER 7 NS
--WHEN
--s='0'
--ELSE
--b AFTER 8 NS
--;
-ARCHITECTURE multidelay OF multiplexer IS
BEGIN
w <= '1' AFTER 7 NS WHEN (s='0') AND (a='1')
'0' AFTER 8 NS WHEN (s='0') AND (a='0')
'1' AFTER 5 NS WHEN (s='1') AND (b='1')
'0' AFTER 6 NS WHEN (s='1') AND (b='0')
'0';
END ARCHITECTURE multidelay;
-ARCHITECTURE processing OF multiplexer IS
BEGIN
com: PROCESS (a, b, s) BEGIN
IF s='0' THEN w <= a AFTER 1.4 NS;
ELSE w <= b AFTER 1.5 NS;
END IF;
END PROCESS com;

ELSE
ELSE
ELSE
ELSE

END ARCHITECTURE processing;


---IF
-s='0'
--THEN
-w <= a AFTER 1.4 NS;
--ELSE
-w <= b AFTER 1.5 NS;
--END IF;
-ARCHITECTURE postprocessing OF multiplexer IS
BEGIN
com: POSTPONED PROCESS (a, b, s) BEGIN
IF s='0' THEN w <= a AFTER 1.4 NS;
ELSE w <= b AFTER 1.5 NS;
END IF;
END PROCESS com;
END ARCHITECTURE postprocessing;
-ARCHITECTURE process_wait OF multiplexer IS
BEGIN
com: PROCESS BEGIN
IF s='0' THEN w <= a AFTER 1.4 NS;
ELSE w <= b AFTER 1.5 NS;
END IF;
WAIT ON a, b, s;
END PROCESS com;
END ARCHITECTURE process_wait;
-ARCHITECTURE functional OF multiplexer IS
FUNCTION mux (databits : BIT_VECTOR; sel : BIT_VECTOR) RETURN BIT IS
VARIABLE selint : INTEGER := 0;
BEGIN
FOR i IN sel'LENGTH - 1 DOWNTO 0 LOOP
IF sel (i) = '1' THEN selint := selint + 2**i; END IF;
END LOOP;
RETURN databits (selint);
END FUNCTION mux;
SIGNAL sel : BIT_VECTOR (0 DOWNTO 0);
BEGIN
sel(0) <= s;
w <= mux ((a,b), sel) AFTER 8 NS;
END ARCHITECTURE functional;
----FUNCTION
--mux
--(databits : BIT_VECTOR; sel : BIT_VECTOR)
--RETURN
--BIT
--IS
-VARIABLE selint : INTEGER := 0;

--BEGIN
-FOR i IN sel'LENGTH - 1 DOWNTO 0 LOOP
-IF sel (i) = '1'
-THEN selint := selint + 2**i;
-END IF;
-END LOOP;
-RETURN
-databits (selint)
-;
--END FUNCTION mux;
--ARCHITECTURE functional OF multiplexer IS
FUNCTION int (invec : BIT_VECTOR) RETURN INTEGER IS
VARIABLE tmp : INTEGER := 0;
BEGIN
FOR i IN invec'LENGTH - 1 DOWNTO 0 LOOP
IF invec (i) = '1' THEN
tmp := tmp + 2**i;
END IF;
END LOOP;
RETURN tmp;
END FUNCTION int;
FUNCTION mux (databits : BIT_VECTOR; sel : BIT_VECTOR) RETURN BIT IS
BEGIN
RETURN databits (int(sel));
END FUNCTION mux;
SIGNAL sel : BIT_VECTOR (0 DOWNTO 0);
BEGIN
sel(0) <= s;
w <= mux ((a,b), sel) AFTER 8 NS;
END ARCHITECTURE functional;

LIBRARY utilities;
USE utilities.VerilogLogic.ALL;
ENTITY multiplexer IS
PORT (a, b, s : IN v4l; w : OUT v4l);
END ENTITY;
-ARCHITECTURE booloeanlevel OF multiplexer IS
BEGIN
w <= (a AND NOT s) OR (b AND s);
END ARCHITECTURE booloeanlevel;
---

LIBRARY utilities;
USE utilities.VerilogLogic.ALL;
ENTITY multiplexer_tester IS
END ENTITY;
-ARCHITECTURE timed OF multiplexer_tester IS
SIGNAL a, b, s, w1 : v4l;
BEGIN
UUT1: ENTITY WORK.multiplexer (booloeanlevel) PORT MAP (a, b, s, w1);
a <= '0', '1' AFTER 020 NS, '0' AFTER 065 NS, '1' AFTER 179 NS;
b <= '1', '0' AFTER 045 NS, '1' AFTER 105 NS, '0' AFTER 195 NS;
s <= '0', '1' AFTER 129 NS, '0' AFTER 211 NS, '1' AFTER 245 NS;
END ARCHITECTURE timed;

..
LIBRARY utilities;
USE utilities.VerilogLogic.ALL;
ENTITY multiplexer IS
PORT (a, b, s : IN v4l; w : OUT v4l);
END ENTITY;
--ARCHITECTURE wired OF multiplexer IS
SIGNAL y : wiring v4l;
BEGIN
T1: y <= a WHEN s='0' ELSE 'Z';
T2: y <= b WHEN s='1' ELSE 'Z';
w <= y;
END ARCHITECTURE wired;

MULTIPLER
DATAPATH
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
ENTITY datapath IS
PORT (clk, clr_P, load_P, load_B : IN STD_LOGIC;
msb_out, lsb_out, sel_sum : IN STD_LOGIC;
load_A, shift_A : IN STD_LOGIC;
data : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
A0 : OUT STD_LOGIC);
END ENTITY;
-ARCHITECTURE procedural OF datapath IS

SIGNAL sum, ShiftAdd : STD_LOGIC_VECTOR (7 DOWNTO 0);


SIGNAL A, B, P : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL co : STD_LOGIC;
SIGNAL op : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL result : STD_LOGIC_VECTOR (8 DOWNTO 0);
BEGIN
PROCESS (clk) BEGIN
IF(clk = '0' AND clk'EVENT) THEN
IF (load_B = '1') THEN
B <= data;
END IF;
END IF;
END PROCESS;
-PROCESS (clk) BEGIN
IF(clk = '0' AND clk'EVENT) THEN
IF (load_P = '1') THEN
P <= (co AND sel_sum) & ShiftAdd (7 DOWNTO 1);
END IF;
END IF;
END PROCESS;
-PROCESS (clk) BEGIN
IF(clk = '0' AND clk'EVENT) THEN
CASE op IS
WHEN "01" => A <= ShiftAdd(0) & A(7 DOWNTO 1);
WHEN "10" => A <= data;
WHEN OTHERS => A <= A;
END CASE;
END IF;
END PROCESS;
result <= ('0'&P) + ('0'&B);
co <= result(8);
sum <= result(7 DOWNTO 0);
A0 <= A(0);
ShiftAdd <= (OTHERS => '0') WHEN clr_P = '1' ELSE
P WHEN sel_sum = '0' ELSE sum;
data <= A WHEN lsb_out = '1' ELSE (OTHERS => 'Z');
data <= P WHEN msb_out = '1' ELSE (OTHERS => 'Z');
op <= load_A & shift_A;
END ARCHITECTURE procedural;

MULTIPLIER
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;

ENTITY Multiplier IS
PORT (clk, start : IN STD_LOGIC;
databus : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
lsb_out, msb_out, done : OUT STD_LOGIC);
END ENTITY;
-ARCHITECTURE structural OF Multiplier IS
SIGNAL clr_P, load_P, load_B, msb_out_t, A0 : STD_LOGIC;
SIGNAL lsb_out_t, sel_sum, load_A, Shift_A : STD_LOGIC;
BEGIN
dpu : ENTITY WORK.datapath(procedural)
PORT MAP (clk, clr_P, load_P, load_B, msb_out_t, lsb_out_t,
sel_sum, load_A, Shift_A, databus, A0 );
cu : ENTITY WORK.controller(procedural)
PORT MAP (clk, start, A0, clr_P, load_P, load_B, msb_out_t,
lsb_out_t, sel_sum, load_A, Shift_A, done );
msb_out <= msb_out_t;
lsb_out <= lsb_out_t;
END ARCHITECTURE structural;

..

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating


-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity addibhawna is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;

c,carry : out STD_LOGIC);


end addibhawna;

architecture Behavioral of addibhawna is

begin
c<= a xor b;
carry<=a and b;
end Behavioral;

entity muxbhawna is
port(d,e,f:in STD_LOGIC;
g:out STD_LOGIC);
end muxbhawna;
architecture behavioral1 of muxbhawna is
begin
process(d,e,f)
begin
if d='1' then g<=e;
else g<=f;
end if;
end process;
end behavioral1;

entity pe3bhawna is
port(DL_Iout,Iin,Qin,DL_Qout,S0:in STD_LOGIC;
DL_Iin,Iout,Qout,DL_Qin:out STD_LOGIC);
end pe3bhawna;

architecture bhehavioral2 of pe3bhawna is


signal h,i,j,k: STD_LOGIC;
begin
U1:entity work.addbhawna PORT MAP (a=>DL_Iout,b=>(not Iin),c=>h );
U2 :entity work.addbhawna PORT MAP (a=>DL_Iout,b=>Iin,c=>i);
U3 :entity work.addbhawna PORT MAP (a=>Qin,b=>DL_Qout,c=>j);
U4:entity work.addbhawna PORT MAP (a=>(not Qin),b=>DL_Qout,c=>k);
U5:entity work.muxbhawna PORT MAP (d=>S0,e=>h , f=>Iin, g=>DL_Iin );
U6:entity work.muxbhawna PORT MAP (d=>S0, e=>i, f=>DL_Iout , g=>Iout );
U7:entity work.muxbhawna PORT MAP (d=>S0, e=>j, f=>DL_Qout , g=>Qout );
U8:entity work.muxbhawna PORT MAP (d=>S0, e=>k, f=>Qin , g=>DL_Qin );
end bhehavioral2;

.
----------------------------------------------------------------------------------- Company:
-- Engineer:
--- Create Date:

21:31:39 12/27/2015

-- Design Name:
-- Module Name:
-- Project Name:

addibhawna - Behavioral

-- Target Devices:
-- Tool versions:
-- Description:
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating


-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity addibhawna is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;

c,carry : out STD_LOGIC);


end addibhawna;

architecture Behavioral of addibhawna is

begin
c<= a xor b;
carry<=a and b;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity muxbhawna is
port(d,e,f:in STD_LOGIC;
g:out STD_LOGIC);
end muxbhawna;
architecture behavioral1 of muxbhawna is
begin
process(d,e,f)
begin
if d='1' then g<=e;
else g<=f;
end if;
end process;
end behavioral1;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity pe3bhawna is
port(DL_Iout,Iin,Qin,DL_Qout,S0:in STD_LOGIC;
DL_Iin,Iout,Qout,DL_Qin:out STD_LOGIC);
end pe3bhawna;

architecture bhehavioral2 of pe3bhawna is


signal h,i,j,k: STD_LOGIC;
begin
U1:entity work.addibhawna PORT MAP (a=>DL_Iout,b=>(not Iin),c=>h );
U2 :entity work.addibhawna PORT MAP (a=>DL_Iout,b=>Iin,c=>i);
U3 :entity work.addibhawna PORT MAP (a=>Qin,b=>DL_Qout,c=>j);
U4:entity work.addibhawna PORT MAP (a=>(not Qin),b=>DL_Qout,c=>k);
U5:entity work.muxbhawna PORT MAP (d=>S0,e=>h , f=>Iin, g=>DL_Iin );
U6:entity work.muxbhawna PORT MAP (d=>S0, e=>i, f=>DL_Iout , g=>Iout );
U7:entity work.muxbhawna PORT MAP (d=>S0, e=>j, f=>DL_Qout , g=>Qout );
U8:entity work.muxbhawna PORT MAP (d=>S0, e=>k, f=>Qin , g=>DL_Qin );
end bhehavioral2;

----------------------------------------------------------------------------------- Company:
-- Engineer:
--

-- Create Date:

00:13:53 12/28/2015

-- Design Name:
-- Module Name:

PE2bhawnaa - Behavioral

-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating


-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity addibhawna is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c,carry : out STD_LOGIC);
end addibhawna;

architecture Behavioral of addibhawna is

begin
c<= a xor b;
carry<=a and b;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity muxbhawna is
port(d,e,f:in STD_LOGIC;
g:out STD_LOGIC);
end muxbhawna;
architecture behavioral1 of muxbhawna is
begin
process(d,e,f)
begin
if d='1' then g<=e;
else g<=f;

end if;
end process;
end behavioral1;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity pe3bhawna is
port(DL_Iout,Iin,Qin,DL_Qout,S0:in STD_LOGIC;
DL_Iin,Iout,Qout,DL_Qin:out STD_LOGIC);
end pe3bhawna;

architecture bhehavioral2 of pe3bhawna is


signal h,i,j,k: STD_LOGIC;
begin
U1:entity work.addibhawna PORT MAP (a=>DL_Iout,b=>(not Iin),c=>h );
U2 :entity work.addibhawna PORT MAP (a=>DL_Iout,b=>Iin,c=>i);
U3 :entity work.addibhawna PORT MAP (a=>Qin,b=>DL_Qout,c=>j);
U4:entity work.addibhawna PORT MAP (a=>(not Qin),b=>DL_Qout,c=>k);
U5:entity work.muxbhawna PORT MAP (d=>S0,e=>h , f=>Iin, g=>DL_Iin );
U6:entity work.muxbhawna PORT MAP (d=>S0, e=>i, f=>DL_Iout , g=>Iout );
U7:entity work.muxbhawna PORT MAP (d=>S0, e=>j, f=>DL_Qout , g=>Qout );
U8:entity work.muxbhawna PORT MAP (d=>S0, e=>k, f=>Qin , g=>DL_Qin );
end bhehavioral2;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity PE2bhawnaa is
port(DL_Iout,Iin,Qin,DL_Qout,S1:in STD_LOGIC;
DL_Iin,Iout,Qout,DL_Qin:out STD_LOGIC);
end PE2bhawnaa;

architecture Behavioral3 of PE2bhawnaa is

begin

U9 :entity work.muxbhawna PORT MAP (d=>S1, e=>DL_Qout, f=>DL_Iout ,


g=>DL_Iin );
U10 :entity work.muxbhawna PORT MAP (d=>S1, e=>(not DL_Iout), f=>DL_Qout ,
g=>DL_Qin );

end Behavioral3;

.
VADIC MULTIPLIER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vedmac_pipe_32 is
Port ( clk , resetn: in std_logic;
ain1 : in STD_LOGIC_VECTOR (31 downto 0);
bin1 : in STD_LOGIC_VECTOR (31 downto 0);

sout : inout STD_LOGIC_VECTOR (63 downto 0));


end vedmac_pipe_32;
architecture Behavioral of vedmac_pipe_32 is
component caresave_n is
generic( n: integer := 32);
Port ( a2,b2,c2 : in STD_LOGIC_VECTOR (n-1 downto 0);
cot : out STD_LOGIC);
end component;
component accumulator is
Port ( clk, resetn : in STD_LOGIC;
x : in STD_LOGIC_vector (63 downto 0);
result : inout std_logic_vector (63 downto 0) );
end component;
component BEC_16 is
generic( p : integer := 16);
Port ( B : in STD_LOGIC_VECTOR (p-1 downto 0);
X : out STD_LOGIC_VECTOR (p-1 downto 0);
ccarry: in std_logic);
end component;
component vedmine16_clk is
Port ( ainpu, binputt : in STD_LOGIC_VECTOR (15 downto 0);
soutp : out STD_LOGIC_VECTOR (31 downto 0);
clk: in std_logic);
end component;
component hancarlson_64 is
Port ( ainp,binp : in STD_LOGIC_VECTOR (63 downto 0);

soutp : out STD_LOGIC_VECTOR (63 downto 0);


carry : out STD_LOGIC);
end component;
component pipo is
generic (k : integer:= 64);
Port ( clk , resetn: in STD_LOGIC;
din : in STD_LOGIC_VECTOR (k-1 downto 0);
qout : inout STD_LOGIC_VECTOR (k-1 downto 0));
end component;
component dff is
Port ( d : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC);
end component;
signal p : std_logic;
signal m : std_logic_vector(128 downto 0);signal sout1, sum : std_logic_vector(63
downto 0);signal n: std_logic_vector (15 downto 0);signal l: std_logic_vector (63
downto 16);
signal j: std_logic_vector (63 downto 16);
begin
v1: vedmine16_clk port map ( ain1( 15 downto 0), bin1(15 downto 0),m(31 downto
0), clk);
v2: vedmine16_clk port map( ain1( 31 downto 16), bin1(31 downto 16),m(63
downto 32), clk);
v3: vedmine16_clk port map( ain1( 31 downto 16), bin1(15 downto 0),m(95
downto 64), clk);
v4: vedmine16_clk port map( ain1( 15 downto 0), bin1(31 downto 16),m(127
downto 96), clk);

bec3 : bec_16 port map ( m(63 downto 48), l(63 downto 48), m(128));
f: for i in 0 to 15 generate
d: dff port map (m(i), clk, sout1(i));
end generate;
f3: for i in 16 to 63 generate
d4: dff port map (l(i), clk, sout1(i));
end generate;
add : hancarlson_64 port map( sout1( 63 downto 0) , sout(63 downto 0) , sum (63
downto 0), p);
resg : pipo port map (clk, resetn, sum (63 downto 0 ), sout (63 downto 0 ));

END behavioral;

SHIFTER
entity shifter is
generic (
REGSIZE : integer := 8);
port(
clk
: in str_logic;
Data_in : in std_logic;
Data_out : out std_logic(REGSIZE-1 downto 0);
end shifter ;
architecture bhv of shifter is
signal shift_reg : std_logic_vector(REGSIZE-1 downto 0) := (others<='0');
begin
process (clk) begin
if rising_edge(clk) then
shift_reg <= shift_reg(REGSIZE-2 downto 0) & Data_in;
end if;
end process;
end bhv;
Data_out <= shift_reg;

Note:this in not running

.
8 BIT SISI REG this is extra one and running.
entity shifter is

port(
C,S1 : in std_logic;
S0: out std_logic);
end shifter ;
architecture bhv of shifter is
signal temp:std_logic_vector(7 downto 0);
begin
process(C)
begin
if (C'event and C='1')then
for i in 0 to 6 loop
temp(i+1)<=temp(i);
end loop;
temp(0)<=S1;
end if;
end process;
S0<=temp(7);

end bhv;

.
Shifting running

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity shift_register_top is
Port ( CLK : in STD_LOGIC;
D : in STD_LOGIC;
LED : out STD_LOGIC_VECTOR(7 downto 0));
end shift_register_top;

architecture Behavioral of shift_register_top is


signal clock_div : STD_LOGIC_VECTOR(4 downto 0);
signal shift_reg : STD_LOGIC_VECTOR(7 downto 0) := X"00";
begin
process (CLK)
begin
if (CLK'event and CLK = '1') then
clock_div <= clock_div + '1';
end if;
end process;
process (clock_div(4))
begin

if (clock_div(4)'event and clock_div(4) = '1') then


shift_reg(7) <= D;
shift_reg(6) <= shift_reg(7);
shift_reg(5) <= shift_reg(6);
shift_reg(4) <= shift_reg(5);
shift_reg(3) <= shift_reg(4);
shift_reg(2) <= shift_reg(3);
shift_reg(1) <= shift_reg(2);
shift_reg(0) <= shift_reg(1);
end if;
end process;
LED <= shift_reg;
end Behavioral;

FFT USING VHDL

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
PACKAGE untitled_pkg IS
TYPE vector_of_std_logic_vector16 IS ARRAY (NATURAL RANGE <>) OF INTEGER;
END untitled_pkg;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.untitled_pkg.ALL;

---- Uncomment the following library declaration if instantiating


---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Hussain is
generic(N:integer:=8;
log:integer:=3);
port(x:in vector_of_std_logic_vector16(0 TO 7);
clk:in std_logic;
yut vector_of_std_logic_vector16(0 TO 7));
end Hussain;
architecture Behavioral of Hussain is
begin
top: process(clk)
variable b,s,k,h,temp3,temp4:integer;
variable temp:vector_of_std_logic_vector16(0 TO 7);
variable temp1,temp2,w:integer;
begin
If rising_edge(clk)then
temp:=x;

loop1: for l in 1 to log loop


b:=N/(2**l);
s:=N/(2*b);
loop2: for R in 1 to s loop
h:=0; k:=0;
loop3: for n in 0 to (b-1) loop

wRom: case k is

when 0 => w := 2;
when 1 => w := 3;
when 2 => w := 4;
when 3 => w := 5;
when others => null;
end case;
temp1:=temp(n+h)+temp(n+h+(b/2));
temp2:=w*(temp(n+h)-temp(n+h+(b/2)));
temp(n+h):=temp1;
temp(n+h+(b/2)):=temp2;
temp3:=k+s;
k:=temp3;
End loop;
temp4:=h+(2*b);
h:=temp4;
End loop;
End loop;
End IF;
Y<=temp;
End process;
end Behavioral;

FFT running code


library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity test_fft is
generic(
adder_width : positive := 24;
adder_depth : positive := 2;
adc_data_width : positive := 12;
window_ram_adr_width : positive := 8;
window_ram_data_width : positive := 12;
wola_num_blocks : positive := 4

);
port (
CLK, RST : in std_logic;
FFT_XK_RE : out std_logic_vector(30 downto 0);
FFT_XK_IM : out std_logic_vector(30 downto 0);
ADC_DATA: in std_logic_vector(23 downto 0)
);
end test_fft;

architecture Behavioral of test_fft is


component fft_64
port (
xn_re: IN std_logic_VECTOR(23 downto 0);
xn_im: IN std_logic_VECTOR(23 downto 0);
start: IN std_logic;
nfft: IN std_logic_VECTOR(4 downto 0);
nfft_we: IN std_logic;
fwd_inv: IN std_logic;
fwd_inv_we: IN std_logic;
sclr: IN std_logic;
ce: IN std_logic;
clk: IN std_logic;
xk_re: OUT std_logic_VECTOR(30 downto 0);
xk_im: OUT std_logic_VECTOR(30 downto 0);
xn_index: OUT std_logic_VECTOR(5 downto 0);
xk_index: OUT std_logic_VECTOR(5 downto 0);
rfd: OUT std_logic;
busy: OUT std_logic;
dv: OUT std_logic;
edone: OUT std_logic;
done: OUT std_logic);
end component;
-- FPGA Express Black Box declaration
attribute fpga_dont_touch: string;
attribute fpga_dont_touch of fft_64: component is "true";
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of fft_64: component is true;

begin
FFT: fft_64
port map (
xn_re => ADC_DATA,
xn_im => ADC_DATA,
start => '1',
nfft => "00110",
nfft_we => '0',
fwd_inv => '0',
fwd_inv_we => '0',
sclr => '0',
ce => '1',
clk => CLK,
xk_re => FFT_XK_RE,
xk_im => FFT_XK_IM,
xn_index => open,
xk_index => open,
rfd => open,
busy => open,
dv => open,
edone => open,
done => open);
end Behavioral;
.
2 bit shift register

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating


-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY flipflop IS
PORT (

D:IN STD_LOGIC_VECTOR(1 downto 0);

Resetn, Clock
Q

: IN
: OUT

STD_LOGIC ;
STD_LOGIC_VECTOR(1 downto 0)) ;

END flipflop ;

ARCHITECTURE Behavior OF flipflop IS


BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ;
IF Resetn = '0' THEN
Q <= "00" ;
ELSE
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;


..
4 bit shift reg
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY shift_reg4 IS
PORT (
d
: IN std_logic_vector (3 DOWNTO 0);
clk, ld, rst, l_r, s_in : IN std_logic;
q
: OUT std_logic_vector (3 DOWNTO 0));
END shift_reg4;
ARCHITECTURE behavioral OF shift_reg4 IS
BEGIN
PROCESS (clk)
VARIABLE q_t: std_logic_vector (3 DOWNTO 0);
BEGIN
IF rising_edge (clk) THEN
IF rst= '1' THEN
q_t := (OTHERS => '0');
ELSIF ld = '1' THEN
q_t := d;
ELSIF l_r = '1' THEN
q_t := q_t (2 DOWNTO 0) & s_in ;
ELSE
q_t := s_in & q_t (3 DOWNTO 1);
END IF;
END IF;
q <= q_t;
END PROCESS;
END behavioral;

BIT PARALLL MULTIPLICATION


----------------------------------------------------------------------------------- Company:
-- Engineer:
--- Create Date:

22:29:49 01/02/2016

-- Design Name:
-- Module Name:

bitparallelmulti - Behavioral

-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating


-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity addibhawna1 is
Port ( a : in STD_LOGIC_vector(3 downto 0);
b : in STD_LOGIC_vector(3 downto 0);

c:out std_logic_vector(3 downto 0);


carry : out STD_LOGIC_vector(3 downto 0));
end addibhawna1;

architecture Behavioral of addibhawna1 is

begin
c<= a xor b;
carry<=a and b;
end Behavioral;

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

entity addibhawna2 is
Port ( A : in STD_LOGIC_vector(3 downto 0);
B : in STD_LOGIC_vector(3 downto 0);
C:out std_logic_vector(3 downto 0);
carry : out STD_LOGIC_vector(3 downto 0));
end addibhawna2;

architecture Behavioral of addibhawna2 is

begin
C<= A xor B;
carry<= A and B;

end Behavioral;

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY flipflop IS
PORT (

D:IN STD_LOGIC_VECTOR(3 downto 0);

Resetn, Clock
Q

: IN
: OUT

STD_LOGIC ;
STD_LOGIC_VECTOR(3 downto 0)) ;

END flipflop ;

ARCHITECTURE Behavior OF flipflop IS


BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ;
IF Resetn = '0' THEN
Q <= "0000" ;
ELSE
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY shift_reg4 IS
PORT (
d : IN std_logic_vector (3 DOWNTO 0);
clk, ld, rst, l_r, s_in : IN std_logic;
q : OUT std_logic_vector (3 DOWNTO 0));
END shift_reg4;

ARCHITECTURE behavioral OF shift_reg4 IS


BEGIN
PROCESS (clk)
VARIABLE q_t: std_logic_vector (3 DOWNTO 0);
BEGIN
IF rising_edge (clk) THEN
IF rst= '1' THEN
q_t := (OTHERS => '0');
ELSIF ld = '1' THEN
q_t := d;
ELSIF l_r = '1' THEN
q_t := q_t (2 DOWNTO 0) & s_in ;
ELSE
q_t := s_in & q_t (3 DOWNTO 1);
END IF;

END IF;
q <= q_t;
END PROCESS;
END behavioral;

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

entity bitparallelmulti is
Port ( DL_Iout : in STD_LOGIC_vector(3 downto 0);
clk,rst,l_r, s_in ,ld:in STD_LOGIC;
outt : out STD_LOGIC_vector(3 downto 0));
end bitparallelmulti;

architecture Behavioral of bitparallelmulti is

signal u:std_logic_vector(3 downto 0);


signal y:std_logic_vector(3 downto 0);
signal z:STD_LOGIC_vector(3 downto 0);

signal v:std_logic_vector(3 downto 0);

signal x:std_logic_vector(3 downto 0);


signal w:std_logic_vector(3 downto 0);
begin

U11:entity work.addibhawna1 port map(a=>DL_Iout,b=>u,c=>x);


U12:entity work.addibhawna2 port map(A=>x,B=>y,C=>z);
U13:entity work.addibhawna1 port map (a=>w,b=>DL_Iout,c=>outt);
U14:entity work.flipflop port map(D=>DL_Iout,clock=>clk,resetn=>rst,Q=>u);
U15:entity work.shift_reg4 port
map(clk=>clk,rst=>rst,l_r=>l_r,s_in=>s_in,ld=>ld,d=>x,q=>y);
U16:entity work.flipflop port map(D=>y,clock=>clk,resetn=>rst,Q=>w);

end Behavioral;

..
CIRCUIT dig of MULTIPLICATION
----------------------------------------------------------------------------------- Company:
-- Engineer:
--- Create Date:

19:30:52 01/04/2016

-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--- Dependencies:
--- Revision:

wwmultiplication - Behavioral

-- Revision 0.01 - File Created


-- Additional Comments:
--------------------------------------------------------------------------------------------------------------------------------------------------------------------- Company:
-- Engineer:
--- Create Date:

16:04:27 01/04/2016

-- Design Name:
-- Module Name:

wmultilpication - Behavioral

-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--------------------------------------------------------------------------------------------------------------------------------------------------------------------- Company:
-- Engineer:

--- Create Date:

22:29:49 01/02/2016

-- Design Name:
-- Module Name:

bitparallelmulti - Behavioral

-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity addibhawna1 is

Port ( a : in STD_LOGIC_vector(3 downto 0);


b : in STD_LOGIC_vector(3 downto 0);
c:out std_logic_vector(3 downto 0);
carry : out STD_LOGIC_vector(3 downto 0));
end addibhawna1;
architecture Behavioral of addibhawna1 is

begin
c<= a xor b;
carry<=a and b;
end Behavioral;
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY flipflop IS
PORT (

D:IN STD_LOGIC_VECTOR(3 downto 0);

Resetn, Clock
Q

: IN
: OUT

STD_LOGIC ;
STD_LOGIC_VECTOR(3 downto 0)) ;

END flipflop ;
ARCHITECTURE Behavior OF flipflop IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ;
IF Resetn = '0' THEN
Q <= "0000" ;
ELSE

Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY shift_reg4 IS
PORT (
d : IN std_logic_vector (3 DOWNTO 0);
clk, ld, rst, l_r, s_in : IN std_logic;
q : OUT std_logic_vector (3 DOWNTO 0));
END shift_reg4;

ARCHITECTURE behavioral OF shift_reg4 IS


BEGIN
PROCESS (clk)
VARIABLE q_t: std_logic_vector (3 DOWNTO 0);
BEGIN
IF rising_edge (clk) THEN
IF rst= '1' THEN
q_t := (OTHERS => '0');
ELSIF ld = '1' THEN
q_t := d;
ELSIF l_r = '1' THEN
q_t := q_t (2 DOWNTO 0) & s_in ;

ELSE
q_t := s_in & q_t (3 DOWNTO 1);
END IF;
END IF;
q <= q_t;
END PROCESS;
END behavioral;

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

entity bitparallelmulti is
Port ( DL_Iout : in STD_LOGIC_vector(3 downto 0);
clk,rst,l_r, s_in ,ld:in STD_LOGIC;
outt : out STD_LOGIC_vector(3 downto 0));
end bitparallelmulti;

architecture Behavioral of bitparallelmulti is

signal u:std_logic_vector(3 downto 0);


signal y:std_logic_vector(3 downto 0);
signal z:STD_LOGIC_vector(3 downto 0);
signal v:std_logic_vector(3 downto 0);
signal x:std_logic_vector(3 downto 0);
signal w:std_logic_vector(3 downto 0);
begin

U11:entity work.addibhawna1 port map(a=>DL_Iout,b=>u,c=>x);


U12:entity work.addibhawna1 port map(a=>x,b=>y,c=>z);
U13:entity work.addibhawna1 port map (a=>w,b=>DL_Iout,c=>outt);
U14:entity work.flipflop port map(D=>DL_Iout,clock=>clk,resetn=>rst,Q=>u);
U15:entity work.shift_reg4 port
map(clk=>clk,rst=>rst,l_r=>l_r,s_in=>s_in,ld=>ld,d=>x,q=>y);
U16:entity work.flipflop port map(D=>y,clock=>clk,resetn=>rst,Q=>w);
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity wmultilpication is
Port ( Iin : in STD_LOGIC_VECTOR (3 downto 0);
Qin : in STD_LOGIC_VECTOR (3 downto 0);
clk,rst,l_r, s_in ,ld:in STD_LOGIC;
Iout : out STD_LOGIC_VECTOR (3 downto 0);
Qout : out STD_LOGIC_VECTOR (3 downto 0));
end wmultilpication;
architecture Behavioral of wmultilpication is
signal r:std_logic_vector(3 downto 0);
signal t:std_logic_vector(3 downto 0);
begin
U17: entity work.addibhawna1 port map(a=>Iin, b=>Qin, c=>r);
U18: entity work.addibhawna1 port map(a=>Qin, b=>not Iin, c=>t);

U19: entity work.bitparallelmulti port map


(clk=>clk,rst=>rst,l_r=>l_r,s_in=>s_in,ld=>ld,outt=>Iout,DL_Iout=>r);
U20: entity work.bitparallelmulti port map
(clk=>clk,rst=>rst,l_r=>l_r,s_in=>s_in,ld=>ld,outt=>Qout,DL_Iout=>t);
end Behavioral;

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