Scribd
Upload
619 views1 page

Median Filter

This document discusses the implementation of a 3x3 median filter on an Altera DE2 Cyclone II FPGA board to remove impulse noise from images. A median filter is effective at reducing impulse noise while preserving edges. The design uses an optimized systolic array architecture to sort pixel values and find the median. Implementation results show improvements in operating frequency and resource usage compared to general purpose techniques. The median filter hardware is combined with software to provide faster image processing compared to an all-software approach.

Uploaded by

Dyana Ramly
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
619 views1 page

Median Filter

This document discusses the implementation of a 3x3 median filter on an Altera DE2 Cyclone II FPGA board to remove impulse noise from images. A median filter is effective at reducing impulse noise while preserving edges. The design uses an optimized systolic array architecture to sort pixel values and find the median. Implementation results show improvements in operating frequency and resource usage compared to general purpose techniques. The median filter hardware is combined with software to provide faster image processing compared to an all-software approach.

Uploaded by

Dyana Ramly
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 1

Implementation of Median Filter on FPGA Board

Abstract-Digital image processing is the process of displaying an


images. This field has wide number of applications each of which is
useful in a daily life. Various image processing algorithms helps user to
clearly view an image and able to recognise different characteristics of
the image. Median filter is an effective device for the removal of
impulse-based noise on video signals. This is due to the partial
averaging effect of the median filter and its biasing of the input
stream, rather than straight mathematical averaging. This paper gives
the algorithm and implementation details of a sliding real time 3x3
median filter. The design in implemented on an Altera DE2 Cyclone II
Board. The technique being used is implementing an optimized
systolic architecture sort hardware developed in Verilog HDL. The
Verilog HDL model of the sort hardware for median filter is
implemented on grayscale bitmap loaded onto FPGA (Field
Programmable Gate Array). The algorithm used to implement median
filter is very efficient and implementation results show the significant
improvements in operating frequency and hardware requirements
over general purpose techniques.
Keywords-digital image processing, median filter, impulse-based noise
video signals, input stream, algorithm.

I. INTRODUCTION
Digital image processing has been widely used in variety of
applications in our daily life such as medicine, surveillance, images
capture by digital cameras and even our smart phones and many
more areas [1]. However, in most of the cases, captured images
from image sensors are affected by undesired signals which
commonly being referred as a noise. One of the most frequently
referred types of noise is the impulse noise or also known as salt
and pepper noise (white and black dotes). Impulse noise is caused
by faulty memory locations of hardware, malfunctioning pixels in
camera sensors or any errors that occurs during data transmission.
Once of the most important image processing operations is
image enhancement [2]. Image enhancement provides more
effective display of image for visual interpretation. It helps user to
clearly view the image and able to recognise different
characteristics of the image. This technique is very useful for
assisting with distinction of different objects in an image.
Media filter is a non-linear filter used in image processing for
impulse noise removal while preserving the edges. The filtering

algorithm is applied by moving a mask on the input frame from


pixel to pixel. The mask can be of varying size like 3x3, 5x5, 7x7,
etc.
Median filtering can be considered as a popular method to
overcome this noise from images as it can be effectively reducing
the impulse noise while at the same time preserve the images
edges information [3]. To meet the demands for a higher
throughput image processing, the combinational of hardware and
software system design has become an attractive option rather than
just software alone system design as the hardware part is offering
parallel processing that will make the computational to be faster.
This project is intended to develop a hardware and software based
design median filter to remove the impulse noise in images using
Altera DE2 Cyclone II Board. The algorithm used to sort out the
median value of the 3x3 pixels window is the optimized systolic
array.
For hardware implementation of image processing algorithms,
FPGA has emerged as a visible target. This is because FPGA offers
various advantages like it proves to be much more efficient in
terms of cost and performance, offers parallelism performing
various operations simultaneously, provides flexibility to
reprogram or upgrade the design and can speed up implementations
by avoiding redundant operations [5].
The image processing algorithms implemented by software
alone system have some limitations such as a long processing time
due to the limited processor speed and a greater number of clock
cycles needed to executes the software code. Processing speed is
very crucial for applications that need to display clear images for
every second such as surveillance, satellite communication and
automated visual inspection [4].
However, with the advances in todays VLSI technology,
combination of hardware and software implementation has become
an attractive alternative where the concept of parallelism and pipelining can be applied in the hardware part to allow a parallel
processing, and thus will increase the processing capacity and
reduce the processing time [5].

You might also like