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Ripple Counters: Asynchronous

The document discusses different types of synchronous and asynchronous counters including ripple counters, Johnson counters, and ring counters. It provides Verilog code examples for implementing a universal shift register, synchronous 4-bit counter, and ripple counter. Stimulus and testbench code is also included for simulating the ripple counter.

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133 views

Ripple Counters: Asynchronous

The document discusses different types of synchronous and asynchronous counters including ripple counters, Johnson counters, and ring counters. It provides Verilog code examples for implementing a universal shift register, synchronous 4-bit counter, and ripple counter. Stimulus and testbench code is also included for simulating the ripple counter.

Uploaded by

vlsijp
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Ripple Counters

Asynchronous

BCD Counter State Diagram

Ripple BCD Counter

Cascaded Ripple BCD


Counter

Synchronous Binary Counter

Use Normal Design


Process for Moore Machine

Synchronous Up/Down Binary


Counter

4-bit Counter with Parallel


Load

BCD Counters with Parallel


Load
counter from previous slide

Lock-out Prevention

Ring Counters

Johnson Counter

Verilog for Universal Shift Register


//HDL Example 6-1
//--------------------//Behavioral description of
//Universal shift register
// Fig. 6-7 and Table 6-3
module shftreg (s1,s0,Pin,lfin,rtin,A,CLK,Clr);
input s1,s0;
//Select inputs
input lfin, rtin;
//Serial inputs
input CLK,Clr;
//Clock and Clear
input [3:0] Pin;
//Parallel input
output [3:0] A;
//Register output
reg [3:0] A;
always @ (posedge CLK or negedge Clr)
if (~Clr) A = 4'b0000;
else
case ({s1,s0})
2'b00: A = A;
//No change
2'b01: A = {rtin,A[3:1]}; //Shift right
2'b10: A = {A[2:0],lfin}; //Shift left
2'b11: A = Pin;
//Parallel load input
endcase
endmodule

Verilog for Universal Shift Register


Structural Description
//HDL Example 6-2
//------------------------------------//Structural description of
//Universal shift register(see Fig.6-7)
module SHFTREG (I,select,lfin,rtin,A,CLK,Clr);
input [3:0] I;
//Parallel input
input [1:0] select;
//Mode select
input lfin,rtin,CLK,Clr; //Serial inputs,clock,clear
output [3:0] A;
//Parallel output
//Instantiate the four stages
stage ST0 (A[0],A[1],lfin,I[0],A[0],select,CLK,Clr);
stage ST1 (A[1],A[2],A[0],I[1],A[1],select,CLK,Clr);
stage ST2 (A[2],A[3],A[1],I[2],A[2],select,CLK,Clr);
stage ST3 (A[3],rtin,A[2],I[3],A[3],select,CLK,Clr);
endmodule

Verilog for Universal Shift Register


Structural Description (cont)
//One stage of shift register
module stage(i0,i1,i2,i3,Q,select,CLK,Clr);
input i0,i1,i2,i3,CLK,Clr;
input [1:0] select;
output Q;
reg Q;
reg D;
//4x1 multiplexer
always @ (i0 or i1 or i2 or i3 or select)
case (select)
2'b00: D = i0;
2'b01: D = i1;
2'b10: D = i2;
2'b11: D = i3;
endcase
//D flip-flop
always @ (posedge CLK or negedge Clr)
if (~Clr) Q = 1'b0;
else Q = D;
endmodule

Verilog for Synchronous Counter


//HDL Example 6-3
//------------------//Binary counter with parallel load
//See Figure 6-14 and Table 6-6
module counter (Count,Load,IN,CLK,Clr,A,CO);
input Count,Load,CLK,Clr;
input [3:0] IN;
//Data input
output CO;
//Output carry
output [3:0] A;
//Data output
reg [3:0] A;
assign CO = Count & ~Load & (A == 4'b1111);
always @ (posedge CLK or negedge Clr)
if (~Clr) A = 4'b0000;
else if (Load) A = IN;
else if (Count) A = A + 1'b1;
else A = A;
// no change, default condition
endmodule

Verilog for Ripple Counter


//HDL Example 6-4
//---------------------//Ripple counter (See Fig. 6-8(b))
module ripplecounter (A0,A1,A2,A3,Count,Reset);
output A0,A1,A2,A3;
input Count,Reset;
//Instantiate complementing flip-flop
CF F0 (A0,Count,Reset);
CF F1 (A1,A0,Reset);
CF F2 (A2,A1,Reset);
CF F3 (A3,A2,Reset);
endmodule
//Complementing flip-flop with delay
//Input to D flip-flop = Q'
module CF (Q,CLK,Reset);
output Q;
input CLK,Reset;
reg Q;
always @ (negedge CLK or posedge Reset)
if (Reset) Q = 1'b0;
else Q = #2 (~Q);
// Delay of 2 time units
endmodule

Verilog for Ripple Counter Testbench


//Stimulus for testing ripple counter
module testcounter;
reg Count;
reg Reset;
wire A0,A1,A2,A3;
//Instantiate ripple counter
ripplecounter RC (A0,A1,A2,A3,Count,Reset);
always
#5 Count = ~Count;
initial
begin
Count = 1'b0;
Reset = 1'b1;
#4 Reset = 1'b0;
#165 $finish;
end
endmodule

Ripple Counter Simulation Results

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