Microprocessor and Programming
Microprocessor and Programming
1
Basics of
Microprocessor
8085
Memory basics To select the chip,
whether read or write
Control inputs
operation
Data input lines 0000 1111 (0FH)
To address any used for
location or to No. of locations
DATA BUS 0010 0100 (24H)
select any location =M
writing operation
we require
1010 1110 (AEH)
address lines.
-
No of address Eg: 3 bit address lines are
lines = therefore = 8 locations and
Address lines 0001 1010 (1AH)
address varies as:
000
001
0101 0111 (57H)
010
Every location consist of N D
Data output lines -
bit data (in general 8 bit used for reading 111
data) A
operation and at every location 8 bit
T
data present
A
B
U
S
Microprocessor Ports
Memory
This is an 8 bit temporary register which is not used by the user but only used by the
microprocessor itself to store temporary data.
Microprocessor
Memory
Higher nibble
Word : 16 bits form a word
Eg : 1001 1000 1011 1010 Lower byte
Higher byte
The BIU :
- Sends out addresses
- Fetches instructions and data from memory
- Reads the ports
In other words all operations related to outside world (outside the µp) are handled by the BIU
i.e. all data transfers and address transfers are handled by this unit for BIU.
The word Bus interface unit itself indicates that this unit is used to interface the buses with the outside world.
The EU
- Tells BIU where to fetch instructions and data from
- Decodes the instruction
- Executes the instruction
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BIU Memory ARCHITECTURE
Interface
Σ20 6
5
4
DS 3 6 byte instruction
2 queue register
ES
1
Segment Registers
CS
-------------------------------------
--------
SS
AH AL
BH BL General purpose ARITHMETIC LOGIC
CH CL Registers UNIT (ALU)
DH DL
SP
BP
Pointers and index
SI TEMPORARY REGISTER
Registers
DI
FLAG REGISTER
EU
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BIU (Bus Interface Unit)
The BIU consist of the following modules:
1. Physical address calculation unit (Generates 20 bit physical address)
2. Segment registers (Used to store the base address to access a segment)
3. Instruction pointer (Used to store the offset address, used along with the code segment)
4. Queue register, 6 bytes long (Used to store 6 prefetch instruction bytes from the memory)
With the help of these modules it performs the following action:
- It sends out addresses to access memory and i/o ports
- It fetches instructions and data from the memory and also performs write operation with the help of system bus
- In other words it interfaces with the external world
- Instruction queuing in the queue register
CS 1000H -
PA = BA + EA = 20 bits = 12FACH Code segment
IP 2FACH -
-
-
8086 FFFFFH
Memory
Microprocessor
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Stack Pointer (SP) register
The stack memory segment is used to save useful data in the form of stack of data and addresses when the µp
transfers the control from the main program to the subroutine.
To access the stack memory segment again we require physical address of 20 bits. Now we require base
address and offset address. µp will always obtain the base address from SS register and offset address
from SP register.
The stack segment register and the stack pointer register together address the stack top. Initial
1000H Stack segment 0000H stack top
- -
SS BA - -
PA = BA + EA = 10000H + Top of stack
OA 25 FFFCH
SP FFFCH = 1FFFCH
00 FFFDH
98 FFFEH
Microprocessor
34 FFFFH
3AH 0000H
SS = BA = 1000H - - AX = 6F5DH
5DH 0FFEH PUSH AX when SP = 1000H
6FH 0FFFH
But if SP is loaded initially 8BH 1000H
= 1000H and then PUSH Initially SP = 0000H
- -
inst. Is executed then data When PUSH inst. Is
storage starts from 0FFFH 3EH FFFEH executed storage of data
and then points to data starts from 1 less i.e.
2CH FFFFH
last entered i.e. 0FFEH FFFFH and then points to
STACK SEGMENT the data last entered i.e. STACK SEGMENT
64 Kb FFFEH 64 Kb
PUSH AX when SP = 0000H AX = 2C3EH
µprocessor FFFFH
8 MSB’s 8 LSB’s
X – Indicates Intel reserved (for future use) A 16 bit register used out of which 9 are used by the µp and
Total 9
the rest are reserved by Intel for future use.
CF – Carry Flag
PF – Parity Flag flags Since it is a register it can either be 0 or 1
AC – Auxiliary Carry Flag Therefore a flag may be reset or set
ZF – Zero Flag The flags may be status flags or control flags
SF – Sign Flag Status flags are those which give the current status of the µp
TF – Trap Flag Control flags are those which control the
IF – Interrupt Flag operations of the µp
DF – Direction Flag
OF – Overflow Flag
BX = 2008H
ADD AX,BX instruction is executed. The result obtained is 300AH (0011 0000 0000 1010) which is stored in AX register.
Now µp will check only the last 8 bits of the result
Here It came to know that No. of 1’s are 2 which is even hence PF = 1
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Zero flag (Bit 7)
Type: Status Flag
Operation: Whenever any arithmetic or logical operation takes place and the result is 0 then zero flag sets to
indicate that the result is 0 i.e. ZF = 1
Eg: Let AL = 80H
BL = 80H
SUB AL,BL instruction is executed. The result obtained is 00H in AL register. When µp checks this it has to
reflect it somewhere that the result is zero, so it reflects in bit 7 which is reserved for zero flag by setting its
value to 1 i.e. ZF = 1
Similarly for 16 bit operations, when the result is 0000H. ZF sets i.e. ZF = 1
Else it is always 0 i.e. ZF = 0
SUB = 1 1 1 1 1 1 1 0 = FEH
INTR pin
To INTR circuit
IF
Shown above is the internal circuitry to control the maskable interrupts. When Bit 10 of Flag register is 0 i.e.
IF = 0, input to the AND gate is 0 therefore o/p of AND gate goes low. Therefore any input to the AND gate won’t be
recognized hence any interrupt occurring on the INTR pin won’t be acknowledged as it is not recognized.
When IF = 1 and interrupt on the INTR pin occurs it is recognized and given to the internal INTR circuitry through AND
gate and then acknowledged.
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Trap Flag (Bit 9)
Type: Control Flag
Operation: This flag is used to detect any error in the program (debugging) by executing the program in single
stepping mode.
- If logic 0 is stored in TF, then the µp will execute all the instructions of a program in one operation (free run
operation)
Eg: When we execute the program and press key F9, the entire program gets executed in one stroke. The imp. Point
to understand is that when we press the key F9, value 0 gets placed bit 9 of the flag register therefore Trap flag
resets i.e. TF = 0.
- If logic 1 is stored in TF, then the µp will execute one instruction of the program at a time, after executing each
instruction µp will execute INT1 (software interrupt), so µp will branch from main program to subroutine.
The subroutine has a program which displays the result in different registers of µp on the screen, so after each
instruction the programmer can verify the result.
Eg: We use F8 function key to execute the program in single stepping mode. When we press key F8 value 1 gets
placed into bit 9 of flag register, hence trap flag sets i.e. TF = 1
In the above example we see two memory blocks. The offset address of first memory block is placed in the SI
register and offset address of the second memory block is placed in the DI register.
Now we need to manually increment SI and DI after each byte transfer from data segment to extra segment.
OA OA
Source memory block Destination memory block
1 person can do the work in 1 sec, now the work got divided, but first time all the modules are in wait state
and waiting for the previous one to complete i.e. M2 is waiting for M1 to complete. So time taken is same
i.e. 1s. But after the entire cycle is complete once, now the time taken is only 0.2 sec.
Byte 6
Byte 5
Byte 4 First in
first out
Byte 3
Byte 2
Byte 1
Execution unit
BIU
6
It has a two stage pipeline 5
1. Fetch stage (prefetches upto 6 bytes)
2. Decode and Execute stage (where) 4
Instructions are decoded and executed 3
2
1
6 bytes queue
BHE/ Maximum
CLK 19 34
mode pins
RESET 21 32 RD
READY 22 8086
µp 31 HOLD /
30 HLDA /
29 WR LOCK
NMI 17 26 DEN
INTR 18 27 DT/R
28 M/ IO
TEST 23 25 ALE
MN/MX 33 24 INTA
RD OE (o/p enable)
Microprocessor Memory
Address
Address or Data depending upon ALE
Data 2 : 1 MUX
-------
1 T state
= 0.2 sec
. STB
- - 20 bit address generated to access
8282
Memory or I/O device
STB
-
8282
Multiplexed
Microprocessor Address and
Data bus
𝐴1 𝐴1
Even Memory Odd Memory
Address Bus Address Bus
𝐴 19 Bank 𝐴 19 Bank
𝐷0 𝐷8
Data Bus Data Bus
𝐷 7
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𝐷15
BY UBAID SAUDAGAR 107
Concept of Memory Banking
SELECTION OF MEMORY BANKS :
As we know that only 19 address lines are required to access memory banks, 1 address line is left.
With the help of the previous diagram we understood how address and data bus is connected to the memory
banks. Now we need to understand how this memory banks are enabled and disabled.
CS CS
Microprocessor
8086
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
DO – D7 DATA BUS
ADDRESS BUS
D8 – D15 DATA BUS
As we discussed before that our main aim of memory banking is that the microprocessor should be able to
access 16 bits i.e. 2 bytes i.e. 1 word at a time and process it in 1 machine cycle.
But depending upon instruction and address it accesses bytes or words.
Consider the table on next slide
Byte is accessed in one Word is accessed in one Byte is accessed in one Word is accessed in two
machine cycle as this machine cycle as this machine cycle as this machine cycles. This inst. Is
instruction is accessing a byte instruction is accessing a word instruction is accessing a byte accessing a word starting from
from even memory location. from even memory location. from odd memory location. the odd memory location hence
Hence even bank is enabled Hence even and odd bank both Hence odd bank is enabled in the first machine cycle 1 byte
and odd bank is disabled and are enabled to and data is and even bank is disabled and is accessed from odd bank, in
data is available on the lower available on the lower order data is available on the higher the 2nd machine cycle 2nd byte is
order data bus D0 - D7 data bus D0 - D7 order data bus D8 – D15 accessed from even bank
WR WR
8086
Microprocessor Memory
Data from the microprocessor goes to memory
WR WR
RD OE
Data Bus
8086
Microprocessor Memory
Input Output
Input Output
In the above diagram we see an active high tri state buffer. When the enable i/p is high the buffer acts normally
i.e. allows i/p to appear at the o/p with an increase in current as current is amplified.
Output A Input A
A
Input B Output B
B
Enable
Enable
As we know that data bus is bidirectional, hence we see that buffers are also bidirectional.
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Concept of Octal Bus Transrecievers
Now this octal bus Transreciever consist of such 8 bidirectional buffers.
When data gets transferred between the µp and the memory, ALE goes high during T1 state, address gets
latched with the help of an 8282 octal latch.
After T1 state gets over, T2 starts, ALE goes low, latches gets disabled, data is now available on the multiplexed
bus.
8086 has an o/p pin DEN which is connected to the OE pin of the Transreciever.
When DEN pin is high Transreciever is inactive, when it becomes low Transreciever gets activated.
During the T1 state, this pin is high as no data is available on the multiplexed A/D bus, therefore 8286 is inactive.
As soon as T1 state gets over, DEN pin goes low activating the 8286 Transreciever
As we know that Data bus is bidirectional hence there are two possibilities viz. data transfer from the µp to the
memory, data transfer from memory to the µp.
Active
DEN OE low i/p
Active 8286
low o/p Transreciever
Microprocessor OE
8086
8286
Transreciever
DT/R T
8286
Transreciever
8086
Microprocessor
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(Pin 28 – 26) – Status lines
These are the active low status lines used in maximum mode which reflect the type of operation being carried
out by the processor. It indicates which machine cycle is currently in operation.
Refer table below:
Indication
0 0 0 Interrupt acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code Access
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive
Queue status
1 0 The instruction queue is empty, all registers are cleared due to branching operation
The 74LS373 octal latch has two control inputs ‘Enable’ (G) and ‘Output Control’ (OC).
The ‘Enable’ control is active high and is connected to CLK inputs of all 8 latches. Logic I in CLK input will store the
The ‘Output Control’ signal is active-low and is connected to control inputs of all 8 tri-state buffers.
Logic O will enable the buffers to output data from respective latches.
A db 20h,45,00101101B
B dw 2786h,34h,76,10011010B
C dd 12345678h,32h,6ABFh
D dq 12345678ABCD9876h
E dt 123456789ABCDE874590h
Data ends
Eg: the statement ASSUME DS : DATA indicates to the assembler that the data items related to the program are
available in the logical segment named DATA, and DS register is to be initialized by the segment address for data
segment while loading
ALU
In this instruction, content of the source is transferred or copied into the destination. The source value does not
changes.
The possible combination of source and destination are:
Destination Source
Register Register
Memory Register
Register Memory
Register/memory Data
Register/memory Segment register
Segment register except CS Register/memory
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MOV D,S (Move source data into
destination)
Register can be any 8/16 bit register.
But important is to notice that source and destination should be of same size.
Memory can be indicated by any method as discussed in the addressing modes.
For examples refer class notes
X may be 0 or 1
As reserved by Intel
Refer testint.asm
X may be 0 or 1
As reserved by Intel
Refer testint.asm
Note: The value which is reserved by Intel cannot be changed or manipulated
Eg: if at bit no.6, Intel has reserved a 0, if we try to set that bit, it cannot be set.
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LDS R,Memory (Load DS and given
register {16 bit register} with memory
contents )
This instruction copies the contents of four memory locations in the given register and DS register.
The register R should be of 16 bits. Refer testint.asm
Note: immediate addressing is also not allowed over here
DS
Memory
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LES R,Memory (Load ES and given
register {16 bit register} with memory
contents )
This instruction copies the contents of four memory locations in the given register and ES register.
The register R should be of 16 bits. Refer testint.asm
Note: immediate addressing is also not allowed over here
ES
Memory
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LEA R,EA(OA) (Load effective address
of memory into given register R)
This instruction copies the effective address of memory into the given register R.
The register R should be of 16 bits, as EA or OA is always of 16 bits.
R EA of memory
16 bit register
Destination Source
Register Register
Register Memory
Memory Register
Register/memory Data
CALL
Next
Y instruction
HLT RET