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Le Ectur E14: VLS SI Desi Ign Bas Sed On Cmos S Realiz Zation

1. The document discusses stick diagrams which are used for planning integrated circuit layout and routing. Stick diagrams represent conducting materials with colored lines without specifying width. 2. Rules for stick diagrams are provided, such as red over green representing an nFET and connections specified by X. Metal lines on different layers can cross. 3. Examples of CMOS implementations and their corresponding stick diagrams are given for gates such as inverters and NAND gates.

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Mohamad El-Masry
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43 views

Le Ectur E14: VLS SI Desi Ign Bas Sed On Cmos S Realiz Zation

1. The document discusses stick diagrams which are used for planning integrated circuit layout and routing. Stick diagrams represent conducting materials with colored lines without specifying width. 2. Rules for stick diagrams are provided, such as red over green representing an nFET and connections specified by X. Metal lines on different layers can cross. 3. Examples of CMOS implementations and their corresponding stick diagrams are given for gates such as inverters and NAND gates.

Uploaded by

Mohamad El-Masry
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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1

Leecture 14
VLS
SI desiign bassed on CMOS
S realizzation
S
Stick
D
Diagram
m

ng the layo
out and routing off integrateed circuitss.
9 Useful for plannin
ng or desiign rules are applieed.
9 No spacin
ne of cond
ducting material is represented with a distinct colored
9 Every lin
line of no
o width.
l
allow
w the layoout design
ner to trace signal flow path
hs
9 Colored lines
through conductin
c
ng layers easily in complex
c
i
integrated
d circuits..
w
and
d spacingg are not importantt because the stick diagram
9 The line width
just give the routin
ng and wiiring infoormation.
FET is desscribed byy red over ggreen as shown
s
in the follow
wing figurre.
An nF

Red(Polyy) crossess over Greeen (Activ


ve)
ET is desccribed by the same red over green coding, but the crosssing pointt
A pFE
is conttained witthin an nW
Well Bou
undary as shown in
n the following figu
ure.

ECE
E 511

D Nooha Y. Ahmed
Dr.
A

Stick
k diagrram ru
ules
Only rou
uting is im
mportant n
not the lin
ne width
Red(Polyy) over green(Activve) gives FET
F
Blue(Mettal1) can cross over Red(polly), or Grreen(Activve) withou
ut a
connectioon.

Connectiions betweeen layerss are speccified by X that rep


presents an
a oxide
etch.

ECE
E 511

D Nooha Y. Ahmed
Dr.
A

Metal lin
nes on diffferent layyers (Metaal1 &Metal2) can cross
c
one another.
Contactin
ng two diffferent metal
m
layerrs requiree a via.

ECE
E 511

D Nooha Y. Ahmed
Dr.
A

Inverrter CM
MOS realizatioon and Stick
S
diiagram

OS realization
Inveerter CMO

ECE
E 511

Inverrter CMO
OS stick d
diagram

D Nooha Y. Ahmed
Dr.
A

CMO
OS realiization,, CMOS
S Layou
ut, and Stick d
diagram
m of
NAN
ND2 CM
MOS gatte.

ECE
E 511

D Nooha Y. Ahmed
Dr.
A

Examp
ple :Draw
w the CM
MOS realizzation, th
he stick diiagram an
nd the lay
yout of
AND22 gate , OU
UT = A.B
B.

ECE
E 511

D Nooha Y. Ahmed
Dr.
A

Note th
hat: As much
m
as poossible avooid cutting
g active laayers for not
n increaasing the
layoutt area.
Examp
ple: Re-d
draw the stick
s
diagrram hencce the circcuit layou
ut of CMO
OS
NAND
D2 gate, avoiding
a
aany cuttin
ng in activve regionss.

ECE
E 511

D Nooha Y. Ahmed
Dr.
A

CMO
OS realiization,, stick d
diagram
m, and C
CMOS L
Layout,, of
NOR
R2 CMO
OS gatee.

ECE
E 511

D Nooha Y. Ahmed
Dr.
A

Examp
ple: Draw
w the CM
MOS realizzation and
d the stick
k diagram
m of the fu
unction :
OUT = (A+B+C).D

ECE
E 511

D Nooha Y. Ahmed
Dr.
A

10

VDD

p+
OUT

n+

VSS
A

ECE 511

Dr. Noha Y. Ahmed

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