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DSD

This document outlines the course units and content for an M.Tech course in VLSI/VLSI Design/VLSI System Design. The 5 units cover: 1) minimization and transformation of sequential machines including state equivalence and machine minimization, 2) digital design using components like ROMs, PALs, and PLAs for circuits like adders and multipliers, 3) state machine charts including derivation and realization, 4) fault modeling and test pattern generation techniques for combinational and sequential circuits, and 5) fault diagnosis approaches for sequential circuits. Recommended textbooks are also provided.

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Anil Marturi
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766 views1 page

DSD

This document outlines the course units and content for an M.Tech course in VLSI/VLSI Design/VLSI System Design. The 5 units cover: 1) minimization and transformation of sequential machines including state equivalence and machine minimization, 2) digital design using components like ROMs, PALs, and PLAs for circuits like adders and multipliers, 3) state machine charts including derivation and realization, 4) fault modeling and test pattern generation techniques for combinational and sequential circuits, and 5) fault diagnosis approaches for sequential circuits. Recommended textbooks are also provided.

Uploaded by

Anil Marturi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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M.Tech.

(VLSI/ VLSI DESIGN/VLSI SYSTEM DESIGN)-R13 Regulations


JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
M. Tech I Year I Sem. (VLSI/VLSI Design/VLSi System Design)
DIGITAL SYSTEM DESIGN
(ELECTIVE -I)
UNIT -I:
Minimization and Transformation of Sequential Machines:
The Finite State Model Capabilities and limitations of FSM State equivalence and machine
minimization Simplification of incompletely specified machines.
Fundamental mode model Flow table State reduction Minimal closed covers Races, Cycles
and Hazards.
UNIT -II:
Digital Design:
Digital Design Using ROMs, PALs and PLAs , BCD Adder, 32 bit adder, State graphs for control
circuits, Scoreboard and Controller, A shift and add multiplier, Array multiplier, Keypad Scanner,
Binary divider.
UNIT -III:
SM Charts:
State machine charts, Derivation of SM Charts, Realization of SM Chart, Implementation of Binary
Multiplier, dice game controller.
UNIT -IV:
Fault Modeling & Test Pattern Generation:
Logic Fault model Fault detection & Redundancy- Fault equivalence and fault location Fault
dominance Single stuck at fault model Multiple stuck at fault models Bridging fault model.
Fault diagnosis of combinational circuits by conventional methods Path sensitization techniques,
Boolean Difference method Kohavi algorithm Test algorithms D algorithm, PODEM, Random
testing, Transition count testing, Signature analysis and test bridging faults.
UNIT -V:
Fault Diagnosis in Sequential Circuits:
Circuit Test Approach, Transition Check Approach State identification and fault detection
experiment, Machine identification, Design of fault detection experiment
TEXT BOOKS:
th
1. Fundamentals of Logic Design Charles H. Roth, 5 Ed., Cengage Learning.
2. Digital Systems Testing and Testable Design Miron Abramovici, Melvin A.
Breuer and Arthur D. Friedman- John Wiley & Sons Inc.
3. Logic Design Theory N. N. Biswas, PHI
REFERENCE BOOKS:
nd
1. Switching and Finite Automata Theory Z. Kohavi , 2 Ed., 2001, TMH
th
2. Digital Design Morris Mano, M.D.Ciletti, 4 Edition, PHI.
3. Digital Circuits and Logic Design Samuel C. Lee , PHI

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