VHDL Portfolio

Constraints file:
# UCF file for the Papilio One 500K & 250K boards
# Generated by pin_converter, written by Kevin Lindsey
# https://github.com/thelonious/papilio_pins/tree/development/pin_converter
#
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Main board wing pin [] to FPGA pin Pxx map

-------C-------------B-------------A------[GND] [C00] P91
[GND] [B00] P85
P86 [A15]
[2V5] [C01] P92
[2V5] [B01] P83
P84 [A14]
[3V3] [C02] P94
[3V3] [B02] P78
P79 [A13]
[5V0] [C03] P95
[5V0] [B03] P71
P70 [A12]
[C04] P98
[B04] P68
P67 [A11] [5V0]
[C05] P2
[B05] P66
P65 [A10] [3V3]
[C06] P3
[B06] P63
P62 [A09] [2V5]
[C07] P4
[B07] P61
P60 [A08] [GND]
[GND] [C08] P5
[GND] [B08] P58
P57 [A07]
[2V5] [C09] P9
[2V5] [B09] P54
P53 [A06]
[3V3] [C10] P10
[3V3] [B10] P41
P40 [A05]
[5V0] [C11] P11
[5V0] [B11] P36
P35 [A04]
[C12] P12
[B12] P34
P33 [A03] [5V0]
[C13] P15
[B13] P32
P26 [A02] [3V3]
[C14] P16
[B14] P25
P23 [A01] [2V5]
[C15] P17
[B15] P22
P18 [A00] [GND]

## Prohibit the automatic placement of pins that are connected to VCC or GND for
configuration.
CONFIG PROHIBIT=P99;
CONFIG PROHIBIT=P43;
CONFIG PROHIBIT=P42;
CONFIG PROHIBIT=P39;
CONFIG PROHIBIT=P49;
CONFIG PROHIBIT=P48;
CONFIG PROHIBIT=P47;
#CONFIG PART=XC3S250E-VQ100-4;
#CONFIG PART=XC3S500E-VQ100-4;
NET CLK
LOC="P89"
CLK
#NET RX
LOC="P90"
# RX
#NET TX
LOC="P88"
# TX
#NET Seg7_AN(3) LOC="P18"
# A0
#NET Seg7_DP
LOC="P23"
# A1
#NET Seg7_AN(2) LOC="P26"
# A2
#NET Seg7_E
LOC="P33"
# A3
#NET Seg7_F
LOC="P35"
# A4
#NET Seg7_C
LOC="P40"
# A5
#NET Seg7_D
LOC="P53"
# A6
#NET Seg7_A
LOC="P57"

| IOSTANDARD=LVTTL | PERIOD=31.25ns;
| IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;

| IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP;

| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;

# A7
#NET Seg7_AN(1) LOC="P60"
# A8
#NET Seg7_G
LOC="P62"
# A9
#NET Seg7_B
LOC="P65"
# A10
#NET Seg7_AN(0) LOC="P67"
# A11
#NET SPI_CS
LOC="P70"
# A12
#NET SPI_MISO
LOC="P79"
# A13
#NET SPI_MOSI
LOC="P84"
# A14
#NET SPI_SCLK
LOC="P86"
# A15
#NET VGA_VSYNC
LOC="P85"
# B0
#NET VGA_HSYNC
LOC="P83"
# B1
#NET VGA_BLUE(0) LOC="P78"
# B2
#NET VGA_BLUE(1) LOC="P71"
# B3
#NET VGA_GREEN(0) LOC="P68"
# B4
#NET VGA_GREEN(1) LOC="P66"
# B5
#NET VGA_GREEN(2) LOC="P63"
# B6
#NET VGA_RED(0) LOC="P61"
# B7
#NET VGA_RED(1) LOC="P58"
# B8
#NET VGA_RED(2) LOC="P54"
# B9
#NET AUDIO
LOC="P41"
# B10
#NET JOY_RIGHT
LOC="P36"
# B11
#NET JOY_LEFT
LOC="P34"
# B12
#NET JOY_DOWN
LOC="P32"
# B13
#NET JOY_UP
LOC="P25"
# B14
#NET JOY_SELECT LOC="P22"
# B15
#NET SWITCH(7)
LOC="P4"
C0
#NET SWITCH(6)
LOC="P3"
C1
#NET SWITCH(5)
LOC="P2"
C2
#NET SWITCH(4)
LOC="P98"
# C3
#NET SWITCH(3)
LOC="P95"
# C4
NET SWITCH(2)
LOC="P94"

| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;

| IOSTANDARD=LVTTL;

| IOSTANDARD=LVTTL;

| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;
| IOSTANDARD=LVTTL;

# C5
NET SWITCH(1)
# C6
NET SWITCH(0)
# C7
NET LED(0)
# C8
NET LED(1)
# C9
NET LED(2)
C10
NET LED(3)
C11
NET LED(4)
C12
NET LED(5)
C13
NET LED(6)
C14
NET LED(7)
C15
#NET JTAG_TMS
# JTAG_TMS
#NET JTAG_TCK
# JTAG_TCK
#NET JTAG_TDI
# JTAG_TDI
#NET JTAG_TDO
# JTAG_TDO
#NET FLASH_CS
# FLASH_CS
#NET FLASH_CK
# FLASH_CK
#NET FLASH_SI
# FLASH_SI
#NET FLASH_SO
# FLASH_SO

LOC="P92"

| IOSTANDARD=LVTTL;

LOC="P91"

| IOSTANDARD=LVTTL;

LOC="P17"

| IOSTANDARD=LVTTL;

LOC="P16"

| IOSTANDARD=LVTTL;

LOC="P15" | IOSTANDARD=LVTTL;

LOC="P12" | IOSTANDARD=LVTTL;

LOC="P11" | IOSTANDARD=LVTTL;

LOC="P10" | IOSTANDARD=LVTTL;

LOC="P9" | IOSTANDARD=LVTTL;

LOC="P5" | IOSTANDARD=LVTTL;

LOC="P75" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;

LOC="P77" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;
LOC="P100" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;
LOC="P76" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;
LOC="P24" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;
LOC="P50" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;
LOC="P27" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;
LOC="P44" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP;

VHDL Files by Chapter:

Chapter 6: Wire Switches to LEDs
Chapter 7: Test out AND/OR/XOR Gates
---------------------------------------------------------------------------------- Company: Howard Community College
-- Engineer: Renita Mwangachuchu
--- Create Date:
07:52:39 08/13/2015
-- Design Name:
Switches_LEDs
-- Module Name:
Switches_LEDs - Behavioral
-- Project Name: Switches_LEDs
-- Target Devices: Papilio One
-- Tool versions: Chapter 7 Challenges- Testing OR/AND/NOT/XOR/XNOR gate descrip
tions.
--- Dependencies:
--

-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Switches_LEDs is
Port ( switch_0 : in STD_LOGIC;
switch_1 : in STD_LOGIC;
LED_0 : out STD_LOGIC;
LED_1 : out STD_LOGIC;
LED_2 : out STD_LOGIC;
LED_3 : out STD_LOGIC;
LED_4 : out STD_LOGIC);
end Switches_LEDs;
architecture Behavioral of Switches_LEDs is
begin
LED_0 <= NOT(switch_0) AND switch_1; -- will light if switch_1 is up
LED_1 <= NOT(NOT(switch_0) OR NOT(switch_1)); -- will not light if switch_0 or s
witch_1 are down
LED_2 <= NOT(NOT(switch_0) AND NOT(switch_1)); -- will not light if switch_0 and
switch_1 are down
LED_3 <= (switch_0 NOR switch_1) NOR (switch_0 NOR switch_1); --should do the sa
me thing
LED_4 <= (NOT(switch_0) AND switch_1) OR (switch_0 AND NOT(switch_1)); --XOR fun
ction of switch_0 & switch_1
end Behavioral;
Chapter 8: Signal buses
[Self-Explanatory]
Chapter 9: Adder/Subtractor
---------------------------------------------------------------------------------- Company: Howard Community College
-- Engineer: Renita Mwangachuchu
--- Create Date:
07:52:39 08/13/2015
-- Design Name: Switches_LEDs
-- Module Name:
Switches_LEDs - Behavioral
-- Project Name: Switches_LEDs
-- Target Devices:
Papilio One

-- Tool versions:
-- Description:
Adds when Joy stick is pressed, otherwise subtracts Switches(
7 downto 4) from Switches(3 downto 0)
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponent*s.all;
entity Switches_LEDs is
Port ( switches : in STD_LOGIC_VECTOR(7 downto 0);
JOY_SELECT : in STD_LOGIC;
LEDs
: out STD_LOGIC_VECTOR(7 downto 3));
end Switches_LEDs;
architecture Behavioral of Switches_LEDs is
--Declaring signals to be used within the entity's architecture
signal x
:
STD_LOGIC_VECTOR(3 downto 0);
signal y
:
STD_LOGIC_VECTOR(3 downto 0);
signal carry
:
STD_LOGIC_VECTOR(3 downto 0);
signal result :
STD_LOGIC_VECTOR(4 downto 0) := (others =>'0');
signal joy
: STD_LOGIC := '0';
begin
--Flips the result into a readable order (left to right) and connects to LEDs.
LEDs <= result(4 downto 0);
--Assign switches 0-3 to the signal x.
x <= switches(3 downto 0);
--Assign switches 4-7 to the signal y.
y <= switches(7 downto 4);
--Assign joy stick to a signal
joy <= JOY_SELECT;
--Gives the first bit of sum result
carry(3)
<= joy;
result(0)
<= x(0) XOR (y(0) XOR carry(3));
--Something about the code right here makes subtracter add 1 to everything it su
btracts... lol.
carry(0)
<= (x(0) AND (y(0) XOR carry(3))) OR (carry(3) AND x(0)) OR (car
ry(3) AND y(0));

--Gives the second bit of sum result

result(1)
<= x(1) XOR y(1) XOR carry(3) XOR carry(0);
carry(1)
<= (x(1) AND (y(1) XOR carry(3))) OR (carry(0) AND x(1)) OR (car
ry(0) AND (y(1) XOR carry(3)));
--Gives the third bit of sum result
result(2)
<= x(2) XOR y(2) XOR carry(3) XOR carry(1);
carry(2)
<= (x(2) AND (y(2) XOR carry(3))) OR (carry(1) AND x(2)) OR (car
ry(1) AND (y(2) XOR carry(3)));
--Gives the fourth bit of sum result
result(3)
<= x(3) XOR y(3) XOR carry(3) XOR carry(2);
--The sign bit.
result(4)
<= (x(3) AND (y(3) XOR carry(3))) OR (carry(2) AND x(3)) OR (car
ry(2) AND (y(3) XOR carry(3)));
end Behavioral;
--THAT'S ALL FOLKS!

Chapter 10: Counter that counts in seconds

[Reused in Chapter 14!]

Chapter 11: Timing Constraints with Asynchronous Counter

---------------------------------------------------------------------------------- Company: Howard Community College
-- Engineer: Renita Mwangachuchu
--- Create Date:
07:52:39 08/13/2015
-- Design Name:
Switches_LEDs
-- Module Name:
Switches_LEDs - Behavioral
-- Project Name:
Switches_LEDs
-- Target Devices: Papilio One
-- Tool versions:
-- Description: Learning about timing constraints. Comparing time for different
design techniques.
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values

use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponent*s.all;
entity Switches_LEDs is
Port ( CLK : in STD_LOGIC;
LED : out STD_LOGIC_VECTOR(7 downto 0));
end Switches_LEDs;
architecture Behavioral of Switches_LEDs is
--Declaring signals to be used within the entity's architecture
signal counter
:
STD_LOGIC_VECTOR(29 downto 0) := (others
=>'0');
begin
--Assign binary counter signals to LEDs. [Must be done before if statement but w
ithin the architecture]
LED(7 downto 0) <= counter(29 downto 22);
--begin process using clock for counter
count: process(CLK)
begin
--frequency counter eats cycles per second
if (rising_edge(CLK)) then
counter <= counter+1;
end if;
end process;
-- end process
end Behavioral;
--THAT'S ALL FOLKS!
Chapter 13: Modules- Two switches control two counters (reuses counter30 from Ch
11)
---------------------------------------------------------------------------------- Company: Howard Community College
-- Engineer: Renita Mwangachuchu
--- Create Date:
07:52:39 08/13/2015
-- Design Name:
Modules
-- Module Name:
Switches_LEDs - Behavioral
-- Project Name: Switches_LEDsEDs
-- Target Devices: Papilio One
-- Tool versions:
-- Description: Test the switches, mastery of modules test. Instantiates Ch11 co
unter.
--- Dependencies:
--

-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-----------------------------------------------------------------------------------Library declarations
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;
----------------------------------------------------------------------------------ENTITY-entity Switches_LEDs is
Port ( CLK : in STD_LOGIC;
SWITCH
: in STD_LOGIC_VECTOR(1 downto 0);
LED : out STD_LOGIC_VECTOR(7 downto 0));
end Switches_LEDs;
--ARCHITECTURE-architecture Behavioral of Switches_LEDs is
--Declaring signals to be used within the entity's architecture
signal count1
signal count2

:
:

STD_LOGIC_VECTOR(3 downto 0) := (others =>'0');

STD_LOGIC_VECTOR(3 downto 0) := (others =>'0');

--COMPONENT-- "same area of code as the signal declarations."

COMPONENT counter30
PORT(
CLK : IN std_logic;
enable : IN std_logic;
count : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;

begin
--INSTANCES-- "under Begin in Architecture"
Inst_count1: counter30 PORT MAP(
CLK => CLK,
enable => SWITCH(0),
count => count1
);
Inst_count2: counter30 PORT MAP(
CLK => CLK,
enable => SWITCH(1),
count => count2
);
--Assign binary counter signals to LEDs. [Must be done before if stateme
nt but within the architecture]
LED(3 downto 0) <= count1(3 downto 0);
LED(7 downto 4) <= count2(3 downto 0);

--begin process using module for count2

end Behavioral;

--THAT'S ALL FOLKS!

Chapter 14: Seven Segment Display- Hex Stopwatch
---------------------------------------------------------------------------------- Company: Howard Community College
-- Engineer: Renita Mwangachuchu
--- Create Date:
19:56:30 10/06/2015
-- Design Name:
Segmented Switches_LEDs
-- Module Name:
Switches_LEDs - Behavioral
-- Project Name: Hex Stop Watch
-- Target Devices: Papilio One
-- Tool versions:
-- Description: Connects all the modules to create the Hex Stop Watch
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Main is
Port ( CLK : in STD_LOGIC;
JOY_SELECT: in STD_LOGIC;
SWITCH : in STD_LOGIC_VECTOR (1 downto 0);
Seg7_AN : out STD_LOGIC_VECTOR (3 downto 0);
Seg7_A : out STD_LOGIC;
Seg7_B : out STD_LOGIC;
Seg7_C : out STD_LOGIC;
Seg7_D : out STD_LOGIC;
Seg7_E : out STD_LOGIC;
Seg7_F : out STD_LOGIC;
Seg7_G : out STD_LOGIC;
Seg7_DP : out STD_LOGIC);
end Main;
architecture Behavioral of Main is

-------SIGNALS----------Clock based signals

signal seconds : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
signal digitcount
: STD_LOGIC_VECTOR(1 downto 0) := (others => '0');
--Hexadecimal value based signals. These will be decoded for the displays.
signal digit0
: STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
signal digit1
: STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
signal digit2
: STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
signal digit3
: STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
signal displayed : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
-------------------------------COMPONENTS---------Translates binary values of hexademical counter into 7seg display signals.
COMPONENT Binary_Decoder
PORT(
binary : IN std_logic_vector(3 downto 0);
Seg7_A : OUT std_logic;
Seg7_B : OUT std_logic;
Seg7_C : OUT std_logic;
Seg7_D : OUT std_logic;
Seg7_E : OUT std_logic;
Seg7_F : OUT std_logic;
Seg7_G : OUT std_logic;
Seg7_DP : OUT std_logic
);
END COMPONENT;
--Contains counter that counts in second and counter that muxes digits at 200Hz.
COMPONENT Counters
PORT(
JOY_SELECT : IN std_logic;
SWITCH : IN std_logic_vector(1 downto 0);
CLK : IN std_logic;
seconds : OUT std_logic_vector(15 downto 0);
digitcounter : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
begin --The beginning of the architecture.----------INSTANCES------------Adding behavioral of digits 0-3 to the design
Digit: Binary_Decoder PORT MAP(
binary => displayed,
Seg7_A => Seg7_A,
Seg7_B => Seg7_B,
Seg7_C => Seg7_C,
Seg7_D => Seg7_D,
Seg7_E => Seg7_E,
Seg7_F => Seg7_F,
Seg7_G => Seg7_G,
Seg7_DP => Seg7_DP
);
--Drives signals "seconds" and "digitcount"
Inst_Counters: Counters PORT MAP(

JOY_SELECT => JOY_SELECT,

SWITCH => SWITCH,
seconds => seconds,
digitcounter => digitcount,
CLK => CLK
);
-------------------------------hertz: process( CLK )
-begin
-if (rising_edge(CLK)) then
-hertzcount <= hertzcount+1;
---if hertzcount = 159999 then
-hertzcount <= (others => '0');
-digitcount <= digitcount+1;
-end if;
-end if;
-end process;
decoder: process( digitcount, digit0, digit1, digit2, digit3 ) --Displays varied
digits on anodes.
begin
-----------------------------if (digitcount = 00) then ---0
Seg7_AN
<= "1110";
--Activate anode 0.
displayed
<= digit3; --Digit 0 is
displayed on anode 0.
------------------------------.
else if (digitcount = 01) then --1
Seg7_AN
<= "1101"; --Act
ivate anode 1.
displayed
<= digit2; --Digit 1 is
displayed on anode 1.
-----------------------------else if (digitcount = 10) then --2
Seg7_AN
<= "1011
"; --Activate anode 2.
displayed
<= digit1; --Dig
it 2 is displayed on anode 2.
------------------------------.
else if (digitcount = 11) then -3
Seg7_AN
<= "0111"; --Activate anode 3.
displayed
<= digit
0; --Digit 3 is displayed on anode 3.
end if;
------------------------------.
end if;
-----------------------------end if;
------------------------------.
end if;
-----------------------------end process;

end Behavioral;
---------------------------------------------------------------------------------- Company: Howard Community College
-- Engineer: Renita Mwangachuchu
--- Create Date:
19:56:30 10/06/2015
-- Design Name:
Segmented Switches_LEDs
-- Module Name:
Switches_LEDs - Behavioral
-- Project Name: Hex Stop Watch
-- Target Devices: Papilio One
-- Tool versions:
-- Description: Decodes binary digits into hexadecimal.
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Binary_Decoder is
Port ( binary : in STD_LOGIC_VECTOR (3 downto 0);
Seg7_A : out STD_LOGIC;
Seg7_B : out STD_LOGIC;
Seg7_C : out STD_LOGIC;
Seg7_D : out STD_LOGIC;
Seg7_E : out STD_LOGIC;
Seg7_F : out STD_LOGIC;
Seg7_G : out STD_LOGIC;
Seg7_DP : out STD_LOGIC);
end Binary_Decoder;
architecture Behavioral of Binary_Decoder is
begin
decoder: process( binary(3 downto 0) )
begin
CASE binary(3 downto 0) IS
WHEN "0000" => --0

WHEN

WHEN

WHEN

WHEN

WHEN

WHEN

Seg7_A <= '0';

Seg7_B <= '0';
Seg7_C <= '0';
Seg7_D <= '0';
Seg7_E <= '0';
Seg7_F <= '0';
Seg7_G <= '1';
Seg7_DP
<=
"0001" => --1
Seg7_A <= '1';
Seg7_B <= '0';
Seg7_C <= '0';
Seg7_D <= '1';
Seg7_E <= '1';
Seg7_F <= '1';
Seg7_G <= '1';
Seg7_DP
<=
"0010" => --2
Seg7_A <= '0';
Seg7_B <= '0';
Seg7_C <= '1';
Seg7_D <= '0';
Seg7_E <= '0';
Seg7_F <= '1';
Seg7_G <= '0';
Seg7_DP
<=
"0011" => --3
Seg7_A <= '0';
Seg7_B <= '0';
Seg7_C <= '0';
Seg7_D <= '0';
Seg7_E <= '1';
Seg7_F <= '1';
Seg7_G <= '0';
Seg7_DP
<=
"0100" => --4
Seg7_A <= '1';
Seg7_B <= '0';
Seg7_C <= '0';
Seg7_D <= '1';
Seg7_E <= '1';
Seg7_F <= '0';
Seg7_G <= '0';
Seg7_DP
<=
"0101" => --5
Seg7_A <= '0';
Seg7_B <= '1';
Seg7_C <= '0';
Seg7_D <= '0';
Seg7_E <= '1';
Seg7_F <= '0';
Seg7_G <= '0';
Seg7_DP
<=
"0110" => --6
Seg7_A <= '0';
Seg7_B <= '1';
Seg7_C <= '0';
Seg7_D <= '0';
Seg7_E <= '0';
Seg7_F <= '0';

'0';

'0';

'0';

'0';

'0';

'0';

WHEN

WHEN

WHEN

WHEN

WHEN

WHEN

WHEN

Seg7_G <= '0';

Seg7_DP
<=
"0111" => --7
Seg7_A <= '0';
Seg7_B <= '0';
Seg7_C <= '0';
Seg7_D <= '1';
Seg7_E <= '1';
Seg7_F <= '1';
Seg7_G <= '1';
Seg7_DP
<=
"1000" => --8
Seg7_A <= '0';
Seg7_B <= '0';
Seg7_C <= '0';
Seg7_D <= '0';
Seg7_E <= '0';
Seg7_F <= '0';
Seg7_G <= '0';
Seg7_DP
<=
"1001" => --9
Seg7_A <= '0';
Seg7_B <= '0';
Seg7_C <= '0';
Seg7_D <= '0';
Seg7_E <= '1';
Seg7_F <= '0';
Seg7_G <= '0';
Seg7_DP
<=
"1010" => --10/A
Seg7_A <= '0';
Seg7_B <= '0';
Seg7_C <= '0';
Seg7_D <= '1';
Seg7_E <= '0';
Seg7_F <= '0';
Seg7_G <= '0';
Seg7_DP
<=
"1011" => --11/B
Seg7_A <= '0';
Seg7_B <= '0';
Seg7_C <= '0';
Seg7_D <= '0';
Seg7_E <= '0';
Seg7_F <= '0';
Seg7_G <= '0';
Seg7_DP
<=
"1100" => --12/C
Seg7_A <= '0';
Seg7_B <= '1';
Seg7_C <= '1';
Seg7_D <= '0';
Seg7_E <= '0';
Seg7_F <= '0';
Seg7_G <= '1';
Seg7_DP
<=
"1101" => --13/D
Seg7_A <= '0';
Seg7_B <= '0';
Seg7_C <= '0';

'0';

'0';

'0';

'0';

'1';

'1';

'1';

Seg7_D <= '0';

Seg7_E <= '0';
Seg7_F <= '0';
Seg7_G <= '1';
Seg7_DP
<= '1';
WHEN "1110" => --14/E
Seg7_A <= '0';
Seg7_B <= '1';
Seg7_C <= '1';
Seg7_D <= '0';
Seg7_E <= '0';
Seg7_F <= '0';
Seg7_G <= '0';
Seg7_DP
<= '1';
WHEN OTHERS => --15/F
Seg7_A <= '0';
Seg7_B <= '1';
Seg7_C <= '1';
Seg7_D <= '1';
Seg7_E <= '0';
Seg7_F <= '0';
Seg7_G <= '0';
Seg7_DP
<= '1';
END CASE;
end process;
end Behavioral;
---------------------------------------------------------------------------------- Company: Howard Community College
-- Engineer: Renita Mwangachuchu
--- Create Date:
19:29:19 02/11/2015
-- Design Name: Chapter 10 Using a Clock Signal
-- Module Name:
Counter_LEDs - Behavioral
-- Project Name: HexStopWatch
-- Target Devices: Papilio One
-- Tool versions:
-- Description: Uses chapter 10's seconds counter for hex stop watch. Also cont
rols anode mux.
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.

--library UNISIM;
--use UNISIM.VComponents.all;
entity Counters is
Port ( JOY_SELECT: in STD_LOGIC;
SWITCH
: in STD_LOGIC_VECTOR (1
downto 0);
seconds
: out STD_LOGIC_VECTOR (15 downto 0);
digitcounter : out STD_LOGIC_VECTOR (1 downto 0);
CLK
: in STD_LOGIC
);
end Counters;
architecture Behavioral of Counters is
signal
signal
signal
signal

ns_counter : STD_LOGIC_VECTOR(25 downto 0) := (others => '0');

ns_counter2 : STD_LOGIC_VECTOR(18 downto 0) := (others => '0');
counter : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
digitmux: STD_LOGIC_VECTOR(1 downto 0) := "00";

begin
seconds <= counter;
digitcounter <= digitmux;
count_clk: process(CLK)
begin
if (rising_edge(CLK)) then
ns_counter2 <= ns_counter2+1;
ns_counter <= ns_counter+1;
if (ns_counter=199999) then
digitmux <= digitmux+1;
ns_counter2 <= (others => '0');
if (digitmux=11) then
digitmux <= (others => '0');
end if;
end if;
if (ns_counter=31999999) then -- when 32mil cy
lces/1 second goes by
if (JOY_SELECT='0') then
counter <= (others => '0');
else
if (switch(0)='0') then
-- switch(1) off, begin counting
if (switch(1)='0') then
-- switch(0) on, count up
counter <= count
er+1;
else
-- switch(0) off, count down
counter <= count
er-1;
end if;
else
-- switch(1) on, pause
counter <= counter;
end if;
end if;
ns_counter <= (others => '0'); --after c
ounting, reset cycle/second counter to 0 and count to 32mil again

end if;
end if;
end process;
end Behavioral;

Chapter 15: Block ROM Flashylights

---------------------------------------------------------------------------------- Company: Howard Community College
-- Engineer: Renita Mwangachuchu
--- Create Date:
15:22:18 10/19/2015
-- Design Name:
Flashylights
-- Module Name:
clocked_LEDs - Behavioral
-- Project Name: clocked_LEDs
-- Target Devices: Papilio One 500k
-- Tool versions:
-- Description: Uses IP Core generated counter and ROM to create pattern on LEDs
.
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
LIBRARY XilinxCoreLib;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity clocked_LEDs is
Port ( CLK : in STD_LOGIC;
LED : out STD_LOGIC_VECTOR (7 downto 0));
end clocked_LEDs;
architecture Behavioral of clocked_LEDs is
--The component of the IP CORE generated counter 30 module
COMPONENT counter30
PORT (
clk : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(29 DOWNTO 0)

);
END COMPONENT;
COMPONENT memory
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
--the signal for the counter30 module:
signal counter : STD_LOGIC_VECTOR(29 downto 0) := (others => '0');
attribute box_type : string;
attribute box_type of counter30 : component is "black_box";
attribute box_type of memory : component is "black_box";
begin
--This is an Instance of the IP CORE generated counter30 module.
Inst_counter30 : counter30
PORT MAP (
clk => CLK,
q => counter
);
Inst_memory : memory
PORT MAP (
clka => CLK,
addra => counter(29 downto 20),
douta => LED
);
end Behavioral;
Chapter 16: Audio jack and Digital to Analog Converter
---------------------------------------------------------------------------------- Company: Howard Community College
-- Engineer: Renita Mwangachuchu
--- Create Date:
15:22:18 10/19/2015
-- Design Name:
Audio Wave File
-- Module Name:
clocked_LEDs - Behavioral
-- Project Name:
DAC Practice
-- Target Devices: Papilio One (Spartan 3E -- XC3S500E-5VQ100)
-- Tool versions:
-- Description: Plays a tone of harmonic frequencies at different octaves depend
ent on counter address speed.
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--

--------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY XilinxCoreLib;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity clocked_LEDs is
Port ( CLK : in STD_LOGIC;
AUDIO : out STD_LOGIC);
end clocked_LEDs;
architecture Behavioral of clocked_LEDs is
--The component of the IP CORE generated counter 30 module
COMPONENT counter30
PORT (
clk : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(29 DOWNTO 0)
);
END COMPONENT;
--The memory component.
--Finally just used MATLAB to generate coeffients for initializing coe file rath
er than using calculator.
COMPONENT memory
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
--The digital to analog converter.
COMPONENT dac8
PORT(
CLK : IN std_logic;
Data : IN std_logic_vector(7 downto 0);
PulseStream : OUT std_logic
);
END COMPONENT;
--the signal for the counter30 module:
signal counter : STD_LOGIC_VECTOR(29 downto 0) := (others => '0');
--the signal that transfers sine wave values to analog converter.
signal datastream: STD_LOGIC_VECTOR(7 downto 0) :=(others => '0');

--Attribute declarations to get rid of black box warnings.

attribute box_type : string;
attribute box_type of counter30 : component is "black_box";
attribute box_type of memory : component is "black_box";
---------------------------------------------------------begin
AUDIO <= counter(16);
--This is an Instance of the IP CORE generated counter30 module.
Inst_counter30 : counter30
PORT MAP (
clk => CLK,
q => counter
);
--Increments the memory at 381Hz (15 downto 6). Sine wave values used as initial
izing coe file.
Inst_memory : memory
PORT MAP (
clka => CLK,
addra => counter(15 downto 6),
douta => datastream(7 downto 0)
);
--The Analog converter that converts data stream from memory to binary stream (a
nalog signal)
Inst_dac8: dac8 PORT MAP(
CLK => CLK,
Data => datastream(7 downto 0),
PulseStream => open
);
end Behavioral;
---------------------------------------------------------------------------------- Company: Howard Community College
-- Engineer: Renita Mwangachuchu
--- Create Date:
15:23:56 10/26/2015
-- Design Name:
dac8
-- Module Name:
dac8 - Behavioral
-- Project Name: Audio Project
-- Target Devices: Papilio One 500K
-- Tool versions:
-- Description: A makeshift digital to analog converter for Audio project
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
---------------------------------------------------------------------------------library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dac8 is
Port ( CLK : in STD_LOGIC;
Data : in STD_LOGIC_VECTOR (7 downto 0);
PulseStream : out STD_LOGIC);
end dac8;
architecture Behavioral of dac8 is
signal sum : STD_LOGIC_VECTOR(8 downto 0);
begin
Pulsestream <= sum(8);
process (CLK, sum)
begin
if (rising_edge(CLK)) then
sum <= ("0" & sum(7 downto 0)) + ("0" &data);
end if;
end process;
end Behavioral;
Chapter 17: Combination Lock (Password: LOGIC)
---------------------------------------------------------------------------------- Company: Howard Community College
-- Engineer: Renita Mwangachuchu
--- Create Date:
18:24:33 12/03/2015
-- Design Name:
Combination LockMech
-- Module Name:
LockMech - Behavioral
-- Project Name: MyCombination
-- Target Devices: Papilio One 500K
-- Tool versions:
-- Description: Makes a combination lock out of switches, LEDs, and joystick.
-Reuses Ch15 flashylights and counter30 f
rom Ch11
-- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity LockMech is
Port ( CLK : in STD_LOGIC;
SWITCH : in STD_LOGIC_VECTOR (7 downto 0);
LED : out STD_LOGIC_VECTOR (7 downto 0));
end LockMech;
architecture Behavioral of LockMech is
--Components
COMPONENT counter30
PORT (
clk : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(29 DOWNTO 0)
);
END COMPONENT;
COMPONENT flashylights
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
attribute box_type: string;
attribute box_type of counter30: component is "black_box";
attribute box_type of flashylights: component is "black_box";
--Constants
constant error_state
constant start_state
constant first_state
constant second_state:
constant third_state
constant open_state
--Signals
signal state
');
signal flashy
');
signal counter
;
begin
--Instances
CounterMod : counter30

:
STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
:
STD_LOGIC_VECTOR(3 downto 0) := "0001";
: STD_LOGIC_VECTOR(3 downto 0) := "0010";
STD_LOGIC_VECTOR(3 downto 0) := "0011";
: STD_LOGIC_VECTOR(3 downto 0) := "0100";
: STD_LOGIC_VECTOR(3 downto 0) := "0101";
: STD_LOGIC_VECTOR(3 downto 0) := (others => '0
: STD_LOGIC_VECTOR(7 downto 0) := (others => '0
:

STD_LOGIC_VECTOR(29 downto 0) := (others => '0')

PORT MAP (
clk => CLK,
q => counter
);
MemoryMod : flashylights
PORT MAP (
clka => CLK,
addra => counter(29 downto 20),
douta => flashy
);
--Processes
fsm : process(CLK, SWITCH, state, flashy)
begin
if (rising_edge(CLK)) then
if (SWITCH(0) = '1') then
case state is --WHEN the current state is in....
when start_state =>
--in start state...
case SWITCH(7 downto 1) is
--LEDs do start sequence, look at the switches for next state
when "0011001" =>
state
start_state; --"L" to stay in start state
when "1111001" =>
state <= first_state; --"O" to move to first state
when others =>
state <= error_state;
LED <= "10000001";
end case;
when first_state => --in first state...
case SWITCH(7 downto 1) is
--No LEDs, look at the switches for next state
when "1111001" =>
state
first_state; --"O"
when "1110001" =>
state <= second_state; --"G"
when others =>
state <= error_state;
LED <= (others => '0');
end case;
when second_state =>
--in second state
case SWITCH(7 downto 1) is
--No LEDs, look at the switches for next state
when "1110001" =>
state
second_state; --"G"
when "1001001" =>
state <= third_state; --"I"
when others =>
state <= error_state;
end case;
when third_state => -- in third state
case SWITCH(7 downto 1) is
--No LEDs, look at the switches for open state
when "1001001" =>
state
third_state; --"I"
when "1100001" =>
state <= open_state; --"C"
when others =>
state <= error_state;

<=

<=

<=

<=

end case;
when open_state=>

--in open state

(all LEDs turn on).

case SWITCH(7 downto 1) is
--light all LEDs, look at switches for start state
when "0000000" =>
state <=
error_state; --will stay open til all switches 0.
when others =>
state <= open_state;
LED <= (others => '1');
end case;
when others =>
--in error state, ALSO INIT
IAL STATE
case SWITCH(7 downto 1) is
--LEDs flash, look at the switches for next state.
when "0011001" =>
state <=
start_state;-- First letter "L".
when others =>
state <= error_state;
LED <= flashy;
end case;
end case;
end if;
end if;
end process;
end Behavioral;
Chapter 18: Add a DCM to a project (reuses Ch 10)
[Made seconds counter twice as fast by converting onboard clock from 32MHz to 64
MHz]
Chapter 19: Generate an image on the VGA monitor- alter a design (Reused in fina
l project)
[Used again in final project]
Chapter 20: Create a TX RS-232 signal
---------------------------------------------------------------------------------- Company: Howard Community College
-- Engineer: Renita Mwangachuchu
--- Create Date:
15:40:55 12/08/2015
-- Design Name: TX
-- Module Name:
TX - Behavioral
-- Project Name: PCTalk
-- Target Devices: Papilio One 500K
-- Tool versions:
-- Description: Creates RS-232 signal that can be intercepted by Putty at 9600 b
aud.
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created

-- Additional Comments:
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TX is
Port ( CLK : in STD_LOGIC;
SWITCH : in STD_LOGIC_VECTOR(7 downto 0);
JOY_SELECT : in STD_LOGIC;
data_out : out STD_LOGIC);
end TX;
architecture Behavioral of TX is
signal busyshiftreg : STD_LOGIC_VECTOR(9 downto 0) := (others => '0');
signal datashiftreg : STD_LOGIC_VECTOR(9 downto 0) := (others => '1');
signal counter : STD_LOGIC_VECTOR(12 downto 0) := (others => '0');
signal databyte : STD_LOGIC_VECTOR(7 downto 0) := "01011010" ;
--signal busy_out : STD_LOGIC;
begin
data_out <= datashiftreg(0);
--busy_out <= busyshiftreg(0);
databyte <= SWITCH;
TXshiftreg : process(CLK)
begin
if (rising_edge(CLK)) then
if (JOY_SELECT = '0') then --When the Joy stick is pressed
if busyshiftreg(0) = '0' then -- if the transmitter is n
ot busy then
busyshiftreg <= (others => '1'); --set busyshift
register to busy
datashiftreg <= '1' & databyte & '0'; -- load da
tabyte into shift register
counter <= (others => '0'); --reset counter
else
if counter = 3332 then --sending data bits at 96
00 baud
datashiftreg <= '1' & datashiftreg(9 dow
nto 1); -- shift register sends databytes in serial stream
busyshiftreg <= '0' & busyshiftreg(9 dow
nto 1); --count down til busy signal is turned off
counter <= (others => '0');

else
counter <= counter+1;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
Chapter 21: Use putty to transmit and recieve signals (RX/TX)
---------------------------------------------------------------------------------- Company: Gadget Factory
-- Engineer: Jack Gassett
--- Create Date:
22:31:30 11/27/2010
-- Design Name:
UART Example
-- Module Name:
UARTExample - Behavioral
-- Project Name:
CH21
-- Target Devices: Papilio One 500K
-- Tool versions:
-- Description: Example code for implementing the Xilinx UART example on the Pap
ilio One. Edited to send typed letters to LED and send SWITCHES to Putty.
-http://www.xilinx.com/support/documentation/application_notes/x
app223.pdf
-- Dependencies:
-Requires the latest Picoblaze so
urce code. Xilinx EULA does not allow the redistribution of Source code so the s
ource modules must be downloaded seperately.
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity UARTExample is
Port ( rx : in STD_LOGIC;
tx : out STD_LOGIC;
JOY_SELECT: in STD_LOGIC;
SWITCH: in STD_LOGIC_VECTOR(7 downto 0);
LED: out STD_LOGIC_VECTOR(7 downto 0);
extclk : in STD_LOGIC

);
end UARTExample;

architecture Behavioral of UARTExample is

component uart_tx is
port (
data_in :
write_buffer
reset_buffer
en_16_x_baud
serial_out
buffer_full
buffer_half_full
clk
end component;

in std_logic_vector(7 downto 0);

: in std_logic;
: in std_logic;
: in std_logic;
: out std_logic;
: out std_logic;
: out std_logic;
: in std_logic);

component uart_rx is
port (
serial_in : in STD_LOGIC;
read_buffer : in STD_LOGIC;
reset_buffer : in STD_LOGIC;
en_16_x_baud : in STD_LOGIC;
clk : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (7 downto 0);
buffer_data_present : out STD_LOGIC;
buffer_half_full : out STD_LOGIC;
buffer_full : out STD_LOGIC);
end component;
COMPONENT dcm32to96
PORT(
CLKIN_IN : IN std_logic;
CLKFX_OUT : OUT std_logic;
CLKIN_IBUFG_OUT : OUT std_logic;
CLK0_OUT : OUT std_logic
);
END COMPONENT;
signal dout : STD_LOGIC_VECTOR (7 downto 0);
signal data_present, en_16_x_baud, clk, clk32 : STD_LOGIC;
signal baud_count : integer range 0 to 5 :=0;
begin
LED <= dout;
baud_timer: process(clk)
begin
if clk'event and clk='1' then
if baud_count=1 then
baud_count <= 0;
en_16_x_baud <= '1';
else
baud_count <= baud_count + 1;
en_16_x_baud <= '0';
end if;
end if;
end process baud_timer;

Inst_dcm32to96: dcm32to96 PORT MAP(

CLKIN_IN => extclk,
CLKFX_OUT => clk,
CLKIN_IBUFG_OUT => open,
CLK0_OUT => open
);
INST_UART_TX : uart_tx
port map (
data_in => SWITCH(7 downto 0),
write_buffer => NOT(JOY_SELECT),
reset_buffer => '0',
en_16_x_baud => en_16_x_baud,
clk => clk,
serial_out => tx,
buffer_half_full => open,
buffer_full => open
);
INST_UART_RX : uart_rx
port map (
serial_in => rx,
read_buffer => '1',
reset_buffer => '0',
en_16_x_baud => en_16_x_baud,
clk => clk,
data_out => dout,
buffer_data_present => data_present,
buffer_half_full => open,
buffer_full => open
);
end Behavioral;

Final Project: Display a circle on the VGA monitor (Uses VGA_Palette mostsimple
design).
---------------------------------------------------------------------------------- Company: Howard Community College
-- Engineer: Renita Mwangachuchu
--- Create Date:
19:11:09 12/08/2015
-- Design Name:
CircleProject
-- Module Name:
CircleProject - Behavioral
-- Project Name: CircleProject
-- Target Devices: Papilio One 500K
-- Tool versions:
-- Description: Make a circle by manipulating given VGA project files.
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--

--------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CircleProject is
port(
ext_clock: in std_logic;
red: out std_logic;
green: out std_logic;
blue: out std_logic;
hsync: out std_logic;
vsync: out std_logic;
-c: out std_logic
);
end CircleProject;
architecture Behavioral of CircleProject is
component dcm_32_to_25
port(
clkin_in: in std_logic;
clkfx_out: out std_logic;
clkin_ibufg_out: out std_logic;
clk0_out: out std_logic
);
end component;
constant PIXEL_COUNT: integer := 800;
constant LINE_COUNT: integer := 525;
signal pixel_counter: unsigned(9 downto 0) := (others => '0');
signal line_counter: unsigned(9 downto 0) := (others => '0');
signal clock: std_logic;
begin
vga_clock: dcm_32_to_25
port map(
clkin_in => ext_clock,
clkfx_out => clock,
clkin_ibufg_out => open,
clk0_out => open
);
update_pixel_counter: process(clock)
begin
if clock'event and clock = '1' then
if pixel_counter = PIXEL_COUNT - 1 then
pixel_counter <= (others => '0');
else
pixel_counter <= pixel_counter + 1;
end if;
end if;
end process;

update_line_counter: process(clock)
begin
if clock'event and clock = '1' then
if line_counter = LINE_COUNT - 1 then
line_counter <= (others => '0');
elsif pixel_counter = PIXEL_COUNT - 1 then
line_counter <= line_counter + 1;
end if;
end if;
end process;
update_hsync: process(clock)
begin
if clock'event and clock
if pixel_counter
hsync <=
else
hsync <=
end if;
end if;
end process;

= '1' then
<= 95 then
'0';
'1';

update_vsync: process(clock)
begin
if clock'event and clock = '1' then
if line_counter <= 1 then
vsync <= '0';
else
vsync <= '1';
end if;
end if;
end process;
update_pixel: process(clock)
begin
if rising_edge(clock) then
if pixel_counter >144 and pixel_counter <PIXEL_COUNT-16 and line_cou
nter < LINE_COUNT-35 and line_counter > 30 then
blue <= '1';
green <= '1';
red <= '1';
if (480*pixel_counter-pixel_cou
nter*pixel_counter+640*line_counter-line_counter*line_counter )> 157696 then
blue <= '1';
green <= '0';
red <= '1';
end if;
else
red <= '0';
green <= '0';
blue <= '0';
end if;
end if;
end process;
process(clock)
begin
c <= clock;
end process;

end Behavioral;