E TMD T SY OSEO, SBI uty Om Ere anneMCS'-80/85 FAMILY USER’S MANUAL January 1983Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this dooument nor does it make @ commitment to update the information contained herein. ‘The following are trademarks of Intel Corporation and may only be used to identify Intel Products: inteligent identifier, intgligent Programming™, Intellink, IOSP, IPDS, iRMS, iSBC, ISBX, ISXM, Library Manager, MCS, Megachassis ‘Micromainframe, MULTIBUS, Muttichannel™ Plug-A-Bubbie, MULTIMODULE, PROMPT, Promware, FMX’80, RUPI, System 2000, and UPI, and the combination of ICE, ICS, AMX, ISBC, MCS, or UPI and a numerical suffix. MDS is an ordering code only and is not used as a product name or trademark. MOS® is a registered trademark of Mohawk Data Sciences Corporation. * MULTIBUS is a patented Intel bus. ‘Additional copies of this manual or other intel literature may be obtained from: Intel Corporation Literature Department 3085 Bowers Avenue Santa Clara, CA 95051Table of Contents CHAPTER 1 Part 1: Introduction to the Functions of a Computer .........c0scscceeeeseseeeee " Part 2. Introduction to MCS*-85 .... 16 CHAPTER 2 Functional Description .. a eeeeeeteteteeseseteeeeaeee od CHAPTER 3 System Operation and Interfacing ..... peeeeeierreliad| CHAPTER 4 The 8080 Central Processor Unit ee vee Md CHAPTER 5 The Instruction Set... i: : : 2 St Instruction Set Index 519 “CHAPTER 6 Device Specifications 8080A/8080A-1/8080A-2 8-Bit N-Channel Microprocessor ..........+. ve 61 ‘8085 AH/8085 AH-2/8085AH-1 8-Bit HMOS Microprocessors ee se 810 80854/8085A-2 Single Chip 8-Bit N-Channel Microprocessors... 1... 2 6-26 ‘APPENDIX ‘Applications of MCS*-85 .... eee eee AM WORKSHOPS “For complete data sheets on all microprocessor and peripheral products, refer to the Micro- processor and Peripherals Handbook. See inside front cover to order.DO IntroductionCHAPTER 1 PART 1: INTRODUCTION TO THE FUNCTIONS OF A COMPUTER ‘This chapter introduces certain basic computer con cepts, It provides background information and definitions which will be useful in later chapters of this manual. Those iready familiar with computers may skip this mater their option, ATYPICAL COMPUTER SYSTEM ‘A typical digital computer consists of {a} A central processor unit (CPU) b) Amemory 6} Inputfourput (1/0) ports ‘The memory serves as a place to store Instructions, the coded pieces of information that direct the activities of ‘the CPU, and Data, the coded pieces of information that are processed by the CPU. A group of logically related instruc tions stored in memory is eferred to as a Program, The CPU. reads" each instruction from memory in a logically deve: mined sequence, and uses it to initiate processing actions. If the program sequence is coherent and logical, processing ‘the program will produce intelligible and useful results “The memory is also used to store the data to be manip: Uulated, as well as the instructions that direct that manipu: lation, The program must be organized such that the CPU oes not read a non-instruction word when it expects to see an instruction, The CPU can rapidly access any data stored in memory; but often the memory is not large enough data bank required for a particular appli cation, The problem can be resolved by providing the com ‘puter with one or more Input Ports. The CPU can address ‘these ports and input the data contained there, The addition Of input ports enables the computer to receive information from external equipment (such as 2 paper tape reader oF ‘loppy disk) at high rates of speed and in large volumes. 10 store the ent ‘A computer also requires one or more Output Ports ‘that permit the CPU to communicate the result of its pro cessing 10 the outside world, The output may go to 2 dis- play, for use by a human operator, to a peripheral device that’ produces “hard-copy,” such 85 8 lineprinter, to a peripheral storage device, such as a floppy disk unit, or the ‘output may constitute process control signals that direct the operations of another system, such asan automated assembly line. Like input ports, output ports ere addressable. The input and output ports together permit the processor to ‘communicate with the outside world. ‘The CPU unifies the system, It controls the functions ‘performed by the other components. The CPU must be able 10 fetch instructions from memory, decode their binary ‘contents and execute them. It must also be able to reference memory and 1/0 ports as necessary in the execution of in structions, In addition, the CPU should be able to recognize and respond to certain external control signals, such as INTERRUPT and WAIT requests, The functional units within a CPU that enable it to perform these functions are scribed below. ‘THE ARCHITECTURE OF A CPU ‘A typical central processor unit (CPU) consists of the following interconnected functional units: © Registers ‘© Arithmetic/Logic Unit (ALU) # Control Circuitry Registers are temporary storage units within the CPU. ‘Some registers, such as the program counter and instruction register, have dedicated uses, Other registers, such as the ac: ‘curmulator, are for more general purpose use. Accumulator: ‘The accumulator usually stores one of the operands to be manipulated by the ALU. A typical instruction might direct the ALU to add the contents of some other register to the contents of the accumulator and store the result in the accumulator itself. In general, the accumulator is both a source (operand) and a destination (result) register, Often a CPU will include @ number of additional general purpose registers that can be used to store operands fr intermediate data, The availablity of general purposeregisters eliminates the need to “shuffle” intermediate re sults back and forth between memory and the accumulator, ‘thus improving processing speed and efficiency. Program Counter (Jumps, Subroutines and the Stack): The instructions that make up a program are stored. In the system's memory. The central processor references the contents of memory, in order to determine what action is appropriate, This means that the processor must know Which location contains the next instruction. Each of the locations in memory is numbered, to dis: tinguish it from all other locations in memory, The number hich identifies a memory location is called its Address. ‘The processor maintains 8 counter which contains the address of the next program instruction. This register is called the Program Counter. The processor updates the pro- {gram counter by adding “1" to the counter each time it {etchesan instruction, so that the program counter is always current (pointing to the next instruction) ‘The programmer therefore stores his instructions in ‘numerically adjacent addresses, so that the lower addresses contain the first instructions to be executed and the higher addresses contain later instructions, The only time the pro- grammer may violate this sequential rule is when an instruc tion in one section of memory is a Jump instruction to another section of memory, ‘jump instruction contains the address ofthe instruc- tion which is to follow it, The next instruction may be stored in any memory location, as long as the programmed jump specifies the correct address. During the execution of ‘jump instruction, the processor replaces the contents of its program counter with the address embodied in the Jump, ‘Thus, the logical continuity of the program is maintained. ‘A special kind of program jump occurs when the stored program “Calls” a subroutine, inthis kind of jump, the pro ‘cessor is required to “remember” the contents of the pro ‘ram counter at the time that the jump occurs, This enables the processor to resume execution of the main program when it s finished with the last instruction of the subroutine, A Subroutine is a program within a program, Usually it is @ general-purpose set of instruetions that must be exe cuted repestedly in the course of a main program, Routines which calculate the square, the sine, or the logarithm of @ program variable are good examples of functions often ‘written as subroutines. Other examples might be programs designed for inputting or outputting data to @ particular peripheral device, ‘The processor has a special way of handling sub routines, in order to insure an orderly return to the main program. When the processor receives a Call instruction, it increments the Program Counter and stores the counter’s contents in a reserved memory area known as the Stack. ‘The Stack thus saves the address of the instruction to be ‘executed after the subroutine is completed. Then the pro: 12 cessor loads the address specified in the Call into its Pro: ‘gram Counter. The next instruction fetched will therefore be the first step of the subroutine, ‘The last instruction in any subroutine isa Return, Such ‘an instruction need specity no address. When the processor fetches a Return instruction, it simply replaces the current contents of the Program Counter with the address on the top of the stack. This causes the processor to resume execu tion of the calling program at the point immediately follow. ing the original Call Instruction, Subroutines are often Nested; that is, one subroutine will sometimes call @ second subroutine, The second may calla third, and $0 on. This is perfectly acceptable, as long 15 the processor has enough capacity to store the necessery return addeesses, and the logical provision for doing «0. In fother words, the maximum depth of nesting is determined by the depth of the stack itself, If the stack has space for storing three return addresses, then three levels of subrou tines may be accommodated Processors have different ways of maintaining stacks. Some have facilities forthe storage of return addresses built into the processor itself. Other processors use a reserved {area of external memory as the stack and simply maintain a Pointer register which contains the address of the most recent stack entry, The external stack allows virtually un limited subcoutine nesting In addition, ifthe processor pro- vides instructions that cause the contents of the accumulator and other general purpose registers to be “pushed” onto the stack or “popped” off the stack via the address stored in the stack pointer, multilevel interrupt processing (described later in this chapter) is possible, The status of the processor (ie, the contents of all the registers) can be saved in the stack when an interrupt is accepted and then restored after the interrupt has been serviced. This ability to save the pro- ceessor's status at any given time is possible even if an inter- rupt service routine, itself, is interrupted, Instruction Register and Decoder: Every computer has @ Word Length that is characteris. tic of that machine, A computer's word length is usually determined by the size of its internal storage elements and interconnecting paths (referred to as Bustes); for example, 4 computer whose registers and busses can store and trans {er 8 bits of information has characteristic word length of Bbits and is referred to as an B-bit parallel processor. An eight-bit parallel processor gonerally finds it most efficient to deal with eight-bit binary fields, and the memary asso- ciated with such a processor is therefore organized to store eight bits in each addressable memory location. Data and instructions are stored in memory as eight bit binary num bers, or as numbers that are integral multiples of eight bits: 16 bits, 24 bits, and so on, This characteristic eightbit Field is often referred to as a Byte. Each operation that the processor can perform is identified by a unique byte of data known as an InstructionCode or Operation Code, An eight-bit word used as an in struction code can distinguish between 256 alternative actions, more than adequate for most processors. ‘The processor fetches an instruction in two distinet ‘operations. First, the processor transmits the address in its Program Counter to the memory. Then the memory returns the addressed byte to the processor. The CPU stores this instruction byte in a register known as the Insttuetion Register, and uses it to direct activities during the remainder of the instruction execution, ‘The mechanism by which the processor translates an instruction code into specific processing actions requites more elaboration than we can here afford, The concept, however, should be intuitively clear to any logie designer. The eight bits stored in the instruction register can be de ‘coded and used to selectively activate one of a number of ‘output lines, in this case up to 256 lines. Each line repre sents a set of activities associated with execution of a pat- ticular instruction code. The enabled line can be combined With selected timing pulses, to develop electrical signals that ‘can then be used to initiate specific actions. This transla tion of code into action is performed by the Instruction Decoder and by the attociated control circuitry. ‘An eight-bit instruction code is often sufficient to specify a particular processing action. There are times, how- ever, when execution of the instruction requires more infor: ‘mation then eight bits ean convey. One example of this is when the instruction refer fences a memory location, The basic instruction code iden- tifies the operation to be performed, but cannot specify the object address as wel, In a case lke this, a two- or three byte instruction must be used. Successive instruction bytes fare stored in sequentially adjacent memory locetions, anc the processor performs two or three fetches in succession to ‘obtain the full instruction, The first byte retrieved from memory is placed in the processor's instruction register, and subsequent bytes are placed in temporary storage; the pro ‘cessor then proceeds with the execution phase. Such an instruction is referred to as Variable Length, Address Register(s): ‘A CPU may use a register or register-pair to hold the address of a memory location that is to be accessed for data. If the address register is Programmable, (ie, if there are instructions that allow the programmer to alter the Contents of the register) the program can “"build” an ad- dress in the address register prior to executing @ Memory Reference instruction (ie, an instruction that reads data from memory, writes data to memory or operates on data sored in memory) Arithmetic/L ogie Unit (ALU All processors contain an arithmetic/lagic unit, which is often referred to simply as the ALU. The ALU, as its name implies, is that portion of the CPU hardware which performs the arithmetic and logical operations on the binary ata, ‘The ALU must contain an Adder which is capable of combining the contents of two registers in accordance with the logie of binary arithmetic. This provision permits the processor to perform arithmetic manipulations on the data it obtains from memory and from its other inputs Using only the basic adder @ capable programmer can write routines which will subtract, multiply and divide, giv ing the machine complete arithmetic capabilites. In practice, however, most ALUs provide other built-in functions, in- cluding hardware subtraction, boolean logic operations, and shift capabilities. ‘The ALU contains Flag Bits which specify certain conditions that arige in the course of arithmetic and logical ‘manipulations. Flags typically include Carry, Zero, Sign, and Parity. It i possible to program jumps which are condi tionally dependent on the status of one oF mare flags, Thus, for example, the program may be designed to jump to a special routine if the carry bit is set following an addition instruction, Control Circuitry The control circuitry is the primary functional unit within a CPU. Using clock inputs, the control circuitry ‘maintains the proper sequence of events required for any Processing task. After an instruction is fetched and decoded, the control circuitry issues the appropriate signals (to units both internal and external to the CPU) for initisting the proper processing action. Often the control circuitry will be ‘capable of responding to external signals, such as an inter rupt or wait request. An Interrupt request will cause the control circuitry to temporarily interrupt main program execution, jump t0 a special routine to service the interrupt: ing device, then automatically return to the main program. [A Wait request is often issued by 2 memory or 1/0 element that operates slower than the CPU, The control circuitry will ile the CPU until the memory or 1/0 port is ready with the data COMPUTER OPERATIONS There are certain operations that are basic to almost any computer. A sound understanding of these basic opers- tions is a necessary prerequisite to examining the specific ‘operations of a particular computer. Timing: ‘The activities ofthe central processor are cyclical. The processor fetches an instruction, performs the operations required, fetches the next instruction, and so on. This orderly sequence of events requires precise timing, and the (CPU therefore requires a free running oscillator clock which furnishes the reference for all processor actions, The com bined fetch and execution of a single instruction is referred to a8 an Instruction Cycle. The portion of a cycle identifiedwith a clearly defined activity is called a State. And the inter val between pulses of the timing oscillator is referred to as Clock Period. As 2 general rule, one or more clock periods are necessary for the completion of a state, and there are several states in a cycle. Instruction Fetch: The first state(s) of any instruction eycle will be dedicated te fetching the next instruction, The CPU issues 2 read signal and the contents of the program counter are sent {to memory, which responds by returning the next instruc: tion word. The first byte of the instruction is placad in the instruction cogister, 1 the instruction consists of more than fone byte, additional states are required to fetch each byte of the instruction, When the entire instruction is present in the CPU, the program counter is incremented (in prepsra tion for the next instruction feteh) and the instruction it decoded. The operation specified in the instruction will be executed in the remaining states of the instruction cycle, The instruction may call for a memory read or write, an input or output and/or an internal CPU operation, such as arogister-to-egister transfer or an add registers operation, Memory Read: ‘An instruction fetch is merely a special memory read ‘operation that brings the instruction to the CPU's instruc: tion register. The instruction fetched may then cal for data toberead from memory into the CPU. The CPU again issues ‘read signal and sends the proper memory address; memory responds by returning the requested word. The data re- cvived is placed in the accumulator or one of the other ger eral purpose registers (not the instruction register. ‘Memory Write: ‘A memory write operation is similar to 2 read except for the direction of data flow. The CPU issues a write signal, ends the proper memory address then sends the data ‘word to be written into the addressed memory location, Wait (memory synchronization): As previously stated, the activities of the processor ‘are timed by a master clock oscillator. The clock period ‘determines the timing of all processing activity. ‘The speed of the processing cycle, however, i limited by the memory’s Access Time. Once the processor has sent a ‘ead address to memory, itcannot proceed until the memory hhas had time to respond, Most memories are capable of responding much faster than the processing cycle eequires. A few, however, cannot supply the addressed byte within the minimum time established by the processor's clock ‘Therefore 2 processor should contain a synchroniza: tion provision, whieh permits the memory to request a Wait state, When the memory receives a read or write enable sig nal, it placesa request signal on the processor’s READY ine, ‘causing the CPU to idle temporarily. After the memory has had time to respond, it frees the processor's READY li ‘and the instruction eycle proceeds Input/Output: Input and Output operations are similar to memory read and write operations with the exception that a peri pheral 1/0 device is addressed instead of a memory location, ‘The CPU issues the appropriate input or output control signal, sonds the proper device address and either receives the data being input or sends the data to be output. Data cen be input/output in either paralle! or serial form. All data within a digital computer is represented in binary coded form. A binary data word consists of @ group Of bits; each bit is either a one or a zer0, Parallel I/O con sists of transferring all bits in the word at the same time, fone bit per line, Serial I/O consists of transterring one bit ‘at a time on a single line. Naturally serial 1/0 is much slower, but it cequires considerably less hardware than does paral 1/0, Interrupts: Interrupt provisions are included on many central processors, a8 8 means of improving the processor's effi ciency. Consider the case of a computer that is processing a large volume of data, portions of which are to be output to 9 printer. The CPU ean output a byte of data within single machine cycle but it may take the printer the equiva lent of many machine eycles to actually print the character specified by the data byte, The CPU could then remsin idle ‘waiting until the printer can accept the next data byte. If aninterrupt capability is implemented on the computer, the CPU can output a data byte then return to data processing. When the printer is ready to accept the next data byte, it ‘ean request an interrupt, When the CPU acknowledges the interrupt, it suspends main program execution and auto matically branches to @ routine that will output the next data byte. After the byte is output, the CPU continues with main program execution. Note that this i, in principle, Quite similar to a subroutine call, except that the jump is initiated externally rather than by the program. More complex interrupt structures are possible, in Which several interrupting devices share the same processor but have different priority levels. Interruptive processing is ‘an important feature that enables maximum untilization of ‘8 processor's capacity for high system thoughout. Hold: ‘Another important feature that improves the through put of a processor is the Hold, The hold provision enables Direct Memory Access (DMA) operations. Inordinary input and output operations, the processor itselt supervises the entire data transfer. Information to be placed in memory is transferred from the input device to the processor, and then from the processor to the designated memory location. In similar fashion, information that goesfrom memory to output devices goes by way of the Processor. Some peripheral devices, however, are capable of transferring information to and from memory much faster than the processor itself can accomplish the transfer. If any appreciable quantity of data must be transferred to or from such @ device, then system throughput will be increased by having the device accomplish the transfer directly. The pro: ‘cessor must temporarily suspend its operation during such a transfer, to prevent conflicts that would arise if processor and peripheral device attempted to access memory simul- taneously. It is for this reason that 2 hold provision is ‘cluded on some processors, fea aca] =i 1sPART THE MCS-85™ MICROCOMPUTER SYSTEM The basic philosophy behind the MCS-85 microcomputer system is one of logical, evolu- tionary advance in technology without the waste of discarding existing investments in hardware and software. The MCS-85 provides. the existing 8080 user with an increase in per- formance, a decrease in the component count, operation from a single 5-Volt power supply, and still preserves 100% of his existing software in- vestment. For the new microcomputer user, the MCS-85 represents the refinement of the most popular microcomputer in the industry, the intel 8080, along with a wealth of supporting soft- ware, documentation and peripheral com- ponents to speed the cycle from prototype to production, The same development tools that Intel has produced to support the 8080 microcomputer system can be used for the MCS-85, and additional add-on features are available to optimize system development for MCS. This section of the MCS-80/85 User’s Manual will briefly detail the basic differences between the MCS-85 and MCS-80 families. It will illus- trate both the hardware and software compati- bilities and also reveal some of the engineering trade-offs that were met during the design of the MCS-85. More detailed discussion of the MCS-85 bus operation and component specifications are available in Chapters: 2, 3, 4, and 5. The information provided in Chapter 1 will be helpful in understanding the basic con- cepts and philosophies behind the MCS-85. EVOLUTION In December 1971, Intel introduced the first general purpose, B-bit microprocessor, the 8008. It was implemented in P-channel MOS technology and was packaged in a single 18 pin, dual in-line package (DIP). The 8008 used standard semiconductor ROM and RAM and, for the most part, TTL components for I/O and general interface. It immediately found applica- tions in byte-oriented end products such as ter- minals and computer peripherals where its in- struction execution (20 micro-seconds), general : INTRODUCTION TO MCS-85™ _ T i : am i | | : co a sent so i iINTRODUCTION TO MCS-85™ purpose organization and instruction set matched the requirements of these products. Recognizing that hardware was but a small part in the overall system picture, Intel developed both hardware and software tools for the design engineer so that the transition from pro- totype to production would be as simple and fast as possible. The commitment of providing a total systems approach with the 8008 micro- computer system was actually the basis for the sophisticated, comprehensive development tools that Intel has available today. THE 8080A MICROPROCESSOR With the advent of high-production N-channel RAM memories and 40 pin DIP packaging, Intel designed the 8080A microprocessor. it was designed to be software compatible with the 8008 so that the existing users of the 8008 could preserve their investment in software and at the same time provide dramatically increased per- formance (2 micro-second instruction execu- tion), while reducing the amount of components. necessary to implement a system. Additions were made to the basic instruction set to take advantage of this increased performance and large system-type features were included on- chip such as DMA, 16-bit addressing and exter- nal stack memory 50 that the total spectrum of application could be significantly increased. The 8080 was first sampled in December 1973. Since that time it has become the standard of the industry and is accepted as the primary building block for more microcomputer based applications than all other microcomputer sys- tems combined. ATOTAL SYSTEMS COMMITMENT The Intel® 8080 Microcomputer System en- compasses a total systems commitment to the user to fully support his needs both in develop- ing prototype systems and reliable, high volume production. From complex MOS/LSI peripheral components to resident high level systems language (PUM) the Intel® 8080 Microcom- puter System provides the most comprehen- sive, effective solution to today’s system pro- blems.INTRODUCTION TO MCS-85™ SOFTWARE COMPATIBILITY As with any computer system the cost of soft ware development far outweighs that of hard- re. A microcomputer-based system is tradi- tionally a very cost-sensitive application and the development of software is one of the key areas where success oF failure of the cost ob- jectives is vital. The 8085A CPU is 100% software compatible with the Intel® 8080A CPU. The compatibility is at the object or “machine code” level so that ex- isting programs written for 8080A execution will run on the 8085A as is. The value of this becomes even more evident to the user who has, mask programmed ROMs and wishes to update his system without the need for new masks. PROGRAMMER TRAINING A cost whi often forgotten is that of pro- grammer training. A new, or modified instruc- tion set, would require programmers to relearn another set of mnemonics and greatly affect the productivity during development. The 100% ‘compatibility of the 8085A CPU assures that no retraining effort will be required. ace 18 For the new microcomputer user, the software ‘compatibility between the 8085A and the 8080A means that all of the software development tools that are available for the 8080A and all software libraries for 8080A will operate with the new design and thus save immeasurable cost in development and debug. ‘The 8085A CPU does however add two instruc- tions to initialize and maintain hardware features of the 8085A. Two of the unused op- of the 8080A instruction set were nated for the addition so that 100% com- patibility could be maintained. HARDWARE COMPATIBILITY The integration of auxiliary 8080A functions, such as clock generation, system control and interrupt prioritization, dramatically reduces the amount of components necessary for most systems. In addition, the MCS-85 operates off a single +5 Volt power supply to further simplify hardware development and debug. A close ex- amination of the ACIDC specifications of the MCS‘85 systems components shows that each is specified to supply a minimum of 400uA of source current and a full TTL load of sink cur- rent so that a very substantial system can be constructed without the need for extra TTL buf- fers or drivers. Input and output voltage levels are also specified so that a minimum of 350mV_ noise margin is provided for reliable, high- Performance operation. - PC BOARD CONSIDERATIONS ‘The 8085A CPU and the 8080A are not pin- compatible due to the reduction in power sup- plies and the addition of integrated auxiliary features. However, the pinouts of the MCS-85 system components were carefully assigned to minimize PC board area and thus yield a smooth, efficient layout. For new designs this incompatibility of pinouts presents no pro- blems and for upgrades of existing designs the reduction of components and board area will far offset the incompatibility.INTRODUCTION TO MCS-85™ MCS-85™ SPECIAL PERIPHERAL COMPONENTS The MCS-85 was designed to minimize the amount of components required for most systems. Intel designed several new peripheral components that combine memory, vO and timer functions to fulfill this requirement. These new peripheral devices directly interface to the multiplexed MCS-85 bus structure and provide new levels in system integration for today’s designer. 785A EPROM and 110 Socket compatible with 8355 2K bytes EPROM ‘Two Bit ports (direction programmable) Single +5 Volt supply read operation UY. Erasable 40 pin DIP package raenn— La. on rwereor 0 2 6155 ~TE, 8156=CE {8188/8156 RAM, UO and Timer 256 bytes RAM Two Sit ports ‘One 6.it port (programmable) (One 14-bit programmable interval timer Single +5 Volt supply operation 40 pin OIP plastic oF cersip package 18385 ROM and ti 2K bytes ROM Two Bit ports (direction programmable) Single +8 Volt supply operation 40)pin DIP plastic or cerdip package ‘One of the most important advances made with the MCS-85 is the socket-compatibility of the 8355 and 8755A components. This allows the systems designer to develop and debug in erasable PROM and then, when satisfied, switch over to mask-programmed ROM 8355 with no performance degradation or board relayout. It also allows qi tion for market impact without going to a com- promise solution. ‘SYSTEM EXPANSION Each of these peripheral components has features that allow a small to medium system to be constructed without the addition of buf- fers and decoders to maintain the lowest pos: ble component count. 19INTRODUCTION TO MCS-85™ ne 108 Figure 1-1. MCS-85"™ Basic SystemINTRODUCTION TO MCS-85™ INTERFACING TO MCS-8o/es™ PROGRAMMABLE PERIPHERAL COMPONENTS ‘The MCS-85 shares with the MCS-80 a wide range of peripheral components that solve system problems and provide the designer with a great deal of flexibility in his /O, Interrupt and DMA structures. The MCS-85 is ‘directly com- patible with these peripherals, and, with the ex- ception of the 8257-5 DMA controller, needs no additional circuitry for their interface in a minimum system. The 8257-5 DMA controller uses an 8212 latch and some gating to support the multiplexed bus of MCS-85. PROGRAMMABLE PERIPHERALS. The list of programmable peripherals for use with the 8085A includes: 8251A Programmable Communications. Interface 8253.5 Programmable Interval Timer 8255A‘5 Programmable Peripheral Inter- face 8257-5 Programmable DMA Controller 8269-5 Programmable Interrupt Con- troller 8271 Diskette Controller 8273 Synchronous Data Link Con- troller 8275 CRT Controller 8278 Keyboard/Display Controller 8279 Keyboard/Display Controller ‘The MCS-80/85 peripheral compatibility assures the designer that all new peripheral com- ponents from Intel will interface to the MCS-85 bus structure to further expand the application spectrum of MCS-85. WK. = ‘0054 mastaINTRODUCTION TO MCS-85™ INTERFACING TO STANDARD MEMORY The MCS-85 was designed to support the full range of system configurations from small 3 chip applications to large memory and 0 ap- plications. The 8085A CPU issues advanced READMRITE status signals (S0, S1, and 1O/M) so that, in the case of large systems, these signals could be used to simplify bus arbitra- tion logic and dynamic RAM refresh circuitry. In large, memory-intensive systems, standard memory’ devices may provide a more cost- effective solution than do the special 8155 and 8355 devices, especially where few I/O lines are required. DEMULTIPLEXING THE BUS In order to interface standard memory com- Ponents such as Intel® 2114, 2142, 2716, 2316E, 2104A and 2117 the MCS-85 bus must be “demultiplexed”. This is accomplished by con- necting an Intel® 8212 latch to the data bus and strobing the latch with the ALE signal from the ‘8085A CPU. The ALE signal is issued to indicate that the multiplexed bus contains the lower Bits of the address. The 8212 latches this in- formation so that a full 16-bit address is available to interface standard memory com- ponents. USE OF 8212 Large, memory intensive systems are usually multi-card implementations and require some form of TTL buffering to provide necessary cur- rent and voltage levels. Frequently, 8212s are used for this purpose. The 8212 has the advan- tage of being able to latch and demultiplex the address bus and provide extra address drive capability at the same time. ToINTRODUCTION TO MCS-85™ ‘SYSTEM PERFORMANCE The true benchmark of any microcomputer- based system is the amount of tasks that can bbe performed by the system in a given period of time. Increasing speed of CPU instruction ex- ecution has been the common approach to in- creasing system throughput but this puts a greater strain on the memory access reqi ment and bus operation than is usually prac- tical for most applications. A much more desirable method would be to distribute the task-load to peripheral devices. DISTRIBUTED PROCESSING The concept of distributed task processing is not new to the computer designer, but until recently little if any task distribution was available to the microcomputer user. The use of the new programmable MCS-80/85 peripherals can relieve the central processor of many of the bookkeeping 1/0 and timing tasks that would otherwise have to be handled by system soft- ware. INSTRUCTION CYCLE/ACCESS TIME The basic instruction cycle of the 8085A is 1.3 microseconds, the same speed as the 8080A-1. Aclose look at the MCS-85 bus operation shows that the access requirement for this speed is only 575 nanoseconds. The MCS-80 access re- quirements for this speed would be under 300 nanoseconds. This illustrates the efficiency and improved timing margins of the MCS-85 bus structure. The new 8085A-2, a high-speed selected version of the 8085A with a .8 micro- second instruction cycle, provides a 60% per- formance improvement over the standard 8085A. CONCLUSIONS: THROUGHPUTICOST When a total system throughputicost analysis is taken, the MCS-85 system with its advanced processor will yield the most cost-effective, rellable and producible system. saFunctional Description 9CHAPTER 2 8085A FUNCTIONAL DESCRIPTION 2.1. WHAT THE 8085A IS The 8085A is an B-bit general-purpose micro- processor that is very cost-effective in small ‘systems because of its extraordinarily low hard- ware overhead requirements. At the same time it Is capable of accessing up to 64K bytes of memory and has status lines for controlling large systems. 2.2 WHAT'S IN THE 8085A In the 8085A microprocessor are contained the functions of clock generation, system bus con- trol, and interrupt priority selection, in addition to execution of the instruction set. (See Figure 2-1) The 8085A transfers data on an Bit, bi- directional 3state bus (ADp7) which is time- multiplexed so as to also transmit the eight lower-order address bits. An additional eight lines (Ag.15) expand the MCS-85 system memory addressing capability to 16 bits, thereby allow- ing 64K bytes of memory to be accessed direct- ly by the CPU. The 8085A CPU (central process- ing unit) generates control signals that can be used to select appropriate external devices and cir tet functions to perform READ and WRITE opera- tions and also to select memory or /O ports. ‘The 8085A can address up to 266 different 1/0 locations. These addresses have the same numerical values (00 through FFH) as the first 256 memory addresses; they are distinguished by means of the IO/M output from the CPU. You may also choose to address /O ports as memory locations (i.e., memory-map the W/O, Section 3.2). 224 Registers ‘The 8085A, like the 8080, is provided with inter- nal B-bit registers and 16-bit registers. The 8085A has eight addressable 8-bit registers. Six of them can be used either as 8-bit registers or as 16bit register pairs. Register pairs are treated as though they were single, 16-bit registers; the high-order byte of a pair is located in the first register and the low-order byte is, located in the second. In addition to the register pairs, the 8085A contains two more 16-bit registers. ty t Ray LT : U ¥ FIGURE 2-1 8085A CPU FUNCTIONAL BLOCK DIAGRAMFUNCTIONAL DESCRIPTION The 8085A's CPU ré follows: ‘* The accumulator (ACC or A Register) is the focus of all of the accumulator in- structions (Table 4-1), which include arithmetic, logic, load and store, and VO instructions. It is an &-bit register only. (However, see Flags, in this list.) * The program counter (PC) always points to the memory location of the next in- struction to be executed. It always con- tains a 16-bit address. © General-purpose registers BC, DE, and HL may be used as six Bit registers or as three 16it registers, interchangeably, depending on the instruction being per- formed. HL functions as a data pointer to reference memory addresses that are either the sources or the destinations in a number of instructions. A smaller number of instructions can use BC or DE for indirect addressing. * The stack pointer (SP) is a special data pointer that always points to the stack top (next available stack address). It is an indivisible 16-bit register. * The flag register contains five one-bit flags, each of which records processor status information and may also control processor operation. (See following paragraph.) isters are distinguished as 22.2 Flags The five flags in the 8085A CPU are shown below: Dr De Ds Dy Ds De Dy Do s|z AC P cy The carry flag (CY) is set and reset by arithmetic operations. Its status can be directly tested by a program. For example, the addition of two ‘one-byte numbers can produce an answer that does not fit into one byte: HEXIDECIMAL AEH +74H 1224 Carry bit sets carry flag to 1 22 An addition operation that results in an ‘overflow out of the high-order bit of the ac- cumulator sets the carry flag. An addition operation that does not result in an overflow clears the carry flag. (See 8080/8085 Assembly Language Programming Manual for further details.) The carry flag also acts as a “borrow” flag for subtract operations. The auxiliary carry flag (AC) indicates overflow out of bit 3 of the accumulator in the same way that the carry flag indicates overtiow out of bit 7. This flag is commonly used in BCD (binary coded decimal) arithmetic. The sign flag is set to the condition of the most significant bit of the accumulator following the execution of arithmetic or logic instructions. These instructions use bit 7 of data to represent the sign of the number contained in the ac- cumulator. This permits the manipulation of numbers in the range from — 128 to +127. The zero flag is set if the result generated by certain instructions is zero. The zero flag is cleared if the result is not zero. A result that has a carry but has a zero answer byte in the ac- cumulator will set both the carry flag and the zero flag. For example, HEXADECIMAL BINARY ATH 10100111 +59H +01011001 100H 100000000, 7100000000, Cary bit — 7 Eight zero bits set zero flag to 1 incrementing or decrementing certain CPU registers with a zero result will also set the zero flag. The parity flag (P) is set to 1 if the parity (number of 1-bits) of the accumulator is even. If dd, it is cleared. 223° Stack ‘The stack pointer maintains the address of the last byte entered into the stack. The stack pointer can be initialized to use any portion of read-write memory as a stack. The stack pointer is decremented each time data is pushed onto the stack and is incremented each time data is Popped off the stack (i.e, the stack grows downward in terms of memory address, and the stack “top” is the lowest numerical address represented in the stack currently in use). Note that the stack pointer is always incremented or decremented by two bytes since all stack operations apply to register pairs.FUNCTIONAL DESCRIPTION 2.2.4 Arithmetic-Logic Unit (ALU) ‘The ALU contains the accumulator and the flag register (described in Sections 2.2.1 and 2.2.2) and some temporary registers that are inac- cessible to the programmer. Arithmetic, logic, and rotate operations are per- formed by the ALU. The results of these oper: tions can be deposited in the accumulator, or they can be transferred to the internal data bus for use elsewhere. 2.2.5 Instruction Register and Decoder During an instruction fetch, the first byte of an instruction (containing the opcode) is trans- ferred from the internal bus to the 8-bit instruc- tion register. (See Figure 2-1.) The contents of the instruction register are, in turn, available to the instruction decoder. The output of the decoder, gated by timing signals, controls the registers, ALU, and data and address buffers. The outputs of the instruction decoder and in- ternal clock generator generate the state and machine cycle timing signals. 2.26 Intemal Clock Generator ‘The 8085A CPU incorporates a complete clock generator on its chip, so it réquires only the ad- dition of a quartz crystal to establish timing for its operation. (It will accept an external clock in- put at its X; input instead, however.) A suitable crystal for the standard 8085A must be parallel- resonant at a fundamental of 6.25 MHz or less, twice the desired internal clock frequency. The 8085A-2 will operate with crystal of up to 10 MHz. The functions of the 8085A internal clock generator are shown in Figure 2-2. A Schmitt trigger is used interchangeably as oscillator or a o r al 2 FIGURE 2-2 8085A CLOCK LOGIC 23 as input conditioner, depending upon whether a crystal or an external source is used. The clock circuitry generates two nonoverlapping internal clock signals, #; and 42 (see Figure 2-2). 6; and #2 control the internal timing of the 8085A and are not directly available on the outside of the chip. The extemal pin CLK is a buffered, in- verted version of ¢;. CLK is half the frequency of the crystal input signal and may be used for clocking other devices in the system. FIGURE 2-3 8085A HARDWARE AND SOFT- WARE RST BRANCH LOCATIONS 2.27 Interrupts ‘The five hardware interrupt inputs provided in the 8085A are of three types. INTR is identical with the 8080A INT line in function; ie., it Is maskable (can be enabled or disabled by El or DI software instructions), and causes the CPU to fetch in an RST instruction, externally placed on the data bus, which vectors a branch to any one of eight fixed memory locations (Restart ad- dresses). (See Figure 2:3) INTR can also be controlled by the 8259 programmable interrupt controller, which generates CALL instructions instead of RSTs, and can thus vector operation of the CPU to a preprogrammed subroutine located anywhere in your system's memory map. The RST 5.5, RST 6.5, and RST 7.5 hard- ware interrupts are different in function in that they are maskable through the use of the SIMFUNCTIONAL DESCRIPTION instruction, which enables or disables these in- terrupts by clearing or setting corresponding mask flags based on data in the accumulator. (See Figure 2-4.) You may read the status of the interrupt mask previously set by peforming a RIM instruction. Its execution loads into the ac- cumulator the following information. (See Figure 2-5.) © Current interrupt mask status for the RST 5.5, 6.5, and 7.5 hardware status. ‘* Current interrupt enable flag status (ex- cept that immediately following TRAP, the IE flag status preceding that inter: tupt is loaded). * RST 5.5, 6.5, and 7.5 interrupts pending. RST 5.5, 65, and 7.5 are also subject to being enabled or disabled by the El and DI instruc: tions, respectively. INTR, RST 5.5, and RST 6.5, are level-sensitive, meaning that ‘these inputs may be acknowledged by the processor when they are held at a high level. RST 7.5 is edge- sensitive, meaning that an internal flip-flop in the 80854 registers the occurrence of an inter- rupt the instant a rising edge appears on the RST 7.5 input line. This input need not be held high; the flip-flop will remain set until it is cleared by one of three possible actions: ‘+ The 8085A responds to the interrupt, and sends an internal reset signal to the RST 755 flip-flop. (See Figure 264) SIM — SET INTERRUPT MASK iercove = 20) ‘CONTENTS OF ACCUMULATOR BEFORE EXECUTING SIM: Y ~] mae] (ia FIGURE 2-4 INTERRUPT MASKS SET USING SIM INSTRUCTION FIM — READ INTERRUPT MASK “ore« ‘CONTENTS OF ACCUMULATOR AFTER EXECUTING RIM: FIGURE 2-5 RIM — READ INTERRUPT MASK RST ‘SET RESET (INTERNAL) INTERRUPT REQUEST ONTERNAL) FIQURE26ARST75 FLIP FLOP FIGURE2-68 TRAP INTERRUPT INPUTS FIGURE 26 RST 7.5 AND TRAP INTERRUPT INPUTS PayFUNCTIONAL DESCRIPTION * The 8085A, before responding to the RST 7.5 interrupt, receives a RESET IN signal from an external source; this also ac- tivates the internal reset. ‘* The 8085A executes a SIM instruction, with accumulator bit 4 previously set to. 1, (See Figure 2-4.) third type of hardware interrupt is TRAP. input is not subject to any mask or inter- rupt enable/disable instruction. The receipt of a positive-going edge on the TRAP input triggers. the processor's hardware interrupt sequence, but the pulse must be held high until acknowledged internally (see Figure 2-68). The sampling of all interrupts occurs on the descending edge of CLK, one cycle before the end of the instruction in which the interrupt in- Put is activated. To be recognized, a valid inter- Tupt must occur at least 160 ns before sampling time in the 8085A, or 150 ns in the 8085A-2. This means that to guarantee being recognized, RST 55 and 6.5 and TRAP need to be held on for at least 17 clock states plus 160 ns (150 for 8084-2), assuming that the interrupt might ar- rive just barely too late to be acknowledged dur- ing a particular instruction, and that the follow- ing instruction might be an 18-state CALL. This timing assumes no WAIT or HOLD cycles are used. The way interrupt masks are set and read described in Chapter 4 under the RIM (read in- The a terrupt mask) and SIM (set interrupt mask) in- struction listings. Interrupt functions and their priorities are shown in the table that follows. sume rrony sl ae wm ry when inter. Trager rupt occurs a Rage ct oo ee aus merce «ah a oe Ea (1) In the case of TRAP and RST 5.5-7.5, the contents of the Program Counter’ are pushed onto the stack before the branch occurs. (@) Depends on the instruction that is pro- vided to the 8085A by the 8259 or other circuitry when the interrupt is acknowl: edged. 2.28 Serial Input and Output The SID and SOD pins help to minimize chip count in small systems by providing for easy in- terface to a serial port using software for timing and for coding and decoding of the data. Each time a RIM instruction is executed, the status of the SID pin is read into bit 7 of the accumulator. RIM is thus a dual-purpose instruction. (See Chapter 4.) In similar fashion, SIM is used to latch bit 7 of the accumulator out to the SOD output via an internal flip-flop, providing that bit 6 of the accumulator is set to 1. (See Figure 2-7.) Section 2.3.8 describes SID and SOD timing. SID can also be used as a general purpose TEST input and SOD can serve as a one-bit con- trol output. 28 [EFFECT OF RIM INSTRUCTION EFFECT OF Si INSTRUCTION FIGURE 2-7 EFFECT OF RIM AND SIM INSTRUCTIONS ON SERIAL DATA LINESFUNCTIONAL DESCRIPTION 23 HOW THE MCS-85 SYSTEM WORKS The 8085A CPU generates signals that tell peripheral devices what type of information is on the multiplexed Address/Data bus and from that point on the operation is almost identical to the MCS-80™ CPU Group. A multiplexed bus structure was chosen because it freed device ins so that more functions could be integrated ‘on the 8085A and other components of the fami- ly. The multiplexed bus is designed to allow complete compatibility to existing peripheral components with improved timing margins and access requirements. (See Figure 2-8.) To enhance the system integration of MCS-85, several special components with combined memory and 1/0 were designed. These new devices directly interface to the multiplexed bus of the 8085A. The pin locations of the 8085A, and the special peripheral components are assigned to minimize PC board area and to allow for efficient layout. The details on peripheral components are contained in subse- quent paragraphs of this chapter and in Chapters 6 and 6. FIGURE 28A MCS-20" CPU GROUP a [> soontssaus FIGURE 2.88 MCS-85"H CPUIBOR5A (MCS-80 COMPATIBLE FUNCTIONS) FIGURE 2.8C MULTIPLEXED BUS TIMING FIGURE 2-8 BASIC CPU FUNCTIONSFUNCTIONAL DESCRIPTION 23.1 Multiplexed Bus Cycle Timing The execution of any 8085A program consists of a sequence of READ and WRITE operations, of which each transfers a byte of data between the 8085A and a particular memory or JO ad- dress. These READ and WRITE operations are the only communication between the processor and the other components, and are all that is Necessary to execute any instruction or pro- gram. Each READ or WRITE operation of the 80854 is teferred to as a machine cycle. The execution of each instruction by the 8085A consists of a se- quence of from one to five machine cycles, and each machine cycle consists of a minimum of from three to six clock cycles (also referred to as T states). Consider the case of the Store Ac- cumulator Direct (STA) instruction, shown in Figure 2-9. The STA instruction causes the con- tents of the accumulator to be stored at the direct address specified in the second and third bytes of the instruction. During the first machine cycle (M,), the CPU puts the contents of the program counter (PC) on the address bus and performs a MEMORY READ cycle to read from memory the opcode of the next instruction (STA). The M; machine cycle is also referred to as the OPCODE FETCH cycle, since it fetches the operation code of the next instruction. In the fourth clock cycle (T,) of M;, the CPU inter- prets the data read in and recognizes it as the ‘opcode of the STA instruction. At this point the CPU knows that it must do three more machine cycles (two MEMORY READs and one MEMORY WRITE) to complete the instruction. The 8085A then increments the program counter so that it points to the next byte of the instruction and performs a MEMORY READ machine cycle (M2) at address (PC + 1). The ac- cessed memory places the addressed data on the data bus for the CPU. The 8085A temporarily stores this data (w! is the low-order byte of the direct address) internally in the CPU. The 8085A again increments the program counter to location (PC +2) and reads from memory (M3) the next byte of data, which is the high- order byte of the direct address. At this point, the 8085A has accessed all three bytes of the STA instruction, which it must now execute. The execution consists of placing the data accessed in M, and Ms on the address bus, then placing the contents of the accumulator on the data bus, and then performing a MEMORY WRITE machine cycle (M,). When Mg is finished, the CPU will fetch (M,) the first byte of the next instruction and continue from there. State Transition Sequence As the preceding example shows, the execution of an instruction consists of a series of machine cycles whose nature and sequence is determined by the opcode accessed in the My lawns FIGURE 2-9 CPU TIMING FOR STORE ACCUMULATOR DIRECT (STA) INSTRUCTION 29FUNCTIONAL DESCRIPTION fi | jro---eee ecos-e-e-[al = Logic “0” 1= Logie "I" TS=High Impedance X= Unipeifed FIGURE 2-10 8085A MACHINE CYCLE CHART machine cycle. While no one instruction cycle will consist of more than five machine cycles, every machine cycle will be one of the seven types listed in Figure 2-10. These seven types of machine cycles can be differentiated by the state ofthe three status lines VMN, Sand S) and the three control signals (RD, WR, and INTA). Most machine cycles consist of three T states, (cycles of the CLK output) with the exception of OPCODE FETCH, which normally has either four or six T states. The actual number of states required to perform any instruction depends on the instruction being executed, the particular machine cycle within the instruction cycle, and the number of WAIT and HOLD states inserted into each machine cycle through the use of the READY and HOLD inputs of the 8085A. The state transition diagram in Figure 2-11 il lustrates how the 8085 proceeds in the course ‘of a machine cycle. The state of various status and control signals, as well as the system buses, is shown in Figure 2-12 for each of the ten possible T states that the processor can be in, Figure 2-11 also shows when the READY, HOLD, and interrupt signals are sampled, and how they modify the basic instruction sequence (T;- Te and Twar). As we shall see, the timings for each of the seven types of machine cycles are almost identical. OPCODE FETCH (OF): The OPCODE FETCH (OF) machine cycle is unique in that it has more than three clock cycles. This is because the CPU must interpret the opcode accessed in T;, Ta, and T; before It can decide what to do next. © - ayaeaasworserensorn FIGURE 2-11 8085A CPU STATE TRANSITION 28FUNCTIONAL DESCRIPTION Sanus & Buses Machine Sute_|51,5010/81|Ap-Arg|AD9-ADy 7 xx] x] x 7 m fxix} x] x x|o twar | x} x | x | x x|o 1 xix] x] x x|o ™ rfol x | 4s rio 1 rfo| x | ts ajo 1. rfo} x | ts Jrje taeser | x [ts] ts | ts | ts[ 1) 0 twur | 0 [ts| ts | ws | ts] 1) 0 two | x|ts| ts | ts | ts] 1] 0 0 Lopie "0" 1=Lople “1 TS=High Impadence X=Unpectind ALE not generated during 2rd and ra machine cycles of DAD. “OVA = 1 during T4-Te sate of AST and INA cycles. FIGURE 2-12 8085A MACHINE STATE CHART Figure 2-13 shows the timing relationships for an OF machine cycle. The particular instruction illustrated is DCX, whose timing for OF differs from other instructions in that it has six T states, while some instructions require only four T states for OF. In this discussion, as well ‘as the following discussions, only the relative timing of the signals will be discussed; for the actual timings, refer to the data sheets of the in- dividual parts in Chapters 5 and 6. ‘The first thing that the 8085A does at the begin- ning of every machine cycle is to send out three status signals ((O/M, S1, SO) that define what type of _machine cycle is about to take place. ‘The 1O/M signal identifies the machine cycle as being either a memory reference or input/output operation. The Si status signal identifies whether the cycle is a READ or WRITE oper tion. The SO and S1 status signals can be used together (see Figure 2-10) to identify READ, WRITE, or OPCODE FETCH machine cycles as well as the HALT state. Referring to Figure 2-13, the 8085A will send out |O/M = 0,S1 = 1,50 = 1 at the beginning of the machine cycle to iden- tify it as a READ from a memory location to ob- tain an opcode; in other words, it identifies the machine cycle as an OPCODE FETCH cycle. ‘The 8085A also sends out a 16-bit address at the beginning of every machine cycle to identify the particular memory location or 1/0 port that the machine cycle applies to. In the case of an OF ‘cycle, the contents of the program counte placed on the address bus. The high order byte (PCH) is placed on the As-A;s lines, where it will stay until at least Ts. The low order byte (PCL) is placed on the ADp-AD; lines, whose three-state drivers are enabled if not ‘found already on. Unlike the upper address lines, however, the in- formation on the lower address lines will re- main there for only one clock cycle, after which the drivers will go to their high impedance state, indicated by a dashed line in Figure 2-13. This is necessary because the AD,-AD; lines are time mulitplexed between the address and data buses. During T; of every machine cycle, ADg- AD; output the lower Bbits of address after which ADgAD, will either output the desired data for a WRITE operation or the drivers will float (as is the case for the OF cycle), allowing the external device to drive the lines for a READ operation. Since the address information on ADg-AD; is of a transitory nature, it must be latched either in- ternally in special multiplexed-bus components like the 8155 or externally in parts like the 8212 Bit latch. (See Chapter 3.) The 8085A provides @ special timing signal, ADDRESS LATCH ENABLE (ALE), to facilitate the latching of Ag-A7; ALE Is present during T; of every machine cycle. After the status signals and address have been sent out and the ADo-AD, drivers have been disabled, the 8085A provides a low level on RD to enable the addressed memory device. The device will then start driving the ADo-AD; lines; this is indicated by the dashed line turnin, 10 a solid line in Figure 2-13. After a period of time. (which is the access time of the memory) valid data will be present on ADo-AD;. The 8085A dur- ing Ts will load the memory data on ADg-AD; in- to its instruction register and then raise FD to the high level, disabling the addressed memory device. At point, the 8085A have fin- ished accessing the opcode of the Instruction. Since this is the first machine cycle (My) of the instruction, the CPU will automatically step to Ty, as shown in Figure 2-11. During Ts, the CPU will decode the opcode in the instruction register and decide whether to enter Ts on the next clock or to start a new machine cycle and enter T;. In the case of the DCX instruction shown in Figure 2-13, it will enter Ts and then Tg before going to T;.FUNCTIONAL DESCRIPTION ‘018, Artis Abya0; ® FIGURE 2-13 OPCODE FETCH MACHINE CYCLE (OF DCX INSTRUCTION) During Ts and Ts, of DCX, the CPU will decre- ment the designated register. Since the As-A1s lines are driven by the address latch circuits, which are part of the incrementer/decrementer logic, the Ag-A;s lines may change during Ts and Te, Because the value of Ag-Ais can vary during '¢Te, it is most important that all memory and VO devices on the system bus qualify their selection with AD. If they don’t use RD, they may be spuriously selected. Moreover, with a linear selection technique (Chapter 3), two or more devices could be simultaneously enabled, which could be potentially damaging. The generation of spurious addresses can also oc- cur momentarily at address bus transitional periods in Tj. Therefore, the selection of memory and I/O devices must be qualified with RD or WR. Many new memory devices like the 8155 and 8355 have the AD input that internally is used to enable the data bus outputs, remov- Ing the need for externally qualifying the chip enable input with RD. Figure 2-14 is identical to Figure 2-13 with one exception, which is the use of the READY line. ‘As we can see in Figure 2-11, when the CPU Ta, it examines the state of the READY II the READY line is high, the CPU will proceed to T3 and finish executing the instruction. If the READY line is low, however, the CPU will enter Twat and stay there indefinitely until READY goes high. When the READY line does go high, the CPU will exit Twarr and enter Ta, in order to complete the machine cycle. As shown in Figure 2-14, the external effect of using the READY line is to preserve the exact state of the processor signals at the end of T, for an integral number of clock periods, before finishing the machine cycle. This “stretching” of the system timing has the further effect of increasing the allowable access time for memory or /O devices. By inserting Twarr states, the 8085A can accommodate even the slowest of memories. Another common use of the READY line is to singe-step the processor with a manual switch. 2.8.2 Read Cycle Timing MEMORY READ (MR): Figure 2-15 shows the timing of two successive MEMORY READ (MR) machine cycles, the first without a Twarr state and the second with one ‘Twarr State. The timing during T;-Ts is absolute- ly identical to the OPCODE FETCH machine cy- cle, with the exception that the status sent out during T; is 1O/M = 0, 1 = 1, $0 = 0, identify- ing the cycles as a READ from a memory loca- tion. This differs from Figure 2-13 only in that SO = 1 for an OF cycle, identifying that cycle as an OPCODE FETCH operation. Otherwise, the two cycles are identical during T-Ts. A second difference occurs at the end of T3. As shown in Figure 2-11, the CPU always goes to Ty, from T3 during My, which is always an OF cycle. During all other machine cycles, the CPU will always go from Ts to T; of the next machine cycle. 210FUNCTIONAL DESCRIPTION sonaL 7 ware % 7 5 % FIGURE 2-14 OPCODE FETCH MACHINE CYCLE WITH ONE WAIT STATE sou hl MI Ts n Mi Twarr a 2 see chenienseoas bese Sa snstotomnsiees see sea = Ber wr ar » FIGURE 2-15 MEMORY READ (OR 1/0 READ) MACHINE CYCLES. (WITH AND WITHOUT WAIT STATES)FUNCTIONAL DESCRIPTION The memory address used in the OF cycle is always the contents of the program counter, which points to the current instruction, while the address used in the MR cycle can have ‘several possible origins. Also, the data read in during an MR cycle is placed in the appropriate register, not the instruction register. UO READ (IOR): Figure 2-15 also shows the timing of two suc- cessive 0 READ (1OR) machine cycles, the first without a Twarr state. As is readily apparent, the timing of an IOR cycle is identical to the timing ‘of an MR cycle, with the exception of IO/M = 0 for MR and IO/M = 1 for IOR; recall that |O/M status signal identifies the address of the cur- rent machine cycle as selecting either a memory location or an I/O port. The address used in the 1OR cycle comes from the second byte (Port No.) of an INPUT instruction. Note that the I/O port address is duplicated onto both ADg-AD; and Ag-A1s. The IOR cycle can occur only as the third machine cycle of an INPUT in- struction. Note that the READY signal can be used to generate Twarr States for I/O devices as well as, memory devices. By gating the READY signal with the proper status lines, one could generate Twair States for memory devices only of for lO devices only. By gating in the address lines, one can further qualify Twair state generation by the particular devices being accessed. 23.3 WRITE Cycle Timing MEMORY WRITE (MW): Figure 2-16 shows the timing for two successive MEMORY WRITE (MW) machine cycles, the first without a Twarr state, and the second with one ‘Twarr State. The 8085A sends out the status dur- ing T; in a similar fashion to the OF, MR and 1OR cycles, except that !O/M = 0,S1 = 0, and S0= 1, identifying the current machine cycle as being a WRITE operation to a memory location. The address is sent out during T; in an identical manner to MR. However, at the end of T;, there is a difference. While the ADo-AD; drivers were disabled during TzTs of MR In expectation of the addressed memory device driving the ADo- AD; lines, the drivers are. not disabled for MW. This is because the CPU must provide the data to be written into the addressed memory loca- tion. The data is placed on AD,-AD; at the start of Tz. The WR signal is also lowered at this time to enable the writing of the addressed memory device. During Tz, the READY line is checked to see if a Twarr State Is required. If READY is low, «r states are inserted until READY goes high. During Ts, the WR line is raised, disabling the addressed memory device and thereby ter- minating the WRITE operation. The contents of the address and data lines are not changed un- til the next T;, which directly follows. Note that the data on ADg-AD; is not guaranteed to be stable before the falling edge Toit-o mm on B ieleelihetl ‘Ao, A0, SCE = a FIGURE 2-16 MEMORY WRITE (OR 1/0 WRITE) MACHINE CYCLES (WITH AND WITHOUT WAIT STATES)FUNCTIONAL DESCRIPTION of WR. The AD,-AD; lines are guaranteed to be stable both before and after the rising edge of VO WRITE (OW): As Figure 2-16 shows, the timing for an VO WRITE (OW) machine cycle is the same as an MW machine cycle except that IO/M = 0 during ‘the MW cycle and IO/M = during the |OW cycle. As with the IOR cycle discussed previously, the address used in an IOW cycle is the 1/0 port number which Is duplicated on both the high and low bytes of the address bus. In the case of IOW, the port number comes from the second byte of an OUTPUT instruction as the instruc: tlon Is executed. 2.3.4 Interrupt Acknowledge (INA) Timing Figures 2-17 and 2-18 (a continuation of 2-17) depict the course of action the CPU takes in response to a high level on the INTR line if the INTE FF (Interrupt enable flip-flop) has been set by the El instruction, The status of the TRAP and RST pins as well as INTR is sampled during the second clock cycle before My + Ty. If INTR was the only valid interrupt and if INTE FF is set, then the CPU will reset INTE FF and then enter an INTERRUPT ACKNOWLEDGE (INA) machine cycle. The INA cycle is identical to an OF cycle with two exceptions. INTA is sent out instead of RD. Also, 1O/M = 1 during INA, whereas IO/M = 0 for OF. Although the con- tents of the program counter are sent out on the address lines, the address lines can be ignored. When INTA is sent out, the external interrupt logic must provide the opcode of an instruction to execute. The opcode is placed on the data bus and read in by the processor. If the opcode is the first byte of a multiple-byte instruction, additional pulses will be provided by the 8085A to clock in the remaining bytes. RESTART and CALL instructions are the most (onst.s0 fete ABAD m FIGURE 2-17 INTERRUPT ACKNOWLEDGE MACHINE CYCLES (WITH CALL INSTRUCTION IN RESPONSE TO INTR)FUNCTIONAL DESCRIPTION logical choices, since they both force the pro- cessor to push the contents of the program counter onto the stack before jumping to anew location. In Figure 2-17 it is assumed that a CALL opcode is sent to the CPU during M,. The CALL opcode could have been placed there by a device like the 8259 programmable interrupt controller. After receiving the opcode, the processor then decodes it and determines, in this case, that the CALL instruction requires two more bytes. The CPU therefore performs a second INA cycle (M2) to access the second byte of the instruction from the 8259. The timing of this cycle is iden- tical to My, except that it has only three T states. Mz is followed by another INA cycle (Ms) to access the third byte of the CALL instruction from the 8259, Now that the CPU has accessed the entire in- struction used to acknowledge the interrup! will execute that instruction. Note that any i struction could be used (except El or DI, the in- structions which enable or disable interrupts), but the RESTART and CALL instructions are the most logical choices. Also notice that the CPU hibited the incrementing of the program counter (PC) during the three INA cycles, 80 that the correct PC value can be pushed onto the stack during Mg and Ms, During My and Ms, the CPU performs MEMORY WRITE machine cycles to write the upper and then lower bytes of the PC onto the top of the stack. The CPU then places the two bytes ac- cessed in Mz and Mg into the lower and upper bytes of the PC. This has the effect of jumping the execution of the program to the location specified by the CALL instruction. mai oan FIGURE 2- (WITH CALL 2 INTERRUPT ACKNOWLEDGE MACHINE CYCLES INSTRUCTION IN RESPONSE TO INTR)2.3.5 Bus Idle (Bl) and HALT State Most machine cycles of the 8085A are associated with either a READ or WRITE opera- tion. There are two exceptions to this rule. The first exception takes place during Mz and Ms of the DAD instruction. The 8085A requires si ternal T states to execute a DAD instru: but it is not desirable to have M; be ten (four normal plus six extra) states long. Therefore, the CPU generates two extra machine cycles that do not access either the memory or the 1/0. These cycles are referred to as BUS IDLE (BI) machine cycles. In the case of DAD, they are identical to MR cycles except that RD remains high and ALE is not generated. Note that READY is ignored during Mz and M3 of DAD. line is FUNCTIONAL DESCRIPTION The other time when the BUS IDLE machine cy- cle occurs Is during the internal opcode genera- tion for the RST or TRAP interrupts. Figure 2-19 ignored during the BI cycle. 4p ~-b += 4 Ke | i | i | [ee ee see aca CPT FIGURE 2-19 RST 7.5 BUS IDLE MACHINE CYCLE 218. illustrates the BI cycle generated in response to RST 7.5. Since this interrupt is rising-edge- triggered, it sets an internal latch; that latch is sampled at the falling edge of the next to the last T-state of the previous instruction. At this n, point the CPU must generate its own internal RESTART instruction which will (in subsequent machine cycles) cause the processor to push the program counter on the stack and to vector to location 3CH. To do this, it executes an OF machine cycle without issuing RD, generating the RESTART opcode instead. After My, the CPU continues execution normally respects except that the state of the READY allFUNCTIONAL DESCRIPTION Figure 2-20 illustrates the BI cycle generated in Tesponse to RST 7.5 when a HALT instruction has just been executed and the CPU is in the Tract state, with its various signals floating. There are only two ways the processor can com- pletely exit the Tracy state, as shown in Figure 2-11, The first way is for RESET to occur, which always forces the 8085A to Taeser. The second way to exit Tat permanently is for a valid in- terrupt to occur, which will cause the CPU to disable further interrupts by resetting INTE FF, and to then proceed to M; + T; of the next in- struction. When the HOLD input is activated, the CPU will exit Tyacr for the duration of Two and then return to Traut. In Figure 2-20 the RST 7.5 line is pulsed during Tuart- Since RST 7.5 is a rising-edge-triggered interrupt, it will set an internal latch which is sampled during CLK = “1” of every Tuair state (as well as during CLK '1" two T states before any M, « T;,) The fact that the latched in- terrupt was high (assuming that INTE FF = and the RST 7.5 mask =0) will force the CPU to exit the THacr state at the end of the next CLK period, and to enter M; + Ty. This completes our analysis of the timing of each of the seven types of machine cycles. mer com hese [ieee acter oto = Ve ce at eal me rn i ee eee mee FIGURE 2-20 HALT STATE AND BUS IDLE MACHINE CYCLE RST 7.5 TERMINATES Tuart STATEFUNCTIONAL DESCRIPTION 2.3.6 HOLD and HALT States The 8085A uses the THo.o state to momentarily cease executing machine cycles, allowing ex- temal devices to gain control of the bus and peform DMA cycles. The processor internally latches the state of the HOLD line and the un- masked interrupts during CLK = “1” of every ‘Tuatr state. If the internal latched HOLD signal is high during CLK = “1” of any Tuatr State, the CPU will exit Taar and enter Tov on the following CLK = “1”. As shown in Figure 2-21 this will occur even if a valid interrupt occurs simultaneously with the HOLD signal. The state of the HOLD and the unmasked inter- rupt lines is latched Internally during CLK = 1 of each Tyoup state as well as during Tat states. If the internal latched HOLD signal is low during CLK = 1, the CPU will exit Tou and enter Tyacr on the following CLK = ‘The 8085A accepts the first unmasked, enabled interrupt sampled; thereafter, all interrupt sampling is inhibited. The interrupt thus ac- cepted will inevitably be executed when the CPU exits the HOLD state, even at the expense of holding off higher-priority interrupts ‘luding TRAP). (See Figure 2-22.) ‘When the CPU is not in THact OF THoo, it inter- nally latches the HOLD line only during CLK = ‘of the last state before Ts (Te oF Twat) and dur- ing CLK = 1 of the last state before Ts (T, of a six T-state M;). If the internal latched HOLD signal is high during the next CLK = 1, the CPU will enter Top after the following clock. When the CPU Is notin Tact or THoto, It will internally latch the state of the unmasked interupts only during CLK of the next to the last state before each My « Ty. fare (eee dee e/g wm LY FIGURE 2-21 HOLD VS INTERRUPT — NON HALT anFUNCTIONAL DESCRIPTION I | a ee | = eee | =" 1 FIGURE 2-22 8085A HOLD VS INTERRUPTS — HALT MODE 2.3.7 Power On and RESET IN The 8085A employs a special internal circuit to Increase its speed. This circuit, which is called a substrate bias generator, creates a negative voltage which is used to negatively bias the substrate. The circuit employs an oscillator and a charge pump which require a certain amount ‘of time after POWER ON to stabilize. (See Figure 2:23.) Taking this circuit into account, the 80B5A is not guaranteed to work until 10 ms after Voc reaches 4.75V. For this reason, it is suggested ‘that RESET IN be kept low during this period. Note that the 10 ms period does not include the time it takes for the power supply to reach its 4,75V level — which may be milliseconds in ‘some systems. A simple RC network (Figure 3-6) can satisfy this requirement. The RESET IN line is latched every CLK = 1. This latched signal is recognized by the CPU during CLK = 1 of the next T state. (See Figure 2.24.) If it is low, the CPU will issue RESET OUT and enter Tyacr for the next T state. RESET IN should be kept low for a minimum of three clock periods to ensure proper synchronization of the CPU. When the signal goes high, the 218 CPU will enter My « T; for the next T state. Note that the various signals and buses are floated in Treser 88 well a8 Tuat and THoup. For this reason, it is desirable to provide pull-up resistors_for the main control signals (par- ticularly WR). Specifically, the RESET IN signal causes the following actions: RESETS SETS PROGRAM COUNTER RST 5.5 MASK INSTRUCTION REGISTER RST 6.5 MASK INTE FF RST 7.5 MASK RST 7.5 FF TRAP FF SOD FF MACHINE STATE FF's MACHINE CYCLE FF’s INTERNALLY LATCHED FF’s for HOLD, INTR, and READY RESET IN does not explicitly change the con- tents of the 80854 registers (A, B, C, D, E, H, L) and the condition flags, but due to Ri oc: curring at a random time during instruction ex- ecution, the results are indeterminate.FUNCTIONAL DESCRIPTION FIGURE 2-23 POWER-ON TIMING man eser obese] 4+ FIGURE 2-24 RESET IN TIMING -+-47] Following RESET, the 8085A will start executing instructions at location 0 with the interrupt system disabled, as shown in Figure 2.24. Figure 2-24 also shows READ and WRITE opera- tions being terminated by a RESET signal. Note that a RESET may prematurely terminate any READ or WRITE operation in process when the RESET occurs. 2.3.8 SID and SOD Signals: Figure 2-25 shows the timing relationship of the SID and SOD signals to the RIM and SIM instruc- tions. The 8085A has the ability to read the SID line into the accumulator bit 7 using RIM instruc- tions. The state of the SID line is latched int nally during Ts « CLK = Oof the RIM instruction. Following this, the state of the interrupt pins and masks are also transferred directly to the accumulator. ‘The 8085A can set the SOD flip-flop from bit 7 of the accumulator using the SIM instruction. (See Figure 2:26.) The data is transferred from the ac- cumulator bit 7 to SOD during My + Tz» CLK = 0 of the instruction following SIM, assuming that accumulator bit 6 is a 1. Accumulator bit 6 is a “serial output enable” bit.FUNCTIONAL DESCRIPTION ‘A040, » [| MY eT TMS FIGURE 2-25 RELATIONSHIP OF SID AND SOD SIGNALS TO RIM AND SIM INSTRUCTIONS: EFFECT OF RIM INSTRUCTION EFFECT OF SIM INSTRUCTION S10 00 4 z 9 Cl AAA, ‘ACCUMULATOR ‘ACCUMULATOR FIGURE 2.26 EFFECT OF RIM AND SIM INSTRUCTIONS 2.4 COMPARISON OF MCS-80 AND MCS-85 SYSTEM BUSES This section compares the MCS-80 bus with the MCS-85 bus. Figure 2-28 details the signals and general timing of the two buses; the timing diagrams are drawn to the same scale (8080A clock cycle = 480 ns and 8085A clock cycle = 320 ns) to facilitate comparison. 220FUNCTIONAL DESCRIPTION MCS-80™ System Bus ‘The MCS-80 bus is terminated on one end by the CPU-GROUP (consisting of the 8080A, 8224, 8228) and on the other end by the various memory and 1/0 circuits. The following figure shows the major signals of the MCS-80 bus. eee aeeee a tc s— 9 a sa FIGURE 2-27 COMPARISON OF SYSTEM BUSES MCS-85™ System Bus ‘The MCS-85 bus is terminated on one end by the ‘80854 and the other end by various memory and WO devices. The MCS-85 bus may be optionally de-multiplexed with an 8212 eight bit latch to provide an MCS-80 type bus. The following figure shows the major signals of the MCS-85 bus. MCS-80™ System Bus SIGNAL(S) FUNCTION AgAis The 16 lines of the address bus identify a memory or 1/0 location for a data transfer operation. The 8 lines of the data bus are used for the parallel transfer of data between two devices. These five control lines (MEMORY READ, MEMORY WRITE, ]O READ, JO WRITE, and INTERRUPT ACKNOWL- EDGE) identify the type and timing of a data transfer operation. These signals are used for the synchronization of slow speed memories, system reset, DMA, sytem timing, and GPU interrupt. DoDr (oR OW TYR READY, RESET, HOLD, HLDA 62 (TTL), INT FIGURE 2.28 COMPARISON OF SYSTEM BUSES, 221 MCS-85™ System Bus SIGNAL(S) FUNCTION AsAis These are the high order eight bits of the address, and are used to identity a memory or I/O location for a data transfer cycle, These eight lines serve a dual function. During the beginning of a data transfer operation, these lines carry the low order eight bits of the address bus. During the remainder of the cycle, these lines are used for the parallel transfer of data be- tween two devices. These signals identify the type and timing of a data transfer cycle. The VO/MEMORY line iden- tifies a data transfer as be- ing in the ]O address space or the memory address space. ADDRESS LATCH ENABLE enables the latching of the AvAz signals. These signals are used for the synchronization of slow speed memories, system reset, DMA, system timing and CPU interrupt. AD,-AD; RD, WR, INTA 11m ALE READY, RESET OUT, HOLD, HLDA, CLK, INTRFUNCTIONAL DESCRIPTION MCS-80™ System Bus for READ CYCLE ‘The basic timing of the MCS-80 BUS for a READ CYCLE is as follows: @} / 00m ome ee Wares The MCS-80 first presents the address @ and shortly thereafter the control signal@. The data bus, which was in the high impedance state, is driven by the selected device @). The selected device eventually presents the valid data to the processor @). The processor raises the control signal @, which causes the select- ed device to put the data bus in the high impe- dance state@). The processor then changes the address @)for the start of the next data transfer. MCS.80™ System Bus for WRITE CYCLE The basic timing of the MCS-80 BUS for a WRITE CYCLE is as follows: The MCS-80 first presents the address @, then enables the data bus driver@, and later presents the data@. Shortly thereafter, the MCS-80 drops the control signal @ for an inter- val of time and then raises the signal @. The MCS-80 then changes the address @in preparation for the next data transfer. The ad- vance write signal of the 8238 is also shown @. MCS-85™ System Bus for READ CYCLE The basic timing of the MCS-85 BUS for a READ CYCLE is as follows: ing of the READ cycle, the 80858 sends out all 16 bits of address (@). This is followed by ALE@which causes the lower eight bits of address to be latched in either the 8155/56, 8355, 8755A, or in an external 8212. RD is then dropped @ by the 8085A. The data bus is then tri-stated by the 8085A in preparation for the selected device driving the bus@); the selected device will continue to drive the bus with valid data@, until RD is raised @by the 085A. At the end of the READ CYCLE), the address and data lines are changed in prepara- tion for the next cycle. MCS-85™ System Bus for WRITE CYCLE The basic timing of the MCS-85 BUS for a WRITE CYCLE is as follows: ? ‘Avour our our vsvon- CX ao The timing of the WRITE CYCLE is identical to the MCS-85 READ CYCLE with the exception of the ADgAD7 lines. At the beginning of the cycle @, the low order eight bits of address are ‘on ADg-AD;. After ALE drops, the eight bits of data @ are put on ADp-ADy. They are removed @) at the end of the WRITE CYCLE, in anticipation of the next data transfer. FIGURE 2-28 (Continued) COMPARISON OF SYSTEM BUSES anFUNCTIONAL DESCRIPTION The following observations of the two buses can be made: 1. The access times from address leaving the processor to returning data are almost identical, even though the 8085A is operating 50% faster than the 8080. With the addition of an 8212 latch to the 8085A, the basic timings of the two systems are very similar. The 8085A has more time for address setup to RD than the 8080. ‘The MCS-80 has a wider RD signal, but a narrower WR signal than the 8085A. ‘The MCS-80 provides stable data setup to the leading and trailing edges of WR, while the 8085 provides stable data setup to only the trailing edge of WR. The MCS-80 control signals have different widths and occur at different points in the machine cycle, while the 8085A control signals have identical timing. 7. While not shown on the chart, the MCS-80 data and address hold times are adversely affected by the processor preparing to enter the HOLD state. The 80854 has iden- tical timing regardless of entering HOLD. ‘Also not shown on the chart is the fact that all output signals of the 8085A have ~~ 400ya of source current and 2.0 ma of sink current. The 8085A also has input voltage levels of Vi. = 0.8V and Vin =2.0V. CONCLUSION: The preceding discussion has clearly shown that the MCS-85 bus satisfies the two restric- tions of COMPATIBILITY and SPEED. It is com- patible because it requires only an 8212 latch to generate an MCS-80 type bus. If the four control signals MEMR, MEMW, IOR and IOW are desired, they can be generated from RD, WR, 6. and 10/M with a decoder or a few gates. The MCS-85 bus is also fast. While running at 3MHz, the 8085A generates better timing signals than the MCS-80 does at 2MHz. Furthermore, the multiplexed bus structure doesn’t slow the 8085A down, because it is using the internal states to overlap the fetch and execution por- tions of different machine cycles. Finally, the MCS-85 can be slowed down or sped up con- siderably, while still providing reasonable timing. TO USE. The RD, WR, and INTA contro! signals all have identical timing, which isn’t affected by the CPU preparing to enter the HOLD state. Fur- thermore, the address and data bus have good setup and hold times relative to the control signals. The voltage and current levels for the interface signals will all drive buses of up to 40 MOS devices, or 1 schottky TTL device. ‘The MCS-85 system bus is also EFFICIENT. Ef ciency is the reason that the lower eight ad- dress lines are multiplexed with the data bus. Every chip that needs to use both Ag-Ar and Do- D, saves 7 pins (the eighth pin is used for ALE) ‘on the interface to the processor. That means that 7 more pins per part are available to either add features to the part or to use a smaller Package in some cases. In the three chip system shown in Figure 36, the use of the MCS-85 bus saves 3 x 7 = 21 pins, which are used for extra /O and interrupt lines. A further advantage of the MCS-85 bus is apparent in Figure 3-7, which shows a printed circuit layout of the circuit in Figure 36. The reduced number of pins and the fact that compatible pinouts were used, provides for an extremely compact, simple, and efficient printed circuit. Notice that great care was taken when the pinouts were assigned to ensure that the signals would flow easily from chip to chip to chip.System Operating and _ 7 3 InterfacingCHAPTER 3 8085A SYSTEM OPERATION AND INTERFACING 3.1. INTERFACING TO THE 80850 The 8085A interfaces to both and vO devices by means of READ and WRITE machine cycles, the timing of which are identical. During ‘each machine cycle the 8085A issues an address and a control signal, then either sends data out on the bus or reads data from the bus. The 8085A may be performing a READ machine cycle, but what treads could be a ROM, RAM, I/O device, periph- eral device, or nothing. There is no distinction between data, instruction ‘opcodes, and VO port numbers except the way the CPU interprets what it reads from the bus. If an op- code is what would logically appear on the bus, the CPU will treat as an opcode whatever does appear ‘there; if an VO port number is to be expected, what appears will be Interpreted as a port number. The same is true for a WRITE cycle. The 8085A issues. an address, data, and a control signal. Unies it is, requested to WAIT (by use of the READY line) it will complete the cycle and proceed to the next. Regard- less of whether there Is a device present to accept the data, the CPU executes one instruction at a time, in sequence, until told to do otherwise. The rogram controls the sequence and nature of all Machine cycles until an interrupt occurs. ‘There are two ways of addressing /O devices in the MCS25 system. If the IO/M output from the CPU is used to distinguish between VO and memory READ and WRITE cycles, then that system is said to employ standard, or , VO. If 10/M is not so used, the CPU does not distinguish between VO and memory, and its system employs memory- mapped /0. Each method of addressing JO has ad- vantages and disadvantages. 3.2 MEMORY-MAPPED 10 321 Advantages of Memory-Mapped YO Since the processor doesn’t distinguish VO from memory using this addressing scheme, you can take advantage of the larger instruction set that references the memory address space. instead of only being able to transfer a byte of data between the accumulator and the UO port (using INPUT and OUTPUT instructions), you can now program arithmetic and logic operations on port data as well as move data between any internal register and the VO port. Consider the new meaning of the following instructions: Examples: MOVrM (Input Port to any Register) MOV M, (Output any Register to Port) MVM" (Output immediate data to Port) LDA (Input Port to ACC) STA (Output from ACC to Port) LHLD (16Bit Input) SHLD (168it Output) ADD M (Add Port to ACC) ANAM (AND Port with ACC) 322 Disadvantages of Memory-Mapped UO While memory instructions may increase the tlex- ibllty of the UO system, there are some drawbacks. ‘Since VO devices are now addressed as memory, there are fewer addresses available for memory. A ‘common practice is to use address bit 15 (Ars) to distinguish memory from W/O. (See Figure 32 and accompanying discussion) If Ajg=0 then memory is being addressed; if As=1, VO Is being ad- dressed. This particular scheme limits the max- imum amount of memory that can be used to 32k bytes. A further disadvantage of memory-mapped VO is that It takes 3 bytes of instruction and 13 clock cycles using the LDA or STA Instructions to specify moving a byte of data between the ac- cumulator and an I/O device, whereas the INPUT ‘and OUTPUT instructions require only two bytes and 10 clock cycles. This is because the 1/0 ad- dress space is smaller (only 256 bytes) and there- fore requires fewer bits to completely specify an address. A futher advantage of using the IN- PUT and OUTPUT Instructions Is that It allows the easy connection of the MCS-80 peripherals to the MCS-85 multiplexed bus. If you memory- map the MCS-80 peripherals to the MCS-85 bus, you must either latch the lower address bits with an 8212 or use a portion of the memory ad- dress space by connecting the chip selects and address lines of the ports to the unmultiplexed upper eight lines of the address bus.SYSTEM OPERATION 3.3. ADDRESS ASSIGNMENT 3.3.1 Decoding Besides memory-mapped 1/0, another practice is to only partially decode the address bus when generating chip selects. Every device has a given number of unique addresses associated with it, The 8355, for instance, has 2k bytes of ROM and therefore has 2k addresses associated with the ROM. Any one of these 2k addresses can be uniquely specified by a pattern on the 11 (211 = 2k) address lines. However, since the 8355 must work with other devices in a system, it isn’t enough to simply specify the 11 bits; fur- ther bits of information must be used to locate the 2k bytes within the 65k address space. The 2k bytes are located by the use of chip enable (CE) inputs to the 8355 chip. If the 8355 were to ‘occupy the first 2k bytes of the memory address space, it would, strictly speaking, be necessary to decode the fact that Ais-Ay1 were all zeroes, and use that condition as a chip enable. Then the 8355 would be selected only when the ad- dress bus was less than 2k. However, if other 2k blocks of addresses aren't being used, you may combine those addresses and not decode all of the upper five address lines for chip enables. In fact, in a small system you may need to decode only one bit of address, which is to say connect that bit of the address bus to the chip enable line of the 8355. If you connect Aj; to the CE line of the 8355 and tie CE to Veo, then the 8355 would be selected when- ever the memory address was less than 2k. (See Figure 3-14) However, it will also be selected whenever memory ‘locations 4k-6k, 8K-10k, 61k-63k (ie, whenever bit Ar; =0) is addressed. If the pro- grammer is aware of this, and if there are no other devices assigned to the other address spaces, then it may be an acceptable condition. Care must be taken, however, to ensure that at no time will two different devices be selected simultaneously. Whenever one device is selected, that memory address must deselect all other devices. If two devices are selected simultaneously for a READ operation, the elec- trical conflict on the bus may damage one or both parts. Note also that the address bus may reflect an undesired address during Ts, Ts of an ‘opcode fetch cycle and during address bus transitional periods in T; (this is illustrated in Chapter 2). Therefore, ‘all memory and VO devices must qualify their selection with RD or WR, or the address on the bus at the falling ‘edge of the ALE, sos to ignore all spurious ad- dresses. 3.3.2 Linear Selection Using an address bit as a chip select is referred to as linear selection. The direct consequence of linear selection is that you cut the available address space in half for each single address. bit used as a chip enable. If this penalty is too high, you can always use an 8205 one-of-eight decoder. Also, some chips have multiple chip enables, which allows for some automatic decoding of the address. (See Figures 3-1B and 310) ‘One drawback to linear selection is that the memory addresses of the different parts are not contiguous. For example, if three 8355s are ad- dressed using linear selection, one might be located at 0-2k, the next at 6k-8k, and the next at 10k-12k. The programmer must recognize these page boundries and jump over them. 34 INTERFACING TO THE 8155/8156, 8355/8755 3.4.1, 10 Mapped 10: This section describes some of the techniques involved in connecting the MCS-85 combination memory and VO chips to the 8085A as 1/0 devices. Figure 3.14 shows one 8355 connected to the 085A bus. (In the interest of simplicity, only the chip enable and IO/M lines are shown; the other lines are connected as shown in Figures 3.6, 3.7 of 3.8) Notice that CE is tied to Voc and CE is, connected to Ax. This is because after RESET the processor always starts executing at loca- tion 0. Since the ROM normally contains the program, it must be selected when the address is all zeroes. ‘One consequence of the ROM being selected by an all-zero address is that the VO ports on the chip will be selected only when A, =0. This is because the VO ports and the memory have common chip enables, therefore forcing the selection conditions of one onto the other. Fur- thermore, since the IO/M line of the chip is con- nected to the IO/M line of the 8085A, the port has VO mapped W/O. The VO ports can be ac- cessed only by use of the INPUT and OUTPUT instructions; since these are the only instruc- tions that cause IO/M to go high. The boxes to the right of the chip in Figure 3.14 indicate the memory addresses and VO Port numbers required to access the chip. As a result of the linear selection technique used, there are many “don't care” bits (marked by “X"s) in the address. While they don't affect the addressing of this device, they may affect otherSYSTEM OPERATION FIGURE S-1A SINGLE CHIP RTT An je om = 10 FIGURE 3.18 MULTIPLE CHIPS a he ee om ‘om : i focmmcacen) Con [a Exo TAA) FIGURE 3-1C FULLY DECODED AND EXPANDED a FIGURE 3-1 MCS-85™ PERIPHERALS WITH I/O MAPPED 1/0 33 oeSYSTEM OPERATION devices in the system, which would force them to be either ones or zeroes. Remember that two devices may not be selected simultaneously; thus each device must have an address that not only selects itself, but also deselects all other devices. If there are any bits which are truly “don’t cares,” they are customarily assigned to be zero. If all the “X" bits in Figure 3.1A were “don't cares,” then the chip could be addressed as memory locations 0-2k, and 1/0 Ports 0-3. Figure 3.18 shows a slightly larger system of two 8355s and one 8156. Notice that 8355 No. 1 uses its two chip enable lines to decode Ay=1, Aig=0. It is possible to address each of the chips without selecting any of the others. Also notice that there are some illegal addresses (€.g., A= 0, Ars= 1) that would cause two of the devices to turn on simultaneously. The pro- grammer must not use these addresses. Figure 3.1C shows a larger MCS-85 system. Two 820s are used to completely decode the ad- dresses. There are some interesting points to observe here. First, while some of the devices have multiple possible address (i.e., they have some “don't care” bits), there aren't any ad- dresses which can cause simultaneous selec- tion of two or more parts. Second, the VO and memory portions of the 8x55 components share chip enables, so they are forced to live with each other's constraints. Third, only one 8205 Is required per eight chips for the decoding; that's an overhead of only 1/8 of a chip per part. Figure 3.1D shows a remedy to the problem il- lustrated in Figure 3.1C, namely that /O and memory portions of the chip are forced to live with each other’s chip enable constraints. By using a quad 2 to 1 multiplexer, the chip enables of the 1/0 and memory portions of four chips can be independently assigned. 3.4.2 Memory-Mapped W/O: Figure 3.2A shows an 8355 connected to the 8085A. Since the IO/M pin of the 8355 is con- nected to Ars, whenever Ais =1 the I/O ports will be accessed. While Ajs could be set to 1 either by a memory or by an I/O instruction, in this situation the port is usually accessed only by the memory instructions. You may access ports either as memory locations (where Ais=1 refers to a memory address of 32k or higher) or as 1/0 ports (where Ars=1 refers to an iO ad- dress of 128 or higher, since bits AgAys are a FIGURE 32A SINGLE CHIP FIGURE 328 MULTIPLE CHIPS se (ape a — feos a (cette epee ee eee eee (ae TE el eee FIGURE 3-2 MCS-85™ PERIPHERALS WITH MEMORY-MAPPED 10 aSYSTEM OPERATION replication of bits Ag-A7). Assuming that memory-mapped 1/O is used, the addresses are shown in the boxes to the right in Figure 3-2. If you want to be sure that neither the I/O nor the memory is ever selected by any INPUT or OUT- PUT instruction, then the chip enable must be conditioned by IO/M =0. Figure 3.28 shows a somewhat larger system, also using memory-mapped 1/0. As in Figure 3.1B care must be exercised to ensure that no two devices are accessed simultaneously. You can see that considerable memory address space is used up as a result of using memory- mapped 1/0. 3.5 INTERFACING TO MCS-80™ PERIPHERALS 3.5.1 VO Mapped /0: For want of a better name, the Intel® 825x, 827x, and 829x series peripherals are referred to here as MCS-80 peripherals because unlike the 8155/ 56, 8355 and 8755A, they are compatible the nonmultiplexed MCS-80 system bus. To interface to an MCS-80 peripheral, you must Pigvide a constant address, a chip select, and ‘or WR. Since the upper address lines (Ag-A1s) of the 8085A are nonmultiplexed, they can be tied directly to the peripherals, 'as shown in Figure 3.3A. To provide JO mapped 1/0, use either linear selection (keeping the 1/0 and memory addresses noncoincidental), or condi- tion the chip selects WR with IO/M =1. Figure 3.3A shows a technique of gating the chip selects with IO/M=1, using an 8205. This technique also allows more I/O devices to be used than linear selection would. Note that this technique relies on the fact that the /O Port number is copied onto Ag Ais as well as Ag-Ay during an INPUT or OUTPUT instruction. Figure 3.3B shows an alternative approach to interfacing to MCS-80 components. By latching the lower 8 bits of address with an 8212, and decoding the control signals with an 8205, you create an exact copy of the MCS-80 (8080A, 8224, 8228) bus. You may then use whatever cir- cuits have been previously developed for the 8080. The total cost is one 8212 and one 8205. Since the same signals might have needed buf- fering anyway (and the 8212 and 8205 provide buffering of their outputs), the extra component overhead ranges from little to nothing. 3.5.2 Memory-Mapped 1/0: Exactly the same techniques used to memory map the MCS-85 apply to the MCS-80 l/O devices. Figure 3.4 shows an 8205 used to qualify the chip select of the VO device with 1O/M =0. Since as the MCS-80 peripherals require nonmultiplexed address lines, linear select is not too useful unless the address lines are latched. This is because connecting both the chip selects and the address lines of the MCS-80 peripherals to AgAis would deplete all the useful addresses very quickly. 3.6 INTERFACING TO STANDARD BUS MEMORIES: ‘Standard bus memory devices are designed to be used with nonmultiplexed address and data buses. Interfacing to standard memories is very lar to interfacing to MCS-85 memories with the exception that Ag-A7 must be latched. Once this requirement is met, all the tricks discussed earlier can be used. Since the address lines would eventually require buffering as the system size grew, the overhead of the 8212 latch again becomes negligible. Figure 3.5 shows the interface of the 8085A to a large block of memory, specifically 16k bytes of ROM and 8k bytes of RAM. Besides the memories, the circuit requires only 2-1/6 other parts for logical gating. If MCS-80 /O parts were used, the 8212 latch could be shared between the two groups, further reducing the gating overhead per IC. Sixteen 2142 chips and eight 2316E chips are used in this design. The data bus, address lines 8-10, and control signal: this system all should be buffered. This applies to any system with the number of memory devices represented here. Wherever two or more parts are paralleled on the same bus, they must be 3-state devices such as the 2142 RAM, 2316E ROM, 2716 EPROM, 2332 ROM, 2732 EPROM, and 2364 ROM, which have either an output disable (OD) input'or multiple chip select (CS) inputs. To pre- vent bus contention, only one memory device may be output-enabied at a time in this con- figuration; the outputs of all others must be deselected during RD. For additional information on interfacing stan- dard memory devices, please read Section 2 of Appendix | and the Intel applications note AP-30 “Application of Intel’s 5V EPROM and ROM Family for Microprocessor Systems” available from: Intel, Literature Dept., 3065 Bowers Ave., Santa Clara, CA 95051 3.7 DYNAMIC RAM INTERFACE: For interfacing the dynamic RAM, Intel makes a single-component dynamic RAM refresh con- troller, the 8202, which interfaces the 8085A to multiplexed-address-bus dynamic RAMs like‘SYSTEM OPERATION FIGURE 3.3A DECODED CHIP SELECTS. ri Fo or es Capea] » ro fone ra 30 ree FIGURE 3-38 DECODED CONTROLS AND LATCHED ADDRESS (MCS-80™ TYPE BUS) aE FIGURE 3-4 MCS-80™ PERIPHERALS WITH MEMORY-MAPPED I/O AND DECODED CHIP SELECTS: 26SYSTEM OPERATION the Intel 21044 and 2117. The 8202 provides the _ have constructed a microcomputer system that necessary refreshing for such dynamic RAMs, has the following functior ae also provides ind control signals: required PARTS FUNCTIONS for accessing, selecting, and address clocking. Itallows for the use of the 8085A's full capabili. | S085A Sy roles ty of 64k bytes of address space with no addi. 1 8355/8758 fondness tional buffering devices. As with other standard 1 8156 EPROM cr ROM memory interfaces, it is necessary to demulti- 1 Crystal on. plex the lower 8 bits of address from the multi- 4 Resistors 56 Bytes oF plexed 8085A bus, ADg7. 1 Capacitor $8 VO Lines 4 Diode 5 Interrupts ible Timer! 3.8 MINIMUM MCS-85™ SYSTEM 1+5 Power Supply 1 Programmable Timer ‘The Schematics of Figure 3.6 depict a minimum eee ee system core. In actual use, some of the pro- cessor control signals (TRAP, INTR, and HOLD) 1 Power-on Reset would have to be terminated. Also, interface By looking at the printed circuit layout of Figure logic to external devices as well as more 3.7, we can see that not only are there just 31Cs, memory and V/O devices may be desirable. The but that the interconnection of these parts is first thing one notices about the system in extremely easy and provides a very dense Figure 3.6 is the scarcity of parts required to layout. Expecially notice the easy flow of the build this system. With a minimum of parts, we ‘system bus on the solder side of the board. eon aban / od i ay won Jou soe I. sas eerie fe a ies : foe r rt ~ ——— pd FIGURE 3-5 STANDARD MEMORIES WITH LATCHED ADDRESS AND DECODED CHIP SELECTS a7SYSTEM OPERATION sawn ner rare ropes} 040, FIGURE 3-6 MINIMUM 8085 SYSTEM 38Cbeeeeeeeeenge Ss | | \ i CORED RRR Ree Eee eege evoac coe ees Ns 7SYSTEM OPERATION < ara loro MOGI area sssmsa pnoaiee ion petro aS 7SbA Ca Ro Fore ro] Tone e poy ce FIGURE 3-8 EXPANDED SYSTEM‘SYSTEM OPERATION 3.9 EXPANDED MCS-85™ SYSTEM Figure 3.8 shows the circuit Figure 3.6 ex- panded to its maximum size without the use of any extra logic. In an extremely small board area we can fit: PARTS FUNCTION 180854 1 CPU (Clock cycle 3 8355/8750 < 320ns) 28156 ROM/EPROM 1 Crystal 6144 Bytes 4 Resistors 512 Bytes RAM 1 Capacitor 76 1/0 Lines 1 Diode 5 Interrupts 2 Programmable Timer/Counters 2 Serial VO Lines 1 Crystal and Oscillator 1 Clock 1 Power-on Reset 3.10 MCS-85™ SYSTEM WITH 8185 The 8185 1K-byte static RAM chip is another multiplexed-bus component that insures that the most highly integrated systems can be built with MCS-85 components. Figure 3.9 shows a 4-chip MCS-85 system schematic with the following characteristics: PARTS FUNCTION 18085A 4.CPU 18185 ROM/EPROM 18156 2048 Bytes 1 8355/8755A, 1280 Bytes RAM 38 1/0 Lines 5 Interrupts 1 Timer/Counter 2 Serial 1/0 Lines The 8185 also_has power-down capability. By connecting CE; to 10/M from the 80B5A the 8185 will be powered down during 1/0 operations and Interrupt Acknowledge cycles. an ‘asp SER ae wo wom nev ax t som ret | Hose K=> make VVAT . FIGURE 3-9 MCS-85 SYSTEM WITH 8185,Functional Description 4CHAPTER 4 THE 8080 CENTRAL PROCESSOR UNIT ‘The 8080s @ complete S-bit parallel, central procestor unit (CPU) for use in general purpose digital computer sys tems. It is fabricated on a single LSI chip (see Figure 1-1). Using Intel's n-channel silicon gate MOS process, The 8080 transfers data and internal state information via an Bbit, bidirectional 3-state Data Bus (Dg:D7]. Memory and peri Dheral device addresses ae transmitted over a separate 16 bit d-state Address Bus (Ag‘A16). Six timing and control outputs (SYNC, DBIN, WAIT, WR, HLDA and INTE) eman- ‘ate from the 8080, while four control inputs (READY, HOLD, INT and RESET), four power inputs (+12v, +5¥, ‘Sv, and GND) and two clock inputs (1 and 2) are ac cepted by the 8080. Figure 4-1. 8080 Photomicrograph With Pin Designations a4ARCHITECTURE OF THE 8080 CPU ‘The 8080 CPU consists of the following functional units Register array and address logic Arithmetic and fogie unit (ALU) Instruction register and contro! section Bi-directional, 3-state data bus butfer Figure 4-2 illustrates the functional blocks withia ‘the 8080 CPU. Registers: ‘The register section consists of a static RAM array organized into six 16-bit registers: '* Program counter (PC) ‘Stack pointer (SP) «Six B-bit general purpose registers arranged in pairs, ‘The program counter maintains the memory address lf the next program instruction and is incremented auto ‘matically during every instruction fetch. The stack pointer ‘maintains the address of the next avilable stack location in memory. The stack pointer can be initialized to use any portion of read-write memory as a stack. The stack pointer is decremented when data is “pushed” onto the stack and incremented when data is “popped” off the stack (Le., the stack grows “downward”. “The six general purpose registers can be used either as. single registers (Bit) or as register pairs (16-bit). The ‘temporary register pair, W,Z, is not program addressable and is only used for the internal execution of instructions. Eightbit data bytes can be transferred between the internal bus and the register array via the register-select ‘multiplexer. Sixteer-bit transfers ean proceed between the register array and the address latch or the incrementer/ decrementer circu, The address latch receives data from any of the four register pairs and drives the 16 address output buffers (Ag-A15), 9s well as the inccementer/ decrementer circuit, The incrementer/decrementer circuit receives data from the address latch and sends it 10 the register array. The 16:bit data can be incremented or decremented or simply transferred between registers. I on Te we HOLD HOLOMA e[ te a sootiatbus Figure 4-2, 8080 CPU Functional Block DiagramArithmetic and Logic Unit (ALU! ‘The ALU contains the following registers: + An Bbit accumulator ‘s An Bit temporary accumulator (ACT) +A Bait flag register: carry zer0, carry, sign, parity and + An 8.bit temporary register (TMP) Arithmetic, logical and rotate operations are per- formed in the ALU. The ALU is fed by the temporary register (TMP) and the temporary accumulator (ACT) and carry flipfiop. The result of the operation can be trans- ferred to the internal bus or to the accumulator; the ALU also feeds the flag regi ‘The temporary register (TMP) receives information from the internal bus and can send all or portions of it to the ALU, the flag register and the internal bus “The accumulator (ACC) can be loaded from the ALU. land the internal bus and can transfer data to the temporary ‘accumulator (ACT) and the internal bus. The contents of the accumulator (ACC) and the auxiliary cerry flip-lop can ‘be tested for decimal correction during the execution of the DAA instruction (see Section 5). Instruction Register and Control: During an instruction fetch, the frst byte of an in struction (containing the OP code) is transferred from the internal bus to the bit instruction register ‘The contents of the instruction register are, in turn, available to the instruction decoder. The output of the decoder, combined with various timing signals, provides ‘the control signals for the register array, ALU and data buffer blocks. In addition, the outputs from the instruction decoder and external control signals foed the timing and state control section which generates the state and cycle timing signals Data Bus Buffer: This bit bidirectional 3-ttate buffer is used to isolate the CPU's internal bus from the external data bus (Op through 07). In the output mode, the internal bus ‘content is loaded into an B-it latch that, in turn, dives the data bus output butters, The output butfers are switched ‘off during input or non-tansfer operations During the input mode, data from the external data bus is transferred to the internal bus. The internal bus is pr ‘charged at the beginning of each internal state, except for the transfer state (TW and T3-described later in this chapter), 43 ‘THE PROCESSOR CYCLE ‘An instruction eyele is defined as the time required to fetch and execute an instruction, During the fetch, 3 selected instruction (one, two or three bytes) is extracted from memory and deposited in the CPU's instruction regis: ter. During the execution phase, the instruction is decoded and translated into specific processing activities. Every instruction cycle consists of one, two, three, four o five machine cycles. A machine eycle is required ach time the CPU accesses memory or an 1/0 port. The fetch portion of an instruction cycle requires one machine cycle for each byte to be fetched. The duration of the execu ton portion of the instruction eycle depends on the kind of instruction that has been fetched. Some instructions do ‘not require any machine cycles other than those necessary to fetch the instruction; other instructions, however, re- ‘uire additional machine cycles to write or read data to/ from memory or HO devices, The DAD instruction is an ‘exception in that it requires two additional machine eycies +0 complete an internal register-psir add_(s00 Section 6) Each machine cycle consists of three, four or five states, A state isthe smallest unit of processing activity and: is defined as the interval between two successive positive: ‘going transitions of the $1 driven clock pulse. The 8080 isdriven by a two-phase clock oscillator. All processing activ- ities are referred to the period of this clock. The two non: overlapping clock pulses, labeled $+ and 62, are furnished by external circuitry. It is the $1 clock pulse which divides teach machine cycle Into states. Timing logic within the ‘8080 uses the clock inputs to produce a SYNC pulse, Which identifies the beginning of every machine cycle. The SYNC pulse is triggered by the low-tochigh transition of 6, as shown in Figure 4:3. Pel ee Hin ee IS) er Bet te eg eee ett “SYNC DOES NOT OCCUR IN THE SECOND AND THIRD MACHINE GvCLESOF A DAO INSTRUCTION SINE THESE MACHINE CYCLES [AREUSEO FOR AN INTERNAL REGISTER-PAIR ADD. Figure 4-3. 6, 62 and SYNC Timing ‘There are three exceptions to the defined duration of 2 state, They are the WAIT state, the hold (HLDA) state and the halt (HLTA) state, described later in this chapter Because the WAIT, the HLDA, and the HLTA states depend upon external events, they are by their nature of indeter inate length, Even these exceptional states, however, mustbe synchronized with the pulses of the driving clock. Thus, the duration of all states are integral multiples of the clock period. To summarize then, each clock period marks a state; three to five states constitute # machine cycle; and one to five machine cycles comprise an instruction eyele. A full instruction cycle requires anywhere from four to eight: teon states for its completion, depending on the kind of in- struction involved, Machine Cycle Identification: With the exception of the DAD instruction, there is just one consideration that determines how many machine cycles are required in any given instruction eyele: the aum- ber of times that the processor must reference a memory address or an addressable peripheral device, in order t0 fetch and execute the instruction. Like many processors, the 8080 is s0 constructed that it can transmit only one address per machine cycle. Thus, ifthe fetch and execution of an instruction requires two memory references, then the instruction cycle associated with that instruction consists of ‘two machine cycles. If five such references are ealed for then the instruction cycle contains five machine cycles, Every instruction eycle has at least one reference to memory, during which the instruction is fetched, An in struction cycle must always have a fetch, even if the execu tion of the instruction requires no further references 10 ‘memory. The first machine cycle in every instruction cycle is therefore @ FETCH. Beyond that, there are no fast rules. It depends on the kind of instruction that i fetched, Consider some examples. The add-register (ADD +) instruction is an instruction that requires only a singl ‘machine cycle (FETCH} for its completion. In this one-byte instruction, the contents of one of the CPU's six general purpose registers is added to the existing contents of the accumulator. Since all the information necessary to execute the command is contained in the eight bits of the instruction ‘code, only one memory reference is necessary. Three states are sed to extract the instruction from memory, and one ‘additional state is used to accomplish the desiced addition. ‘The entire instruction cycle thus requires only one machine cycle that consists of four states, or four periods of the ex ternal clock: Suppose now, however, that we wish to add the con: tents of a specifie memory location to the existing contents of the accumulator (ADD M). Although ths is quite simil in principle to the example just cited, several additional steps will be used. An extra machine cycle will be used, in order to address the desired memory location, ‘The actual sequence is as follows. First the processor ‘extracts from memory the one-byte instruction word ad dressed by its program counter. This takes three states. ‘The eight-it instruction word obtained during the FETCH machine cycle is deposited in the CPU's instruction register and used to direct activities during the remainder of the instruction eycle, Next, the processor sendsout,asan address, the contents of its H and L registers. The eight-bit data ‘word returned during this MEMORY READ machine cyc! is placed in a temporary register inside the 8080 CPU. By row three more clock periods (states) have elapsed. In the seventh and final state, the contents of the temporary regit- {er are added t0 those of the accumulator. Two machine cycles, consisting of seven states in all, complete the “ADD M"” instruction eycle. [At the opposite extreme is the save H and L registers (SHLD) instruction, which requires five machine cycles. During an "SHLD" instruction cycle, the contents of the processor's H and L registers are deposited in two sequen: tially adjacent memory locations; the destination is indi cated by two address bytes which are stored in the two ‘memory locations immediately following the operation code byte. The following sequence of events occurs: (1) A FETCH machine cycle, consisting of four states. During the first three states of this ‘machine eycle, the processor fetches the instruc- tion indicated by its program counter. The pro- ‘gram counter is then incremented. The fourth state is. used for internal instruction decoding. (2) A MEMORY READ machine cycle, consisting of three states, During this machine cycle, the byte indicated by the program counter is read from memory and placed in the processor's Z register, The program counter is incremented 9 (3) Another MEMORY READ machine eycle, con sisting of three states, in which the byte indica ted by the processor's program counter is read from memory and placed in the W register, The rogram counter is incremented, in anticipation (of the next instruction fetch (4) A MEMORY WRITE machine cycle, of three states, in which the contents of the L. register are transferred to the memory location pointed 10 by the present contents of the W and Z regis: ters. The state following the transfer is used to increment the W.Z register pair so that it ind cates the next memory location to receive data (5) A MEMORY WRITE machine cycle, of three states, in which the contents of the H register are tansfarred to the new memory. location Pointed to by the W,Z register pair In summary, the “SHLD” instruction eycle contains five machine cycles and takes 16 states to execute, Most instructions fall somewhere between the ex tremes typified by the “ADD *” and the “SHLD” instrue- tions, The input (IN) and the output (OUT) instructions, for example, require three machine cycles: 2 FETCH, 10 ‘obtain the instruction; a MEMORY READ, to obtain the address of the object peripheral; and an INPUT or an OUT: PUT machine eycle, to complete the transferWhile no one instruction cycle will consist of more then five machine cycles, the following ten different types ‘of machine cycles may occur within an instruction cycle (1) FETCH (Mn) (2) MEMORY READ (3) MEMORY WaITE (4) STACK READ (5) STACK WRITE (6) INPUT. (7) ourPuT (8) INTERRUPT (9) HALT (10) HALT* INTERRUPT ‘The machine cycles that actually do occur in a par ticular instruction cycle depend upon the kind of instruc: tion, with the overriding stipulation that the first machine cycle in any instruction cycle is always a FETCH. ‘The processor identifies the machine cycle in prog ress by transmitting an eight-bit status word during the frst state of every machine cycle, Updated status information is presented on the 8080's data lines (09:07), curing the SYNC interval. This data should be saved in latches, and used to develop control signals for external circuitry. Table 4-1 shows how the positive-true status information is dis tributed on the processor's data bus. ‘Status signals are provided principally for the control of external circuitry, Simplicity of interface, rather than machine eycle identification, dictates the logical definition ‘of individual status bits. You will therefore observe that certain procestor machine cycles are uniquely identified by a single status bit, but that others are not, The My status bit (D5), for example, unambiguously identifies a FETCH machine cycle. A STACK READ, on the other hand, is indicated by the coincidence of STACK and MEMR sig als, Machine eycle identification data is also valuable in the test and de-bugging phases of system development, Table 4-1 lists the status bit outputs for each type of ‘machine cycle ‘State Transition Sequence: Every machine cyele within an instruction eycle con sists of three to six active states (referred to as Ty, T2, Ta, ‘Ta, Ts of Tw). The actual number of states depends upon ‘the instruction being executed, and on the particular ma chine cycle within the greater instruction cycle. The state transition diagram in Figure 44 shows how the 8080 pro: ceeds from state to state in the course of a machine cycle ‘The diagram also shows how the READY, HOLD, and INTERRUPT tines are sampled during the machine cycle, fand how the conditions on these lines may modify the 45 basic transition sequence, In the present discussion, we are concerned only with the basic sequence and with the READY function, The HOLD and INTERRUPT functions willbe discussed later. ‘The 8080 CPU does not directly indicate its internal state by transmitting a “state control” output during each state; instead, the 8080 supplies direct control output (INTE, HLDA, DBIN, WR and WAIT) for use by external circuitry, Recall that the 8080 passes through at least three states in every machine cycle, with each state defined by successive low-toshigh tvansitions of the $1 clock. Figure 45 shows the timing relationships in a typical FETCH machine cycle, Events that occur in each state are referenced to transitions of the 1 and 42 clock pulses The SYNC signal identities the first state (T4) in every machine cycle. As shown in Figure 45, the SYNC. signal i related to the leading edge of the #2 clock. There is, ‘a delay (tC) between the low-to-high transition of g and the positive going edge of the SYNC pulte. There also is a corresponding delay (also toc) between the next 42 pulse and the falling edge of the SYNC signal, Status information js displayed on DoD? during the same $2 to $2 interval Switching of the status signals is likewise controlled by 62- ‘The rising edge of $2 during T1 also loads the pro: cessor’s address lines (AQ-A15), These lines become stable within @ brief delay (tp) of the $2 clocking pulse, and they remain stable until the first g pulse after state T3. This gives the processor ample time to read the data re turned from memory. Once the processor has sent an address to memory, there is an opportunity for the memory to request a WAIT. ‘This it does by pulling the processor's READY ine low, prior to the “Ready setup” interval (tag) which occurs during the 6 pulse within state T2 or Tw. As long as the READY line remains low, the procesior will idle, giving the memory time to respond to the addressed date request. Refer to Figure 45, ‘The processor responds to @ wait request by entering ‘an alternative state (Tw) at the end of T, rather than pro- ceeding ditectly to the T3 state. Entry into the Twy state is indicated by a WAIT signal from the processor, acknowledg- ing the memory’s request. A low-tochigh transition on the WAIT line is triggered by the rising edge of the 61 clock and jccurs within a brief delay (pc) of the actual entry into the Tw state ‘A wait period may be of indefinite duration. The pro- cessor remains in the waiting condition until its READY line again goes high, A READY indication must precede the fall ing edge of the ¢2 clock by a specified interval (tag), in order to guarantee an exit from the Tyy state, The cycle ‘may then proceed, beginning with the rising edge of the next 61 clack. A WAIT interval will therefore consist of an integral number of Ty states and will always be a multiple of the clock period,Instructions for the 8080 require tram one to five machine cycles for complete execution. The 8080 tends out 8 bit of Status information onthe data bus at the beginning ofeach ‘machine evel during SYNC time). The fallowing table deines {the status information, STATUS INFORMATION DEFINITION Date Bue Symbols Intat Detinition ‘Acknowledge signal for INTERRUPT re- ‘quest. Signal should be used to gate are Stor instuetion onto the data bus when DEIN i active. Indieates thatthe operation in the curent machine cycle will bee WRITE memory ‘SeOUTPUT function (HO = 0} Otherwise, SREAD memory or INPUT operation wil be executed Indicates that the address bus holds the pushdown stack address from the Stack Painter. ‘Acknowledge signal for HALT instruction. Indieates thatthe adress contains the adress of an output vice and the data bus wil contain the output data when WR active Provides a signal to indieate thatthe CPU. fein the feteneyele for the first byte of Inieatasthat the addrossbus contains the tress of an input devee and the input tate should be placed on the data bus vinen DBIN is sctve. Dzsgnates thatthe dota bus wil be used formemory reed data Po wo o STACK HLTA our Ine Og MER" 0; STATUS WORD CHART somo STATUS LATCH ‘TYPE OF macwine cvcte {-@ staruswono [tT @t@t @O[Ol@ Do| wa {oto vfot1 | a a tt1 tt De | stack | 0 | 0 ofo}o Ds | HLTA | 0 oj1]t De{ our | 0 ojolo Ds | M 1 tpe|4 De| ine | 0 olofo Dr | MEM | 1 oj1fo Table 4-1. 8080 Status Bit Definitions 46‘The events that take place during the T state are determined by the kind of machine cyele in progress, In a FETCH machine cycle, the processor interprets the dats on its data bus as an instruction. During a MEMORY READ or @ STACK READ, data on this bus is interpreted as a dat word. The processor outputs data on this bus during 3 MEMORY WRITE machine eycle. During 1/0 operations, the procestor may either transmit or receive data, de pending on whether an OUTPUT or an INPUT operation is involv Figure 4-7 illustrates the timing that is characteristic (of @ data input operation, As shown, the low-to-high transi tion of $2 during T2 clears status information from the peo- cessor's data lines, preparing these lines for the receipt of incoming data, The data presented to the processor must have stabilized prior to both the “G1—data set-up" interval (tpt), that precedes the falling edge of the $1 pulse defin ing state T3, and the “62-data set-up" interval (tpga), that precedes the rising edge of 2 in state T3. This same CPU's data During the input of data to the processor, the 8080 ‘generates a DBIN signal which should be used externally to enable the transfer. Machine cycles in which DBIN is vail- ‘able include; FETCH, MEMORY READ, STACK READ, and INTERRUPT. DBIN is initiated by the rising edee of 62 ‘during state T2 and terminated by the corresponding edge of 62 during T3, Any Tw phases intervening between T2 and Tg will therefore extend DBIN by one or more clock periods. Figure 4.7 shows the timing of a machine cycle in Which the processor outputs data, Qutput data may be des- tined either for memory o* for peripher fof #2 within state T clears status information from the 3, and loads in the date which isto be output to external devices. This substitution takes place within the data must remain stable during the “data hold” interval (tH) that occurs following the rising edge of the g pulse. Data placed on these lines by memory or by other external devices will be sampled during 73, NOTE: @ Reterto Statue Word Chart on Faye 46. Figure 4-5, Basic 8080 Instruction Cycle 48 Is. The rising edgea [= = % i a a “+t i To oevier veer =P ee Tee 23 —— wie | fo TTT XO ® WoTE: @ Reter to Status Word Chart on Pape 4-6, Figure 4-6. Input Instruction Cycle «LALALA Aiea LT tee [fle Tree os) a TX pacar \ owe | TT fea i ay oom iY eae IT i o | S : nL | a ® oe ‘X ® ca Nove: @ Reterto Status Word Chart on Poe 4-6. Figure 4-7. Output Instruction Cycle 49ata output delay” interval (t0D) following the 6 clock’s leading edge. Data on the bus remains stable throughout ‘the remainder of the machine cyee, until replaced by up dated status information inthe subsequent T1 state. Observe that # READY signal is necesary for completion of an OUTPUT machine cycle, Unless such an indication i pres ent, the processor enters the Tw state, following the T2 state. Data on the output lines remains stable in the interim, and. the processing cycle will not proceed until the READY line again goes high ‘The 8080 CPU generates a WR output for the syn chronization of external transfers, during those machine cycles in which the processor outputs data, These include MEMORY WRITE, STACK WRITE, and OUTPUT. The negative going leading edge of WR is referenced tothe rising edge of the first 61 clock pulse following Ta, and occurs Within a briet delay (toc) of that event. WR remains low Until retriggered by the leading edge of $3 during the state following Ta. Note that any Ty states intervening between Tz and 753 ofthe output machine cycle will neces sarily extend WA, in much the same way that DBIN is af- ‘ected during data input operations. All processor machine cycles consist of at least three states: Ty, T, and T3 as just described. Ifthe processor has ‘© wait fo 2 response from the peripheral or memory with which it is communicating, then the machine cycle may also contain one or more Tyy states. During the three basic states, data is transferred to of from the processor. After the T3 state, however, it becomes difficult to ‘generalize. T4 and Tg states are avalable, if the execution of a particular instruction requires them, But not all machine cycles make use of these states. It depends upon the kind of instruction being executed, and on the particular machine cycle within the instruction eycle. The processor will termi: ate any machine cycle as soon as its processing activities are completed, rather than proceeding through the T4 and ‘Tg states every time. Thus the 8080 may exit @ machine cycle following the Tg, the Ta, or the Ts state and pro: ceed directly to the T} state of the next machine cycle. ee STATE ‘ASSOCIATED ACTIVITIES a 7 TW (optional) 13 Ta 15 (optional) "A memory address or 1/0 device number is placed on the Address Bus (Aqs5.0); status information is placed on Data Bus (07.0). “The CPU samples the READY and HOLD in ‘buts and checks for halt instruction, Procesior enters wait sate if READY is low ‘or if HALT instruction has been executed. ‘An instruction byte (FETCH machine cycle), data byte (MEMORY READ, STACK READ, INPUT) or interrupt instruction (INTERRUPT ‘machine eyele) is input to the CPU from the Data Bus or a data byte (MEMORY WRITE, STACK WRITE or OUTPUT machine cycle) ‘s output onto the data bus, States Ta and Tg ae available if the execu: tion ofa particular instruction requires them; if not, the CPU may skip one or both of them, T4 and Ts are only used for internal processor operations, Table 4-2, State Definitions 4-10INTERRUPT SEQUENCES ‘The 8080 has the built-in capacity to handle external interrupt requests, A peripheral device can initiate an inter rupt simply by driving the processor's interrupt (INT) line high The interrupt (INT) input is asynchronous, and a request may therefore originate at any time during any instruction eycle, lnternal logie re-clocks the external re uest, 50 that @ proper correspondence with the driving clock’ is established. As Figure 4-8 shows, an interrupt Fequest (INT) arriving during the time that the interrupt tenable ine (INTE) is high, acts in coincidence with the clock to set the internal interrupt latch, This event takes Place during the last state of the instruction eyele in which the request occurs, thus ensuring that any instruction in Progress is completed before the interrupt can be processed. The INTERRUPT machine cycle which follows the arrival of an enabled interrupt request resembles an ordinary FETCH machine cycle in most respects. The My status bit is transmitted os usual during the SYNC interval. It is accompanied, however, by an INTA status bit (Do) which acknowledges the external request. The contents of the rogram counter are latched onto the CPU's address lines during T}, but the counter itself isnot incremented during the INTERRUPT machine cycle, as it otherwise would be, In this way, the presinterrupt status of the program counter is preserved, so that data in the counter may be restored by ‘the interrupted program after the interrupt request has been processed ‘The interrupt eycle is otherwise indistinguishable from. an ordinary FETCH machine cycle, The processor itself takes no further special action. It isthe responsibilty of the peripheral logic to see that an eight-bit interrupt instruction {s "jammed" onto the processor's data bus during state T3. In a typical system, this means that the data-in bus from memory must be temporarily disconnected from the pro- ‘essor's main data bus, so that the interrupting device can ‘command the main bus without interference, ‘The 8080's instruction set provides a special one-byte call which facilitates the processing of interrupts (the ordi- nary program Call takes three bytes). This is the RESTART instruction (RST). A variable three-bit field embedded in ‘the eight-bit field of the RST enables the interrupting device to direct a Call to one of eight fixed memory locations, The decimal addresses of these dedicated locations are: 0, 8, 16, 24, 32, 40, 48, and 56. Any of these addresses may be used {to store the first instruction(s) of a routine designed to service the requirements of an interrupting device, Since the (RST) is call, completion of the instruction also stores the old program counter contents on the STACK, = = oh rp n rh »Lim TLALALALALALnLaLaLn! ane | res % raya ez oa 7 Fe Tr eT sme J t PLL ein ITN co LIT smn Ls qt | | ee | 2 | an sence L B8anon ms i | nore: ® to Status Word Chart on Pape 4-6, Figure 4-8. Interrupt TimingTERNAL | see arracneo ettcrnicas cnaRAcTERITIS Figure 4-8. HOLD Operation (Read Mode} et vow | / Figure 4-10. HOLD Operation (Write Mode)HOLD SEQUENCES ‘The 8080A CPU contains provisions for Direct Mem ‘ory Access (DMA) operations. By applying a HOLD to the appropriate control pin on the processor, an external device can cause the CPU to suspend its normal operations and re- linguish control of the address and data busses. The proces: sor responds to a request ofthis kind by floating its address to other devices sharing the busses. At the same time, the ‘rovessor acknowledges the HOLD by placing a high on its HLDA outpin pin. During an acknowledged HOLD, the address and data busses are under control of the peripheral which originated the request, enabling it to conduct mem. ‘ory transfers without processor intervention. Like the interrupt, the HOLD input it synchronized internally. A HOLD signal must be stable prior to the "Hold set-up" interval (ts), that precedes the rising edge of 2. Figures 49 and 4-10 illustrate the timing involved in HOLD operations, Note the delay between the asynchronous HOLD REQUEST and the re-clocked HOLD. As shown in ‘the diagram, a coincidence of the READY, the HOLD, and the $2 clocks sets the internal hold latch, Setting the latch ‘enables the subsequent rising edge of the $1 clock pulse to trigger the HLDA output as described below. Acknowledgement of the HOLD REQUEST precedes slightly the actual floating of the processor's address and data lines, The processor acknowledges a HOLD at the begin ning of T3, if a read or an input machine cycle is in progress (see Figure 4.9). Otherwise, acknowledgement is deferred Until the beginning of the state following 3 (see Figure 4-10), In both cases, however, the HLDA goes high within 28 specified delay (tp) of the rising edge of the selected 6 clock pulse, Address and data lines are floated within brief delay after the rising edge of the next 62 clock pulse “This relationship is also shown in the diagrams. Toall outward appearances, the processor has suspend: ced its operations once the address and data busses are floated, Internally, however, certain functions may continue. If 3 HOLD REQUEST is acknowledged st T3, and if the pro: ‘cessor is in the middle of @ machine eycle which requires {our or more states to complete, the CPU proceeds through Ta and Ts before coming to a rest, Not until the end af the machine cycle is reached will processing activities cease, Internal processing is thus permitted to overlap the external DMA transfer, improving both the efficiency and the speed of the entire system. ‘The processor exits the holding state through 2 sequence similar to that by which it entered. A HOLD, REQUEST is terminated asynchronously when the external device has completed its data transfer. The HLDA output returns to 9 low level following the leading edge of the next 61 clock pulse, Normal processing resumes with the ma: chine cycle following the last cycle that was executed. HALT SEQUENCES When a halt instruction (HLT) is executed, the CPU enters the halt state (Typ) after state Ta of the next me chine eycle, as shown in Figure 4-11, There are only three ways in which the 8080 can exit the halt state ‘+ A high on the RESET tine will always reset the 8080 to state T4; RESET also clears the program counter, AHOLD input will cause the 8080 to enter the hold state, as previously described, When the HOLD ine goes low, the 8080 re-enters the halt state on the rising edge of the next 1 clock pulse An interrupt (ie., INT goes high while INTE is enabled) will cause the 8080 to exit the Halt state ‘and enter state Ty on the rising edge of the next 1 clock pulse. NOTE: The interrupt enable (INTE) flag must be set when the halt state is entered ‘otherwise, the 8080 will only be able to exit viaa RESET signal Figure 4-12 illustrates halt sequencing in flow chart form. START-UP OF THE 8080 CPU When power is applied initially to the 8080, the pro- cessor begins opersting immediately. The contents of its program counter, stack pointer, and the other working regis ters are naturally subject to random factors and cannot be specified. For this reason, it will be necessary to begin the power-up sequence with RESET. ‘An external RESET signal of three clock period dura tion (minimum) restores the processors internal program counter to 200, Program execution thus begins with mem: ory location zero, following 2 RESET. Systems which re quire the processor to wait for an explicit startup signal will store a halt instruction (EI, HLT) in the first two loca- tions, A manual or an automatic INTERRUPT will be used for starting. In other systems, the processor may begin ex ecuting its stored program immediately. Note, however, that the RESET has no effect on status flags, or on any of the processor's working registers (accumulator, registers, oF stack pointer). The contents of these registers remain inde ‘terminate, until initialized explicitly by the program,| wa | | oO @ tontarion efor to Status Word Chert on Pape 4-5 Figure 4-11. HALT Timing us Figure 4.12, HALT Sequence Flow Chartror | es t rH | {| | 1 | Bee | | Ke NAT eee | sore: © Rete to Status Word Chart on Pi Figure 4-13, Reset oT aged gee igre eee eae ccas ie ern eee Benes © fae o aE |_| | [ sore © eter to Sat Word Charon Pape #6. Figure 4-14. Relation between HOLD and INT in the HALT State(07040504 [93020109 | 1 | eae eee LAK pial sane [rete sane eee your +t een ‘Aber voeo lisse eee 4 - =a wer pees |fvese? | | | | qt re teet | ‘aracr Se[teal270% | P2020 | | va |r «| [ne 2 a0 e+ 10 Pregue | cemreca[insrarran | canacr eur | Penres ot lew Te aracr ee ara fern = rept anne a Terr perte ies wnaer Bie Dara ferie a = Pe Cd ie Teri piiie ‘arene Bake ara fora Spee | araer Ee ome DO T Sante, ner rs Peer pervert aafo mae [tee pores Fa or Tera ee Fou BRC oe Tar jeer [reales ® Eee wre [aia poo 1 ¥ Bt aa Tetepeer T ¥ Eilon Weer Tere] * Ee a t * = Taper T serineRexvuse | Ste ‘Sarva! Rratuste | Se AoNoTEs: 1._The first memory cycle (M1) is always an instruction fetch; the first (or only) byte, containing the op code, is fetched during this eye. 2. Ifthe READY input from memory is not high during T2of each memory cycle, the processor will enter a wait state (TW) until READY is sampled as high. 3. States Té and TS are present, as required, for opera: tions which are completely internat to the CPU. The con- tents of the internal bus during T4 and TS are available at ‘the data bus; this is designed for testing purposes only. An “X" denotes that the state is present, but is only used for such internal operations as instruction decoding, 4. Only register pars rp = B (registers B and C) or rp= D. (registers D and E) may be specified. 5, These states are skipped, 6. Memory read sub-eycles; an instruction or data word will be read. 7. Memory write sub-cyele. 8 The READY signal is not required during the second ‘and third sub-cycles (M2.and M3). The HOLD signal is ‘accepted during M2 and M3, The SYNC signal is not gene ‘ated during M2 and M3. During the execution of DAD, M2 and M3 are required for an internal ragistr-pair add memory is not referenced. 9. The results of these arithmetic, logical or rotate io- structions are not moved into the accumulator (A) untit state T20f the next instruction cycle. That is, A is loaded ‘while the next instruction is being fetched; this overlapping of operations allows for faster processing. 10. If the value of the least significant 4bits of the accumu: lator is greater than 9 or if the auxiliary carry bit is set, 6 is added to the accumulator. Ifthe value of the most signifi- cant bits of the accumulator is now greater than 8, oF if the carry bit is set, 6 is added to the most significant 4-bits of the accumulator. 11. This represents the first sub-cycle (the instruction fetch) of the next instruction eycle. 12. Ifthe condition was met, the contents of the register pair WZ are output on the address lines (Aq) instead of ‘the contents of the program counter (PC). 13, Ifthe condition was not met, sub-oycles M4 and MB are skipped: the processor instead proceeds immediately to the instruction fetch (Mt) of the next instruction cycle, 14, If the condition was not met, sub-eycles M2 and M3 are skipped; the processor instead proceeds immediately to the instruction fetch (Mt) of the next instruction eycle. 15. Stack read subscyele 16. Stack write sub-cycte. 17. CONDITION coc NZ ~ not zero (20) 000 2 ~ 2010 (Z= 1) 001 NC — no earry (CY = 0) o10 = carry (CY=1) on PO — parity odd (P= 0) 100 PE — parity even (P= 1) 101 P — plus (S= 0} 110 M = minus (S= 1) am 18. 1/0 sub-cycle: the 1/0 port's @bit select code is dupli- ‘ated on address lines 0-7 (Ag7) and 8-16 (Ags. 19. Output sub-eyele. 20. The processor will remain idle in the halt state until an interrupt, a reset or a hold is accepted. When a hold re- {uest is accepted, the CPU enters the hold mode; after the hhold mode is terminated, the processor returns to the halt state. After a reset is accepted, the processor begins execu tion at memory location zero. After an interrupt i accepted, the processor executes the instruction forced onto the data bus (usualy a restart instruction) Value — iT 00 |p} or pots fas] 030] oe on} 100 tot [$852 005 4-20Instruction Set z 5CHAPTER 5 THE INSTRUCTION SET 5.1 WHAT THE INSTRUCTION SET IS DDD,sss The bit pattern designating ‘A computer, no matter how sophisticated, can eee easier ABO. do only what itis instructed to do. A program Is eae aoe " a sequence of instructions, each of which is 7 a recognized by the computer and causes it to DDD or REGISTER perform an operation. Once a program is placed sss NAME in memory space that is accessible to your 44 A CPU, you may run that same sequence of in- 000 8 structions as often as you wish to solve the 001 c same problem or to do the same function. The O10 D set of instructions to which the 8085A CPU will O11 E respond Is permanently fixed in the design of 400 4 the chip. 401 L Each computer instruction allows you to 7 ‘one of the register pairs: tiate the performance of a specific operation. ; The 8085A implements a group of instructions B represents the 8,C pair with that move data between registers, between a B as the high-order register register and memory, and between a register and © as the low-order and an 1/0 port. It also has arithmetic and logic register, instructions, conditional and unconditional D represents the D,E pair with branch instructions, and machine control in- D as the high-order register structions. The CPU recognizes these instruc- and E as the low-order tions only when they are coded in binary form. register; H represents the H,L pair with H as the high-order register 5.2 SYMBOLS AND ABBREVIATIONS: peter eee The following symbols and abbreviations are aa SP represents the 16-bit stack used in the subsequent description of the 80854 instructions: Pointer register. RP The bit pattern designating eee a mennine one of the register pairs accumulator Register A B,D,H,SP: addr 16-bit address quantity RP REGISTER data >it quantity an Guise Tso on causadani 4 Be byte 2 The second byte of the instruc- 10 HL tion n SP byte 3 The third byte of the instruc: rh The first (high-order) register tion of a designated register pair. port Bit address of an WO device The second (low-order) nye One of the registers A,B,C, register of a designated D.EH,L register pair. “Al mnemonics copyrighted © intel Corporation 1978. caTHE INSTRUCTION SET PC 16-bit program counter register (PCH and PCL are used to refer to the high-order and low-order 8 bits respec- tively). sP 16-bit stack pointer register (SPH and SPL are used to refer to the high-order and low-order 8 bits respectively). im Bit m of the register r (bits are number 7 through 0 from left to right). LABEL 16-bit address of subroutine. The condition flags: 2 Zero s Sign Pe Parity cy Carry AC Auxiliary Carry 0 The contents of the memory location or registers enclosed in the parentheses. - “Is transferred to’ n Logical AND w Exclusive OR A Inclusive OR + Addition - Two's complement subtraction : Multiplication “Is exchanged with” The one’s complement(e.g.,(A)) n The restart number 0 through 7 The binary representation 000 through 111 for restart number 0 through 7 respectively. The instruction set encyclopedia is a detailed description of the 8085A instruction set. Each instruction is described in the following man- ner: 1. The MCS-85 macro assembler format, con- 19 of the instruction mnemonic and operand fields, is printed in BOLDFACE on the first line. 2. The name of the instruction is enclosed in parentheses following the mnemonic. 3. The next lines contain a symbolic description of what the instruction does. 4. This is followed by a narrative description of the operation of the instruction. “All mnemonics copyrighted ©intel Corporation 1976. 52 5. The boxes describe the binary codes that ‘comprise the machine instruction. 6. The last four lines contain information about the execution of the instruction. The number, of machine cycles and states required to ex- ecute the instruction are listed first. If the in- struction has two possible execution times, as in a conditional jump, both times are listed, separated by a slash. Next, data ad- dressing modes are listed if applicable. The last line lists any of the five flags that are af- fected by the execution of the instruction. 5.3 INSTRUCTION AND DATA FORMATS. Memory used in the MCS-85 system is organ- ized in Bit bytes. Each byte has a unique location in physical memory. That location is described by one of a sequence of 16-bit binary addresses, The 8065A can address up to 64K (K = 1024, or 210; hence, 64K represents the decimal number 65,536) bytes of ‘memory, which may consist of both randomraccess, read-write memory (RAM) and read-only memory (ROM), which is also random-access. Data in the 80854 is stored in the form of B-bit binary integers: DATAWORD eee eee Dr Dg Ds Dy Dy Dz Dy Do MSB LSB When a register or data word contains a binary number, itis necessary to establish the order in which the bits of the number are written. In the intel 8085A, BIT Ois referred to as the Least nt Bit (LSB), and BIT 7 (of an 8-bit number) is referred to as the Most Significant Bit (MSB). ‘An 8085A program instruction may be one, two or three bytes in length. Multiple-byte instructions must be stored in successive memiory locations; the address ofthe first byte is always used as the address of the in- struction. The exact instruction format will depend ‘on the particular operation to be executed. ‘Single Byte Instructions Meena lecaeeleelnel D, Dp} Op Code ‘Two-Byte Instructions Byte ‘one [D7 Op Code pyte[>T 71 TTT Two Data or AddressTHE INSTRUCTION SET Three-Byte Instructions Byte(—T TT 1 111 One o Dp] Op Code Byte eclaatreel alee lealiet Two [D7 Do}) Data or Byte [TT TT TTT} Address Three [57 Do 5.4 ADDRESSING MODES: Often the data that is to be operated on is stored in memory. When mult-byte numeric data is used, the data, lke instructions, is stored in successive memory locations, with the least significant byte first, follow- ed by increasingly significant bytes. The 8085A has four different modes for addressing data stored in memory or in registers: * Direct — Bytes 2 and 3 of the instruction contain the exact memory ad- dress of the data item (the low- order bits of the address are in byte 2, the high-order bits in byte 3). * Register — The instruction specities the register or register pair in which the data is located. © Register Indirect — The instruction specifies a register pair which contains the memory address where the data is located (the high-order bits of the address are in the first register of the pair the low-order bits in the second). * Immediate — The instruction contains the data itself. This is either an Sbit quantity or a 16-bit quanti- ty (least significant byte first, most significant byte second). Unless directed by an interrupt or branch in- stitution, the execution of instructions pro- ceeds through consecutively increasing memory locations. A branch instruction can specify the address of the next instruction to be ‘executed in one of two ways: © Direct — The branch instruction contains the address of the next instruc- tion to be executed. (Except for the ‘RST’ instruction, byte 2 contains the low-order address and byte 3 the high-order ad- dress.) “AI mnemonics copyrighted Intel Corporation 1076. 53 * Register Indirect — The branch instruc- tion indicates a register-pair which contains the address of the next instruction to be ex- ‘ecuted. (The high-order bits of the address are in the first register of the pair, the low- order bits in the second.) The RST instruction is a special one-byte call in- struction (usually used during interrupt se- quences). RST includes a threebit field; pro- gram control is transferred to the instruction whose address is eight times the contents of this three-bit field. 5.5 CONDITION FLAGS: There are five condition flags associated with the execution of instructions on the 805A. ‘They are Zero, Sign, Parity, Carry, and Auxiliary Carry. Each is represented by a 1-bit register (or flip-flop) in the CPU. A flag is set by forcing the bit to 1; it is reset by forcing the bit to 0. Unless indicated otherwise, when an instruc- tion affects a flag, it affects it in the following manner Zero: If the result of an instruction has the value 0, this flag is set; otherwise it is reset. If the most significant bit of the result of the operation has the value 1, this flag is set; other- wise it is reset. If the modulo 2 sum of the bits of the result of the operation is 0, (ie., if the result has even parity), this flag is set; other- wise It is reset (ie., If the result has odd parity). If the instruction resulted in a carry (from addition), or a bor- row (from subtraction of a com- parison) out of the high-order bit, this flag is set; otherwise it is reset. Auxiliary Carry: If the instruction caused a carry out of bit 3 and into bit 4 of the resulting value, the aux- iliary carry is set; otherwise it is reset. This flag is affected by single-precision additions, sub- tractions, increments, decre- ments, comparisons, and logi- cal operations, but is principal- ly used with additions and in- crements preceding a DAA (Decimal Adjust Accumulator) instruction. Sign: Parity: Carry:THE INSTRUCTION SET 5.6 INSTRUCTION SET ENCYCLOPEDIA In the ensuing dozen pages, the complete 80854 instruction set is described, grouped in ‘order under five different functional headings, as follows: 1. Data Transfer Group — Moves data be- tween registers or between memory locations and registers. Includes moves, loads, stores, and exchanges. (See below.) 2. Arithmetic Group — Adds, subtracts, in- crements, or decrements data’ in registers or memory. (See page 5-13.) 3. Logic Group — ANDs, ORs, XORs, com- pares, rotates, or complements data in Tegisters or between memory and a register. (See page 5-16.) 4, Branch Group — Initiates conditional or unconditional jumps, calls, returns, and restarts. (See page §-20.) 5. Stack, VO, and Machine Control Group — Includes instructions for maintaining the stack, reading from input ports, writing to output ports, setting and reading interrupt masks, and setting and clearing flags. (See page 5-22) The formats described in the encyclopedia reflect the assembly language processed by Intel-supplied assembler, used with the Intellec® development systems. 5.6.1. Data Transter Group This group of instructions transfers data to and from registers and memory. Condition flags are not affected by any instruction in this group. MOV r1, 72 (et) — (2) The content of register 12 is moved to register rt. (Move Register) MOVr,M (Move from memory) © (HU) ‘The content of the memory location, whose address is in registers H and L, is moved to register r. none MOV M,r (Move to memory) (H) L) - 0 ‘The content of register r is moved to the memory location whose address is in registers H and L. Tee Teel olitalalols's's 2 7 eg. indirect Flags: none MVIr, data (Move Immediate) (2) — (byte 2) ‘The content of byte 2 of the instruction is moved to register r. T Faecal eran o o/b bd d]1 141 0 data 2 7 Addressing: immediate Flags: none MVIM, data (Move to memory immediate) (GH) (L) — (byte 2) The content of byte 2 of the instruction is moved to the memory location whose ad- dress is in registers H and L. fae eee eerecetreeecer reece eeeeae Diese o'1]o vo vo] s'sis ° eed Olea aca @ 1 data 4 (8085), 5 (8080) Addressing: register 3 Flags: none 40 “Ail mnemonics copyrighted © intel Corporation 1976. 4 immed.Jreg. indirect noneTHE INSTRUCTION SET LX rp, data 16 (Load register pair immediate) (rh) — (byte 3), (cl) — (byte 2) Byte 3 of the instruction is moved into the high-order register (ch) of the register pair rp. Byte 2 of the instruction is moved into the low-order register (rl) of the register pair tp. LHLD addr (Load H and L direct) (L)—((byte 3\byte 2) (H)—(byte 3)(byte 2)+ 1) The content of the memory location, whose address is specified in byte 2 and byte 3 of the instruction, is moved to register L. The content of the memory location at the suc- ceeding address is moved to register H. Ieee [ese deca fear dares acral o o}/R P/O 0 0 14 Tee Vee ee eae. oo 1 0 4 0 4 0 low-order data low-order addr high-order data high-order addr immediate none LDA addr (Load Accumulator direct) (A) — ((byte 3)(oyte 2)) ‘The content of the memory location, whose address Is specified in byte 2 and byte 3 of the instruction, is moved to register A. Taree gaara eee iaseeee lasers ager ON HOH ited ae aeO nid aitHO) low-order addr high-order addr 13 direct none STA addr (Store Accumulator direct) (byte 3)(byte 2) — (A) ‘The content of the accumulator is moved to the memory location whose address is specified in byte 2 and byte 3 of the instruc- tion. Dee ine nego aeaecy Weare eae Ose Oseceetaec eA ete Ota O tad SHLD addr Cycles: 5 16 direct Flags: none (Store H and L direct) (byte 3ybyte 2)—(L) (byte 3(byte 2) + 1)—(H) The content of register L is moved to the memory location whose address is specified in byte 2 and byte 3. The content of register H is moved to the succeeding memory location. gece gece eee ace Pace (Oi HHO Hi a OOH HO uM IHEO: low-order addr high-order addr LDAX mp 16 direct none (Load accumulator indirect) fA) — (rp) ‘The content of the memory location, whose address is in the register pair rp, is moved to register A. Note: only register pairs 'p=B (registers B and C) or rp=D low-order addr (registers D and E) may be specified. T T aeoeePeaect high-order addr. o o}|R P/1 0 1.0 Cycles: 4 Cycles: 2 States: 13 States: 7 Addressing: direct Addressing: reg. indirect Flags: none Flags: none “All mnemonics copyrighted © Intel Corporation 1978. 65THE INSTRUCTION SET STAX rp (Store accumulator indirect) (trp) — (A) The content of register A is moved to the memory location whose address is in the fegister pair rp. Note: only register pairs 1p=B (registers B and C) or rp=D (registers D and E) may be specified. gene Pee eae econ cee ceca o o}rR P]o 0 1 0 Cycles: 2 States: 7 Addressing: reg. indirect Flags: none XCHG (Exchange H and L with D and E) (H) ~ (D) (L) ~ (6) ‘The contents of registers H and L are ex- changed with the contents of registers D and E. 5.6.2 Arithmetic Group This group of instructions performs arithmetic operations on data in registers and memory. Unless indicated otherwise, all instructions in this group affect the Zero, Sign, Parity, Carry, and Auxiliary Carry flags. according to the stan- dard rules. All subtraction operations are performed via two's complement arithmetic and set the carry flag to one to indicate a borrow and clear it to indicate no borrow. ADDr (Add Register) A) ~ (A) +) The content of register r is added to the content of the accumulator. The result is placed in the accumulator. Addressing: register Flags: Z,8,P,CY,AC “AIL mnemonics copyrighted © Intel Corporation 1976. ADD M (Add memory) (A) ~ (A) + (H) (L) The content of the memory location whose address is contained in the H and L registers is added to the content of the ac- cumulator. The result is placed in the ac- cumulator. ADI data (Add immediate) (A) — (A) + (byte 2) The content of the second byte of the in- struction is added to the content of the ac- cumulator. The result is placed in the ac- cumulator. immediate Z,S,P,CY,AC apc r (Add Register with carry) (A) — (A) + () + (CY) The content of register r and the content of the carry bit are added to the content of the accumulator. The result is placed in the ac- cumulator. Cycles: 1 States: 4 ‘Addressing: register Flags: Z,S,P,CY,AC 56THE INSTRUCTION SET ADC M {Add memory with carry) (A) ~ A) + (HH) (L) + (CY) ‘The content of the memory location whose address Is contained in the H and L fegisters and the content of the CY flag are added to the accumulator. The result is placed in the accumulator. SUBM (Subtract memory) ~~ H)() ‘The content of the memory location whose address is contained in the H and L registers is subtracted from the content of the accumulator. The result is placed in the accumulator. Tee eeeeg O aeeee Taree Paseeec area asses eee arse Mage Desaaea 1 0 0 0 4 4°14 °0 a eseed Yossie Jeeten Jerteax' estan eter: eer 2 Gycles: 2 7 States: 7 reg. indirect Addressing: reg. indirect Flags: — Z,S,P,CY,AC Flags: —Z,S,P,CY,AC ACI dat (Add immediate with carry) ‘SUI data (Subtract immediate) (A) — (A) + (byte 2) + (CY) The content of the second byte of the struction and the content of the CY flag are added to the contents of the accumulator. (A) ~ (A) — (byte 2) The content of the second byte of the in- struction is subtracted from the content of the accumulator. The result is placed in the The result is placed in the accumulator. accumulator. Teese decease era M cecal Tec sea sear laa eee ae 1 91°00 4 1 14 0 Vee Oe Ate Ouiyitedcie 0 data data 2 Gycles: 2 7 States: 7 immediate ‘Addressing: immediate ZS,P,CY,AC Flags: Z,8,P,CY,AC SUBr (Subtract Register) W-a-@ ‘The content of register ris subtracted from the content of the accumulator. The result is placed in the accumulator. (Subtract Register with borrow) @ — (CY) it of register r and the content of the CY flag are both subtracted from the accumulator. The result is placed in the ac- cumulator. Tee aoe T Poe T T 1 oO 0 1 oO s s s 1 0 oO 1 1 s s ; Ss : yet 1 4 register Flags: Z,8,P,CY,AC eee: roa A “All mnemonics copyrighted ©lntel Corporation 1976. 87THE INSTRUCTION SET SBBM (Subtract memory with borrow) A) ~ A) ~ (H) (L) - (CY) The content of the memory location whose address is contained in the H and L registers and the content of the CY flag are both subtracted from the accumulator. The result is placed in the accumulator. les: 2 States: 7 Addressing: reg. indirect Flags: —Z,S,P,CY,AC ‘SBI data (Subtract immediate with borrow) (A) — (A) ~ (byte 2) - (CY) The contents of the second byte of the in- struction and the contents of the CY flag are both subtracted from the accumulator. The result is placed in the accumulator. Deer (ree (essa eran reel rereel Sere sO aeeet sect eee ete: data Gycles: 2 States: 7 ‘Addressing: immediate Flags: Z,8,P,CY,AC INRT (Increment Register) O-M+1 ‘The content of register r is incremented by ‘one. Note: All condition flags except CY are affected. INRM (Increment memory) MY — MH) +1 The content of the memory location whose address is contained in the H and L registers is incremented by one. Note: All condition flags except CY are affected. 10 feg. indirect Z,8,P,AC Derr (Decrement Register) a ‘The content of register ris decremented by ‘one. Note: All condition flags except CY are affected. Cycles: 1 States: 4 (8085), 5 (8080) Addressing: register Flags: Z,8,P,AC DCRM (Decrement memory) H) (Q) — (H) (LY) = 9 The content of the memory location whose address is contained in the H and L registers is decremented by one. Note: All condition flags except CY are affected. Cycles: 1 States: 4 (8085), 5 (8080) Addressing: —_ register Flags: —Z,S,P,AC +All mnemonics copyrighted © intel Corporation 1976. 58 10 rag. indirect Z,8,P,ACTHE INSTRUCTION SET INX rp (Increment register pair) (eh) (et) — (rh) (et) + 1 The content of the register pair rp is in- ‘cremented by one. Note: No condition flags are affected. T T TT _T o o}/R P}o o 4°14 Cycles: 1 States: 6 (6085), 5 (8080) Addressing: —_ register Flags: none DCX rp (Decrement register pair) (ch) (et) = (rh) (rt) = 1 The content of the register pair rp is decremented by one. Note: No condition flags are affected. T T RSE EEeaeeres 1 6 (6085), 5 (8080) register none DAD rp (Add register pair to H and L) 4H) (= (H) (L) + (th) (rt) The content of the register pair rp is added to the content of the register pair H and L. The result is placed in the register pair H and L. Note: Only the CY flag is affected. It is set if there is a carry out of the double DAA (Decimal Adjust Accumulator) The eight-bit number in the accumulator is adjusted to form two four-bit Binary-Coded- Decimal digits by the following process: 1. If the value of the lease significant 4 bits, of the accumulator is greater than 9 or if the AC flag is set, 6 is added to the ac- cumulator. 2. If the value of the most significant 4 bits of the accumulator is now greater than 9, or if the CY flag is set, 6 is added to the most significant 4 bits of the ac- cumulator. NOTE: All flags are affected. Cycles: 1 States: 4 Flags: Z,S,P,CY,AC 5.6.3 Logical Group This group of instructions performs logical (Boolean) operations on data in registers and memory and on condition flags. Unless indicated otherwise, all instructions in this group affect the Zero, Sign, Parity, Auxiliary Carry, and Carry flags according to 'the stan- dard rules. ANAT {AND Register) (A) — (A) A) The content of register ris logically ANDed with the content of the accumulator. The result |s placed in the accumulator. The CY flag Is cleared and AC is set (8085). The CY flag is cleared and AC is set to the OR’ing precision add; otherwise it is reset. of bits 3 of the operands (8080). T T Teele Cecaiiaeeaaletaa TT . oo | RP | 1 0 0 4 Tee HOH een O HOt Helis ag: Gycles: 3 1 States: 10 4 Addressing: register register Flags: CY Z,S,P,CY,AC “All maomonies copyrighted © Intel Corporation 1976,THE INSTRUCTION SET ANAM (AND memory) (A) — (A) (H) (L) The contents of the memory location whose address is contained in the H and L registers is logically ANDed with the con- tent of the accumulator. The result is placed in the accumulator. The CY tlag is Cleared and AC is set (8085). The CY flag is cleared and AC Is set to the OR’ing of bits 3 of the operands (8080). Gyoles: 2 States: 7 Addressing: reg. indirect Flags: Z,8,P,CY,AC ANI data (AND immediate) (A) — (A) A (byte 2) ‘The content of the second byte of the in- struction is logically ANDed with the con- tents of the accumulator. The result is placed in the accumulator. The CY flag is cleared and AC Is set (8085). The CY flag is cleared and AC Is set to the OR’ing of bits 3 of the operands (8080). Cycles: 2 States: 7 Addressing: immediate Flags: Z,8,P,CY,AC XRAr (Exclusive OR Register) (A) — (A)-¥ The content of register r is exclusive-OR'd with the content of the accumulator. The result is placed in the accumulator. The CY and AC flags are cleared. XRAM (Exclusive OR Memory) (A) ~ (A) ((H) (L) The content of the memory location whose address is contained in the H and L registers is exclusive-OR’d with the con- tent of the accumulator. The result is placed in the accumulator. The CY and AC flags are cleared. XRI data (Exclusive OR immediate) (A) ~ (A). (byte 2) The content of the second byte of the in- struction is exclusive-OR'd with the con- tent of the accumulator. The result is placed in the accumulator. The CY and AC flags are cleared. I 1 4° 4° 0 4°47 4 °0 data 2 7 immediate Flags: Z,8,P,CY,AC ORAr (OR Register) A) - AV) The content of register r is inclusive-OR'd with the content of the accumulator. The result is placed in the accumulator. The CY and AC flags are cleared. register ZS,P,CY,AC *Ai1 maemonics copyrighted ©intel Corporation 1976. 510 Cycles: 1 States: 4 Addressing: register Flags: Z,S,P,CY,ACTHE INSTRUCTION SET ORAM (OR memory) ) — AV (HD) : The content of the memory location whose address is contained in the H and L registers is inclusive-OF’d with the content of the accumulator. The result is placed in the accumulator. The CY and AC flags are cleared. ORI data 2 7 Addressing: reg. indirect Flags: Z,8,P,CY,AC (OR Immediate) (A) — (A) V (byte 2) The content of the second byte of the in- struction is inclusive-OR'd with the content of the accumulator. The result is placed in the accumulator. The CY and AC flags are cleared.. 2 7 Addressing: immediate Flags: — Z,S,P,CY,AC (Compare Register) a) The content of register r is subtracted from the accumulator. The accumulator remains unchanged. The condition flags are set as. a result of the subtraction. The Z flag is set to 1 If (A) = (f). The CY flag is set to 1 if (A) <0. Cycles: 1 States: 4 Addressing: register Flags: Z,S,P,CY,AC “AIL mnemonics copyrighted © Intel Corporation 1976. CMP M CPI data (Compare memory) (@) - (HO) The content of the memory location whose address is cont id in the H and L registers is subtracted from the ac- cumulator. The accumulator remains un- changed. The condition flags are set as a result of the subtraction. The Z flag is set to 1 if (A)=((H) (L)). The CY flag is set to 1 if A)<(H) (Ly Cycles: 2 States: 7 Addressing: —_ reg. indirect Flags: Z,8,P,CY,AC (Compare immediate) (A) — (byte 2) ‘The content of the second byte of the in- struction is subtracted from the ac- cumulator. The condition flags are set by the result of the subtraction. The Z tlag is. set to 1 If (A)=(byte 2). The CY flag is set to Tif (A)<(byte 2). data Cycles: 2 States: 7 Addressing: — immediate Flags: Z,S,P,CY,AC RL (Rotate left) (Ag +1) = (An) s(Ao) — (Ar) (CY) — (Ar) The content of the accumulator is rotated left one position. The low order bit and the GY flag are both set to the value shifted out of the high order bit position. Only the CY flag is affected. Eee Cycles: 1 States: 4 Flags: CY