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Binary Divider

This document describes a signed divider circuit. It contains the VHDL code for a divider entity with ports for inputs like the dividend and divisor, and outputs like the quotient and remainder. The architecture contains signals and processes to perform the division algorithm. It shifts the dividend left and subtracts the divisor if possible, tracking the quotient and overflow in 6 states over multiple clock cycles.

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315 views

Binary Divider

This document describes a signed divider circuit. It contains the VHDL code for a divider entity with ports for inputs like the dividend and divisor, and outputs like the quotient and remainder. The architecture contains signals and processes to perform the division algorithm. It shifts the dividend left and subtracts the divisor if possible, tracking the quotient and overflow in 6 states over multiple clock cycles.

Uploaded by

PB
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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library ieee;

use ieee.std_logic_1164.all;
entity divider is
port (St, Clk: in std_logic;
dend: in std_logic_vector(7 downto 0);
dsor: in std_logic_vector(3 downto 0);
v: out std_logic;
qent: out std_logic_vector(3 downto 0)
Rem:out std_logic_vector(3 downto 0));
end divider;

architecture beh of divider is


signal C, Sh, su, Ld: std_logic;
signal DendR: std_logic_vector(8 downto 0);
signal DsorR: std_logic_vector(3 downto 0);
signal Sub: std_logic_vector(4 downto 0);
signal State, nxState: integer range 0 to 6;
begin
Sub <= Add4 (DendR(8 downto 4), 0 & not(DsorR), 1);
C<=sub(4);
Qent<=DendR(3 downto 0);
Rem<=DendR(7 downto 4);
Process (state, st, C)
Begin
V<= 0; Sh<= 0; Su<=0; Ld<=0;

Case state is
When 0=> if (St=1) then Ld<=1; nxState<=1;
Else nxstate<=0; end if;
When 1=> if(C=1) then V<=1; nxstate<=0;
Else Sh<=1; nxState<=2; end if;
When 2 => if (C=1) then Su<=1; nxstate<=State;
Else Sh<=1; nxstate<=state + 1; end if;
When 3 => if (C=1) then Su<=1; nxstate<=State;
Else Sh<=1; nxstate<=state + 1; end if;
When 4 => if (C=1) then Su<=1; nxstate<=State;
Else Sh<=1; nxstate<=state + 1; end if;
When 5 => if (C=1) then Su<=1; nxstate<=State;
Else Sh<=1; nxstate<=0; end if;
end case;
end process;

process (Clk)
begin
if (Clk=1 and Clkevent) then
state<=nxState;
if (Ld=1) then
DendR<=0 & dend;
DsorR<=dsor;
end if;
If (Sh=1) then
DendR<= DendR (7 downto 0) & 0;
end if;
If (Su=1) then
DendR(8 downto 4) <=sub(4 downto 0);
DendR(0)<=1;
end if;
End if;
End process;
End divider;

Control Signals for Signed Divider

LdU Load upper half of dividend from bus


LdL Load lower half of dividend from bus
Lds Load sign of dividend into sign flip-flop
S Sign of dividend
Cm1 Complement dividend register (2's complement)
Ldd Load divisor from bus
Su Enable adder output onto bus (Ena) and load upper half of dividend from bus
Cm2 Enable complementer (Cm2 equals the complement of the sign bit of the divisor,
so that a positive divisor is complemented and a negative divisor is not)
Sh Shift the dividend register left one place and increment the counter
C Carry output from adder (If C = 1, the divisor can be subtracted from the upper
dividend.)
St Start
V Overflow
Qneg Quotient will be negative (Qneg = 1 when sign of dividend and divisor are
different)

entity sdiv is
port(Clk,St: in bit;
Dbus: in bit_vector(15 downto 0); Quotient: out
bit_vector(15 downto 0);
V, Rdy: out bit);
end sdiv;

architecture Signdiv of Sdiv is


constant zero_vector: bit_vector(31 downto 0):=(others=>'0');
signal State: integer range 0 to 6; signal Count : integer range 0 to
15;
signal Sign,C,NC: bit; signal Divisor,Sum,Compout: bit_vector(15
downto 0);
signal Dividend: bit_vector(31 downto 0);
alias Q: bit_vector(15 downto 0) is Dividend(15 downto 0);
alias Acc: bit_vector(15 downto 0) is Dividend(31 downto 16);

begin -- concurrent statements


compout <= divisor when divisor(15) = '1' -- 1's complementer
else not divisor;
Addvec(Acc,compout,not divisor(15),Sum,C,16); -- 16-bit adder
Quotient <= Q; Rdy <= '1' when State=0 else '0';

process
begin
wait until Clk = '1'; -- wait for rising edge of clock
case State is
when 0=>
if St = '1' then
Acc <= Dbus; -- load upper dividend
Sign <= Dbus(15); State <= 1;
V <= '0'; Count <= 0; -- initialize overflow// initialize counter
end if;

when 1=>
Q <= Dbus; State <= 2; -- load lower dividend
when 2=>
Divisor <= Dbus;
if Sign ='1'then -- two's complement Dividend if necessary
addvec(not Dividend,zero_vector,'1',Dividend,NC,32);
end if; State <= 3;

when 3=>
Dividend <= Dividend(30 downto 0) & '0'; -- left shift
Count <= Count+1; State <= 4;
when 4 =>
if C ='1' then -- C
v <= '1'; State <= 0;
else -- C'
Dividend <= Dividend(30 downto 0) & '0'; -- left shift
Count <= Count+1; State <= 5;
end if;

when 5 =>
if C = '1' then -- C
ACC <= Sum; -- subtract
Q(0)<= '1';
else
Dividend <= Dividend(30 downto 0) & '0'; -- left shift
if Count = 15 then -- KC'
count<= 0; State <= 6;
else Count <= Count+1;
end if;
end if;

when 6=>
if C = '1' then -- C
Acc <= Sum; -- subtract
Q(0) <= '1';
else if (Sign xor Divisor(15))='1' then -- C'Qneg
addvec(not Dividend,zero_vector,'1',Dividend,NC,32);
end if; -- 2's complement Dividend
state <= 0;
end if;
end case;
end process;
end signdiv

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