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Lab Report

This document summarizes an ECE 241 lab experiment where the objective was to design, verify, and implement a 2-bit comparator using combinational logic. The procedure involved creating a truth table, separating the outputs into equal, greater than, and less than, and designing the logic circuit. Verification included testing the design and fixing errors. The conclusion notes the design worked but identifies opportunities to further simplify the circuit design.

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124 views1 page

Lab Report

This document summarizes an ECE 241 lab experiment where the objective was to design, verify, and implement a 2-bit comparator using combinational logic. The procedure involved creating a truth table, separating the outputs into equal, greater than, and less than, and designing the logic circuit. Verification included testing the design and fixing errors. The conclusion notes the design worked but identifies opportunities to further simplify the circuit design.

Uploaded by

maulmen724
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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ECE 241 Lab #2

Combinational Logic Design


Ozi Alen

Objective:
Design, verify and implement a 2-bit comparator to become familiar with combinational logic
design. The comparator will accept two, 2-bit unsigned numbers and display an output reading whether
the inputs are equal, one is larger than the other, or one is smaller than the other.
Procedure:
The first step in the experiment involved the design of the comparator. This process begins with
a truth table listing all possible input and output values. After creating the truth table, then separate the
outputs based on A = B (E), A>B (G) or A<B (L). Now, in order to simplify the circuit and remove any
unnecessary gates, I only focused on which values would cover the others. For example, if A0 (the
first input and msb) is 1 and the msb for B is 0, then A > B. This results in a two-input and gate with
one inverter for the B value. In order to minimize the components necessary, I struggled to get this as
simple as possible, including using XNOR gates for the A=B scenarios.
Step two required the verification and implementation of the design. After creating a
schematic, I ran a test bench wave file to check that the outputs would match my predictions and they
appeared to do so. It ended up that I had entered some wrong values for the inputs on my schematic
and therefore had to do some damage control at the end. The next part of implementation was to
assign the package pins which became clear after discovering where the inputs and LED lights were
located on the board. After assigning the package pins, the post-route simulation resulted in a worst
case lag of seven nano-seconds (see attached).
Verification was the last and final step of the experiment. As mentioned earlier, this was the
part where a few things initially did not work correctly. The output LED was not working correctly for
the A<B inputs. After reviewing everything, I determined that my schematic was incorrect. After fixing
this, everything came out as expected.
Conclusion:
Overall, the results came out as they did in my preliminary design. Errors in the schematic as
well as the package pin assignments set me back nearly preventing me from finishing the lab on time.
Another area of opportunity would be further simplification of the circuit design. My design for A<B can
be further simplified by looking at the outputs of A>B and A=B. When the other two outputs are false,
A<B must be true as they are mutually exclusive.

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