0% found this document useful (0 votes)
556 views2 pages

4 Bit Magnitude Comparator-2

This document describes designing a 4-bit magnitude comparator circuit that compares two 4-bit binary inputs and outputs whether the first input is greater than, less than, or equal to the second input. It provides a simple example of a 1-bit comparator circuit and asks the reader to draw a 4-bit comparator circuit using logic gates, write a truth table, and simulate and test the design on an FPGA board.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
556 views2 pages

4 Bit Magnitude Comparator-2

This document describes designing a 4-bit magnitude comparator circuit that compares two 4-bit binary inputs and outputs whether the first input is greater than, less than, or equal to the second input. It provides a simple example of a 1-bit comparator circuit and asks the reader to draw a 4-bit comparator circuit using logic gates, write a truth table, and simulate and test the design on an FPGA board.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 2

4 bit Magnitude Comparator

Design a 4 bit magnitude comparator that compares two 4 bit binary values and output
their relative magnitude.
Magnitude comparator is a combinational circuit that compares to numbers and determines their
relative magnitude. The output of comparator is usually 3 binary variables indicating:
A>B; A=B; A<B

Heres a simple 1 bit comparator circuit :

ECE 205L

Prelab :
1. Draw a circuit using basic logic gates to represent a 4 bit magnitude
comparator.
2. Write a generalized truth table for 4 bit comparator where A3 A2 A1
A0, B3 B2 B1 B0 are inputs and A>B, A<B, A=B are outputs.
(Represent High as logic 1, Low as logic 0 and dont care condition
as X)
Lab :
1. Show the simulation for the verilog modules. Use the following test
values:
A3A2A1A0
1110
1011

B3B2B1B0
0101
1011

1111

0000

1010
0111

1011
1000

1100
0000

1001
0000

2. Demonstrate the same on FPGA using switches for inputs and LEDs for
outputs.

ECE 205L

You might also like