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Iibrary Use Entity Is Port in Downto Out Downto End Architecture of Is Begin y

This document describes a VHDL module that converts a 4-bit binary coded decimal (BCD) input value on port x to a 4-bit binary value on port y. The module uses a series of when/else statements to map each of the 16 possible BCD values on x to the corresponding 4-bit binary value on y.

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Vishu Vishwaroop
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48 views2 pages

Iibrary Use Entity Is Port in Downto Out Downto End Architecture of Is Begin y

This document describes a VHDL module that converts a 4-bit binary coded decimal (BCD) input value on port x to a 4-bit binary value on port y. The module uses a series of when/else statements to map each of the 16 possible BCD values on x to the corresponding 4-bit binary value on y.

Uploaded by

Vishu Vishwaroop
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Iibrary

Use

IEEE;

IEEE . STD_LOGIC_1164 .ALL ;

Entity

bcd_to_c2421

Port

(x :

out

in

is

std_logic_vector

std_logic_vector

(3 downto 0) ;

(3 downto

0} ) ;

end bcd_to_c2421 ;
architecture

behaviorall

of bcd_to_c2421

begin
y <= 0000

when

x = 0000

else

0001

when

x = 0001

else

0010

when

x = 0001

else

0011

when

x = 0010

else

0100

when

x = 0011

else

1011

when

x = 0100

else

1100

when

x = 0100

else

1101

when

x = 1011

else

1110

when

x = 1100

is

else

1111

else

----

when
;

end behaviourall ;

x = 1101

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