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Data Representation: Von Neumann Architecture

This document discusses data representation and computer architecture. It covers ASCII encoding, bytes, Unicode, strings, logical data representation, addresses, Von Neumann architecture including stored program concept and sequential execution. It also describes the bus interconnect system including address lines, data lines, control lines, word length, and basic memory operations like read and write. Main memory is organized into words of a certain bit length determined by the data bus width.

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Nur Syazana
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33 views

Data Representation: Von Neumann Architecture

This document discusses data representation and computer architecture. It covers ASCII encoding, bytes, Unicode, strings, logical data representation, addresses, Von Neumann architecture including stored program concept and sequential execution. It also describes the bus interconnect system including address lines, data lines, control lines, word length, and basic memory operations like read and write. Main memory is organized into words of a certain bit length determined by the data bus width.

Uploaded by

Nur Syazana
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Data Representation

Chapter 7

- ASCII

Von Neumann Architecture

7 bits , 27 = 128 characters


33 control characters
95 printable characters
o 10 dec digits, 26+26 Eng alphabets
o 33 space, punctuation marks, common symbols
-

Byte (8 bits) single character

- Unicode (UTF-8)

Unicode provides a unique number for every character


o no matter what the platform
o no matter what the program
o no matter what the language
Strings
sequence of characters

Logical Data
Each n-bit unit is viewed as consisting of n1-bit items
of data, each item having the value 0 or 1

Addresses
store the memory address

3 key concepts
o Data and instructions are stored in a single
read-write memory
Stored-program concept: instructions in
memory
o Contents of memory are addressable by
location, whether content is data or instruction
o Execution occurs in sequential fashion, unless
explicitly modified by certain instructions
Bus Interconnection
Bus
o communication pathway connecting two or
more devices
o System bus: bus that connects major (top-level)
computer components: processor, memory, I/O
Line
o Electrical connection transmitting digital states
System bus consists of dozens to hundreds of separate
lines, classified into three functional groups
Address lines

Width of address bus

n lines allow addressing 2n


unique memory locations

Maximum possible memory

Basic Memory Operations

capacity

Data lines

Width of data bus

= Amount of data per transfer

= Number of lines (bits) in the data

= Number of bits per memory


location

= 1 Word = Word length

Control lines
Control the access to & use of the data lines
and address lines

Read, write

Bus request, bus grant

Interrupt request, interrupt


acknowledge (ACK)

Clock, reset

Main Memory
o

word= group of n bits

n: word length = width of data bus

different systems have different word length

Processor Memory

Access Memory

Processor Memory

Write

bus

Read

Mean read or write

Word Addressing

Native memory addressing

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