VLSI lab manual

VII sem, ECE

CONTENTS
1. Syllabus

2. PROCEDURES FOR DIGITAL DESIGN

3. Experiment no. 1: Inverter digital design

4. Experiment no. 2: Buffer

14

5. Experiment no. 3: Transmission gate

18

6. Experiment no. 4: Logic gates

20

7. Experiment no. 5: Flip-flops

34

8. Experiment no. 6: Serial and Parallel adders

47

9. Experiment no. 7: 4-bit counters (Synchronous & Asynchronous)

55

10. Experiment no. 8: Successive Approximation Register

61

11. PROCEDURES FOR ANALOG DESIGN

65

12. Experiment no. 9: Inverter analog design

70

13. Experiment no. 10: Common source & Common drain amplifiers

92

14. Experiment no. 11: Single stage differential amplifier

103

15. Experiment no. 12: Operational amplifier

107

16. Experiment no. 13: 4-bit R-2R DAC

111

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SYLLABUS
Subject Code: 06ECL77
No. of Practical Hrs/Week: 03
Total no. of Practical Hrs.: 42

IA Marks: 25
Exam Hours: 03
Exam Marks: 50

PART A
DIGITAL DESIGN
1.

Write Verilog Code for the following circuits and their Test Bench for verification, observe
the waveform and synthesize the code with the technological library, with the given
Constraints*. Do the initial timing verification with gate level simulation.
i.
ii.
iii.
iv.
v.
vi.
vii.
viii.

An inverter
A Buffer
Transmission Gate
Basic/universal gates
Flip flop - RS, D, JK, MS, T
Serial & Parallel adder
4-bit counter [Synchronous and Asynchronous counter]
Successive approximation register [SAR]

* An appropriate constraint should be given

PART - B
ANALOG DESIGN
1.

Design an Inverter with given specifications*, completing the design flow mentioned below:
a. Draw the schematic and verify the following: i) DC Analysis ii) Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the Design
e. Verify & Optimize for Time, Power and Area to the given constraint***

2.

Design the following circuits with the given specifications*, completing the design flow
mentioned below:
a. Draw the schematic and verify the following:

i) DC Analysis ii) AC Analysis

iii) Transient Analysis

b. Draw the Layout and verify the DRC, ERC

c. Check for LVS
d. Extract RC and back annotate the same and verify the Design.
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i) A Single Stage differential amplifier

ii) Common source and Common Drain amplifier
3.

Design an op-amp with the given specification* using given differential amplifier, Common
source and Common Drain amplifier in library** and completing the design flow as
mentioned below:
a. Draw the schematic and verify the following:

i) DC Analysis ii) AC Analysis

iii) Transient Analysis

b. Draw the Layout and verify the DRC, ERC

c. Check for LVS
d. Extract RC and back annotate the same and verify the Design.
4.

Design a 4 bit R-2R based DAC for the given specification and completing the design flow
mentioned using given op-amp in the library**.
a. Draw the schematic and verify the following:

i) DC Analysis ii) AC Analysis

iii) Transient Analysis

b. Draw the Layout and verify the DRC, ERC

c. Check for LVS
d. Extract RC and back annotate the same and verify the Design.
5.

For the SAR based ADC mentioned in the figure below, draw the mixed signal schematic
and verify the functionality by completing ASIC Design flow. [Specifications to GDS-II]

* Appropriate specification should be given.

** Applicable Library should be added & information should be given to the Designer.
*** An appropriate constraint should be given.

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PROCEDURES FOR DIGITAL DESIGN

INITIAL PROCEDURES:
1. After logging in, right click and open terminal.
2. Get into the c shell by typing the command
csh
3. Run the shellscript by typing the command
source cshrc.main

I. STEPS FOR DESIGN ENTRY:

1. Move inside Workarea using the cd command cd Cadence_digital_labs/Workarea
2. Create your own design directory (e.g.: Design1) using the mkdir command
mkdir Design1
3. Write the verilog program for your design (e.g.: Codefile1.v) inside Design1 directory.
4. Write the verilog test bench program for your design (e.g.: Codefile1_tb.v) inside Design1
directory. Now, the design entry using HDL gets finished.

II. STEPS FOR SIMULATION:

1. Initially, both of your verilog programs have to be compiled using the command
ncvlog filename -mess
For this example: ncvlog Codefile1.v -mess
ncvlog Codefile1_tb.v -mess

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2. After compilation, you have to elaborate the top module using the command
ncelab modulename -access +rwc -mess
The process of elaboration builds up the instances and then connects them. Care must be
taken that you elaborate only the top module namely the test bench; the attribute for the
command should be the test bench module name.
3. Next step is to simulate the design using the command
ncsim modulename (or)

ncsim modulename -gui

Here also, the simulation has to be performed using the test bench module name. When gui is
used, the Simvision tool will be invoked and the waveforms can be seen.

III. STEPS FOR SYNTHESIS:

1. Move into the rclabs directory inside the Workarea using the command
cd Cadence_digital_labs/Workarea/rclabs
2. There will be four directories inside rclabs namely library, rtl, tcl and work, as shown

Workarea

Design1

rclabs

rtl

tcl

work

library

First, move into rtl directory using the command

cd rtl
3. Inside rtl directory, copy the verilog program which has to be synthesized, using the
command
cp ../../Design1/Codefile1.v .

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This is required because the synthesis is performed only on the design file, and not on the
test bench. Now, edit the program file and delete all of the compiler directives which are
present in the program file (the commands preceded by `).
As the next step, if switch primitives are present in the program, then they have to be
replaced by the RTL description, because of the fact that, the switch primitives are not
synthesizable. The output of synthesis is a schematic using logic gates. This is called as
logic synthesis, which is technology independent.
4. Then come out of that directory using the command
cd ../
5. Now enter into the tcl directory using the command
cd tcl
6. Inside tcl directory there is a file named setup.g. Open this file using the command
gedit setup.g &
7. In this file, you have to update two variables
(a) FILE_LIST {filename}

e.g: FILE_LIST {Codefile1.v}

(b) DESIGN modulename

Save the setup.g file and come out of tcl directory.
8. Next, enter into the directory work. Create a file named Contraints_file.g. The timing
constraints are defined in this file. Example of one such file is as shown
create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"]
set_clock_transition -rise 0.1 [get_clocks "clk"]
set_clock_transition -fall 0.1 [get_clocks "clk"]
set_clock_uncertainty 1.0 [get_ports "clk"]
set_input_delay -max 1.0 [get_ports "A"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_ports "B"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "sum"] -clock [get_clocks "clk"]

There are three different parts in the constraint file:

a. Clock definition and clock constraints
create_clock -name clk -period 10 -waveform {0 5} [get_ports "clock"]
Clock definition
set_clock_transition -rise 0.1 [get_clocks "clk"]
Clock rise time
set_clock_transition -fall 0.1 [get_clocks "clk"]
Clock fall time
set_clock_uncertainty 1.0 [get_ports "clk"]
Uncertainties of Clock

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b. Input port timing constraints

set_input_delay -max 1.0 [get_ports "A"] -clock [get_clocks "clk"]
Input port delay
set_input_delay -max 1.0 [get_ports "B"] -clock [get_clocks "clk"]
Input port delay

c. Output port timing constraints

set_output_delay -max 1.0 [get_ports "sum"] -clock [get_clocks "clk"]
Output port delay

The port names that are used in the constraint file (bolded) must match with the names
that are used in the Verilog program of the main design module. The constraints are
defined for all the ports in the design.
9. Now, invoke the Encounter tool using the command
rc gui
10. The tool will be invoked and you will get the rc prompt in the terminal, along with a
synthesis window. Next, the following commands are to be typed in the rc prompt
1. include ../tcl/setup.g
2. set_attribute library $LIBRARY
3. set SYN_EFF medium
4. set MAP_EFF medium
5. read_hdl $FILE_LIST
6. elaborate $DESIGN
7. read_sdc ./Constraints_file.g
8. synthesize -to_generic -eff $SYN_EFF
9. report timing
10. report area
11. report power
11. The tool will execute each command as and when it is entered. To come out of the
synthesis environment, exit or quit command in the rc prompt is used.
12. The commands of step-10 can be saved in a .tcl file in the work directory, and that script
file can be invoked in the rc prompt, by using the include command. Optionally, the
synthesis can be performed by going to the GUI window and clicking on File, and then
clicking on Source Script, and then selecting the respective script file.

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NOTES
1. Linux commands:
ls

list files

cp

copy files

mv

rename files

rm

remove files

cd

change directory

pwd

print working directory

mkdir make directory

rmdir remove directory

When ls command is given, the directories are displayed in blue color, the files in black color,
the link files in green color, and the tar files in red color respectively.

2. Command options:

for root directory

for present directory

..

for parent directory

-mess for displaying messages

+rwc for obtaining read, write, compilation access
&

3. Abbreviations:

for making the process a background one

GDS Generic Data Stream

IUS

Incisive Unified Simulator

NC

Native compiler

RC

RTL compiler

RTL Register Transfer Level

TCL Tool Command Language

4. Cadence tools used:

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IUS and Simvision

- to compile, elaborate and simulate

rc and Encounter

- for RTL Compilation & Synthesis

VLSI lab manual

VII sem, ECE

EXPERIMENT NO. 1
INVERTER digital design
Aim: To compile and to simulate the Verilog code for an inverter, and then to synthesize the same for
the given constraints.
Design Files: Main design module, Test bench module and Constraints file.

I Main Design Module: Inverter.v

`resetall
`timescale 1 ns / 1 ns
`view vlog
//Define our own Inverter
module inverter (out, in);
// Declarations of I/O, Power and Ground Lines
output out;
input in;
supply1 pwr;
supply0 gnd;
// Instantiate pmos and nmos switches
pmos (out, pwr, in);
nmos (out, gnd, in);
endmodule
`noview

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II Test Bench Module: Inverter_test.v

`resetall
`timescale 1 ns / 1 ns
`view vlog
// Testbench for Inverter Module
module inv_test;
wire out;
reg in;
`uselib view = vlog
// Instantiate inverter Module
inverter i1 (out, in);
`nouselib
// Display
task display;
begin
$display ("Time=%0d ", $time, " ns ", " Input= ", in, " Output= ", out);
end
endtask
// Apply Stimulus
initial
begin
in = 1'b0; #10; display;
in = 1'b1; #10; display;
in = 1'bx; #10; display;
in = 1'bz; #10; display;
end
endmodule
`noview

Note: The task display is used to display the output on the monitor, in the form of a truth table. For
seeing the waveforms, the Simvision tool can be invoked.
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III Constraints file for Synthesis: Constraints_Inverter.g

set_input_delay -max 1.0 [get_ports "in"]
set_output_delay -max 1.0 [get_ports "out"]

Procedure:
Initially, follow all the steps mentioned in the previous section. The rest of the steps are as follows
1. After invoking the Simvision tool with the command ncsim modulename gui, two windows
will be opened: one is the Simvision Console and the other is the Design Browser window of
the tool, as shown in the snap shot

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2. As the next step, you need to click on the module name on the left side of the Design Browser
window. As soon as you click, you will see all the port names displayed in the right side of
the Design Browser window.

3. Then select all the ports for which you want to see the waveforms.

4. Next, click the waveform icon on the right hand side corner of the Design Browser window.
Now the waveform window will open.

5. Click the play button on the waveform window to run the simulation. The waveforms will be
generated as shown

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6. For synthesis, follow the steps that are mentioned previously. After synthesis, the synthesis
window will be shown as follows

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EXPERIMENT NO. 2
BUFFER
Aim: To compile and to simulate the Verilog code for a buffer, and then to synthesize the same for
the given constraints.
Design Files: Main design module, Test bench module and Constraints file.

I Main Design Module: Buffer.v

`resetall
`timescale 1 ns / 1 ns
`view vlog
//Define our own Inverter
module inverter (Y, A);
// Declarations of I/O, Power and Ground Lines
output Y;
input A;
supply1 pwr;
supply0 gnd;
// Instantiate pmos and nmos switches
pmos (Y, pwr, A);
nmos (Y, gnd, A);
endmodule
// Define our own Buffer
module buffer (out, in);
// Declarations of I/O Lines
output out;
input in;

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// Wire Declaration
wire a;
// Instantiate Inverter module
inverter i1 (a, in);
inverter i2 (out, a);
endmodule
`noview

II Test Bench Module: Buffer_test.v

`resetall
`timescale 1 ns / 1 ns
`view vlog
// Testbench for Buffer Module
module buf_test;
wire out;
reg in;
`uselib view = vlog
// Instantiate Buffer Module
buffer b1 (out, in);
`nouselib
// Display
task display;
begin
$display ("Time=%0d ", $time, " ns ", " Input= ", in, " Output= ", out);
end
endtask
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// Apply Stimulus
initial
begin
in = 1'b0; #10; display;
in = 1'b1; #10; display;
in = 1'bx; #10; display;
in = 1'bz; #10; display;
end
endmodule
`noview

III Constraints file for Synthesis: Constraints_Buffer.g

set_input_delay -max 1.0 [get_ports "in"]
set_output_delay -max 1.0 [get_ports "out"]

Procedure:
1. Follow the procedures as mentioned in the previous experiment. The simulation result
snapshot obtained for the buffer is as shown below

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2. The snapshot obtained after synthesis is as shown below

3. When double-clicked inside the blocks shown, the subsystem is displayed as shown

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EXPERIMENT NO. 3
TRANSMISSION GATE
Aim: To compile and to simulate the Verilog code for a transmission gate.
Design Files: Main design module and Test bench module.

I Main Design Module: Tg.v

`resetall
`timescale 1 ns / 1 ns
`view vlog
//Define our own Transmission Gate
module trangate (out, in, cntrl1, cntrl2);
// Declarations of I/O and Control Lines
output out;
input in;
input cntrl1, cntrl2;
// Instantiate pmos and nmos switches
pmos (out, in, cntrl1);
nmos (out, in, cntrl2);
endmodule
`noview

II Test Bench Module: Tg_test.v

`resetall
`timescale 1 ns / 1 ns
`view vlog
// Testbench for Transmission gate
module trangate_test;
wire out;
reg in;
reg cntrl1, cntrl2;

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// Instantiate trangate Module

trangate t1 (out, in, cntrl1, cntrl2);
// Apply Stimulus
initial
begin
in = 1'b0; cntrl1 = 1'b0; cntrl2 = 1'b1; #10;
in = 1'b0; cntrl1 = 1'b1; cntrl2 = 1'b0; #10;
in = 1'b1; cntrl1 = 1'b0; cntrl2 = 1'b1; #10;
in = 1'b1; cntrl1 = 1'b1; cntrl2 = 1'b0; #10;
end
endmodule
`noview
Note: In the test bench module, the task display is not used because, there is no truth table for the
transmission gate as such, and hence it is easy to verify the output using the waveforms.
Procedure:
1. The procedures remain the same as mentioned previously. The simulation result snapshot
obtained for the transmission gate is as shown below

2. As the transmission gate has to be defined in the switch level, we have to use the switch
primitives. Hence, synthesis for this particular design is not possible.

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EXPERIMENT NO. 4
LOGIC GATES
Aim: To compile and to simulate the Verilog code for the basic logic gates, and then to synthesize
those designs for the given constraints.
Design Files: The main design modules and the respective test bench modules are given as follows,
in the order of NAND, AND, NOR, OR, EXOR and EXNOR gates.
Note: The words and, or, nand, nor, xor and xnor are the gate primitives in Verilog, and hence, care
must be taken not to use these keywords as module names or file names.

a) NAND GATE
I Main Design Module: Nandg.v
`resetall
`timescale 1 ns / 1 ns
`view vlog
//Define our own Nand Gate
module nandgate (out, in1, in2);
// Declarations of I/O, Power and Ground Lines
output out;
input in1, in2;
supply1 pwr;
supply0 gnd;
wire contact;
// Instantiate pmos and nmos switches
pmos (out, pwr, in1);
pmos (out, pwr, in2);
nmos (out, contact, in1);
nmos (contact, gnd, in2);
endmodule
`noview

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II Test Bench Module: Nand_test.v

`resetall
`timescale 1 ns / 1 ns
`view vlog
// Testbench for Nand Gate Module
module nand_test;
wire out;
reg in1, in2;
`uselib view = vlog
// Instantiate Nand Gate Module
nandgate n1 (out, in1, in2);
`nouselib
// Display
task display;
begin
$display ("Time=%0d ", $time, " ns ", " Input1= ", in1, " Input2= ", in2,
" Output= ", out);
end
endtask
// Apply Stimulus
initial
begin
in1 = 1'b0; in2 = 1'b0; #10; display;
in1 = 1'b0; in2 = 1'b1; #10; display;
in1 = 1'b1; in2 = 1'b0; #10; display;
in1 = 1'b1; in2 = 1'b1; #10; display;
end
endmodule
`noview

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b) AND GATE
I Main Design Module: Andg.v
`resetall
`timescale 1 ns / 1 ns
`view vlog
//Define our own And Gate
module andgate (out, in1, in2);
// Declarations of I/O, Power and Ground Lines
output out;
input in1, in2;
supply1 pwr;
supply0 gnd;
// Declaration of Wires
wire contact;
wire nout;
// Instantiate pmos and nmos switches to form Nand gate
pmos (nout, pwr, in1);
pmos (nout, pwr, in2);
nmos (nout, contact, in1);
nmos (contact, gnd, in2);
// Instantiate pmos and nmos switches to form Inv
pmos (out, pwr, nout);
nmos (out, gnd, nout);
endmodule
`noview

II Test Bench Module: And_test.v

`resetall
`timescale 1 ns / 1 ns
`view vlog

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// Testbench for And Module

module and_test;
wire out;
reg in1, in2;
`uselib view = vlog
// Instantiate And Gate Module
andgate a1(out, in1, in2);
`nouselib
// Display
task display;
begin
$display ("Time=%0d ", $time, " ns ", " Input1= ", in1, " Input2= ", in2,
" Output= ", out);
end
endtask
// Apply Stimulus
initial
begin
in1 = 1'b0; in2 = 1'b0; #10; display;
in1 = 1'b0; in2 = 1'b1; #10; display;
in1 = 1'b1; in2 = 1'b0; #10; display;
in1 = 1'b1; in2 = 1'b1; #10; display;
end
endmodule
`noview
Result: The simulation result for the AND gate is as shown

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c) NOR GATE
I Main Design Module: Norg.v
`resetall
`timescale 1 ns / 1 ns
`view vlog
//Define our own Nor Gate
module norgate (out, in1, in2);
// Declarations of I/O, Power and Ground Lines
output out;
input in1, in2;
supply1 pwr;
supply0 gnd;
// Declaration of Wire
wire contact;
// Instantiate pmos and nmos switches
pmos (contact, pwr, in1);
pmos (out, contact, in2);
nmos (out, gnd, in1);
nmos (out, gnd, in2);
endmodule
`noview

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II Test Bench Module: Nor_test.v

`resetall
`timescale 1 ns / 1 ns
`view vlog
// Testbench for Nor Gate Module
module nor_test;
wire out;
reg in1, in2;
`uselib view = vlog
// Instantiate Nor Gate Module
norgate n1 (out, in1, in2);
`nouselib
// Display
task display;
begin
$display ("Time=%0d ", $time, " ns ", " Input1= ", in1, " Input2= ", in2,
" Output= ", out);
end
endtask
// Apply Stimulus
initial
begin
in1 = 1'b0; in2 = 1'b0; #10; display;
in1 = 1'b0; in2 = 1'b1; #10; display;
in1 = 1'b1; in2 = 1'b0; #10; display;
in1 = 1'b1; in2 = 1'b1; #10; display;
end
endmodule
`noview

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d) OR GATE
I Main Design Module: Org.v
`resetall
`timescale 1 ns / 1 ns
`view vlog
//Define our own Or Gate
module orgate (out, in1, in2);
// Declarations of I/O, Power and Ground Lines
output out;
input in1, in2;
supply1 pwr;
supply0 gnd;
// Declaration of Wires
wire contact;
wire nout;
// Instantiate pmos and nmos switches for Nor gate
pmos (contact, pwr, in1);
pmos (nout, contact, in2);
nmos (nout, gnd, in1);
nmos (nout, gnd, in2);
// Instantiate pmos and nmos switches for Not gate
pmos (out, pwr, nout);
nmos (out, gnd, nout);
endmodule
`noview

II Test Bench Module: Or_test.v

`resetall
`timescale 1 ns / 1 ns
`view vlog

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// Testbench for Nor Gate Module

module or_test;
wire out;
reg in1, in2;
`uselib view = vlog
// Instantiate Orgate Module
orgate n1 (out, in1, in2);
`nouselib
// Display
task display;
begin
$display ("Time=%0d ", $time, " ns ", " Input1= ", in1, " Input2= ", in2,
" Output= ", out);
end
endtask
// Apply Stimulus
initial
begin
in1 = 1'b0; in2 = 1'b0; #10; display;
in1 = 1'b0; in2 = 1'b1; #10; display;
in1 = 1'b1; in2 = 1'b0; #10; display;
in1 = 1'b1; in2 = 1'b1; #10; display;
end
endmodule
`noview
Result: The simulation result for the OR gate is as shown

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e) EXOR GATE
Schematic diagram (using pass transistor logic)

in1

in2

out

I Main Design Module: Exorg.v

`resetall
`timescale 1 ns / 1 ns
`view vlog
//Define our own XOR Gate
module xorgate (out, in1, in2);
output out;
input in1, in2;
wire in2bar;
assign in2bar = ~ in2;
pmos (out, in2, in1);
nmos (out, in1, in2bar);
pmos (out, in1, in2);
nmos (out, in2bar, in1);
endmodule
`noview

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II Test Bench Module: Exor_test.v

`resetall
`timescale 1 ns / 1 ns
`view vlog
// Testbench for Xor Module
module xor_test;
wire out;
reg in1, in2;
`uselib view = vlog
// Instantiate Xorgate Module
xorgate x1 (out, in1, in2);
`nouselib
// Display
task display;
begin
$display ("Time=%0d ", $time, " ns ", " Input1= ", in1, " Input2= ", in2,
" Output= ", out);
end
endtask
// Apply Stimulus
initial
begin
in1 = 1'b0; in2 = 1'b0; #10; display;
in1 = 1'b0; in2 = 1'b1; #10; display;
in1 = 1'b1; in2 = 1'b0; #10; display;
in1 = 1'b1; in2 = 1'b1; #10; display;
end
endmodule
`noview

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f) EXNOR GATE
Schematic diagram (using pass transistor logic)

in1

out

in2

I Main Design Module: Exnorg.v

`resetall
`timescale 1 ns / 1 ns
`view vlog
module xnorgate (out, in1, in2);
output out;
input in1, in2;
wire in2bar;
assign in2bar = ~ in2;
// Instantiate pmos and nmos switches
pmos (out, in2bar, in1);
nmos (out, in1, in2);
pmos (out, in1, in2bar);
nmos (out, in2, in1);
endmodule
`noview

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II Test Bench Module: Exnor_test.v

`resetall
`timescale 1 ns / 1 ns
`view vlog
// Testbench for Xnor Module
module xnor_test;
wire out;
reg in1, in2;
`uselib view = vlog
xnorgate x1 (out, in1, in2);
`nouselib
// Display
task display;
begin
$display ("Time=%0d ", $time, " ns ", " Input1= ", in1, " Input2= ", in2,
" Output= ", out);
end
endtask
initial
begin
in1 = 1'b0; in2 = 1'b0; #10; display;
in1 = 1'b0; in2 = 1'b1; #10; display;
in1 = 1'b1; in2 = 1'b0; #10; display;
in1 = 1'b1; in2 = 1'b1; #10; display;
end
endmodule
`noview

Procedure for synthesis:

1. As the design modules are described using the switch primitives, they are not synthesizable.
Therefore, separate Verilog code inclusive of all the logic gates is written, either using RTL
description or using the gate primitives, and then, this particular code is synthesized in
accordance with the given constraints.

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III Verilog code for Synthesis (using RTL description): Gates_RTL.v

module gates (a, b, andg, org, nandg, norg, xorg, xnorg);
output andg, org, xorg, nandg, norg, xnorg;
input a, b;
assign andg = a & b;
assign org = a | b;
assign xorg = a ^ b;
assign nandg = ~ (a & b);
assign norg = ~ (a | b);
assign xnorg = ~ (a ^ b);
endmodule

IV Constraints file for Synthesis: Constraints_gates.g

set_input_delay -max 1.0 [get_ports "a"]
set_input_delay -max 1.0 [get_ports "b"]
set_output_delay -max 1.0 [get_ports "andg"]
set_output_delay -max 1.0 [get_ports "org"]
set_output_delay -max 1.0 [get_ports "nandg"]
set_output_delay -max 1.0 [get_ports "norg]
set_output_delay -max 1.0 [get_ports "xorg"]
set_output_delay -max 1.0 [get_ports "xnorg"]

2. The synthesis result snapshot using RTL description is as shown

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Verilog code for Synthesis (using the gate primitives): Gates_gate.v

module gates (out1, out2, out3, out4, out5, out6, in1, in2);
output out1, out2, out3, out4, out5, out6;
input in1, in2;
and a1 (out1, in1, in2);
or a2 (out2, in1, in2);
nand a3 (out3, in1, in2);
nor a4 (out4, in1, in2);
xor a5 (out5, in1, in2);
xnor a6 (out6, in1, in2);
endmodule
Note: The constraints file will remain the same, except for the change in the variable names.

3. The synthesis result snapshot using the gate primitives is as shown

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EXPERIMENT NO. 5
FLIP-FLOPS
Aim: To compile and to simulate the Verilog code for the common flip-flops, and then to synthesize
those designs for the given constraints.
Design Files: The main design modules and the respective test bench modules are given as follows,
in the order of SR, JK, D, T and MS (The full forms for the names are: Set Reset, Jack Kilby, Data,
Toggle and Master Slave). The compiler directives are not used in these modules, as the primitives
are not used in the design modules, and the timing is specified in the test bench modules.

a) SR FLIP-FLOP
I Main Design Module: SR_ff.v
module srff (q, qbar, s, r, clk, rst);
output q, qbar;
input clk, s, r, rst;
reg tq;
always @(posedge clk or posedge rst)
begin
if (rst)
tq <= 1'b0;
else
begin
if (s == 1'b0 && r == 1'b0)
tq <= tq;
else if (s == 1'b0 && r == 1'b1)
tq <= 1'b0;
else if (s == 1'b1 && r == 1'b0)
tq <= 1'b1;
else if (s == 1'b1 && r == 1'b1)
tq <= 1'bx;
end
end
assign q = tq;
assign qbar = ~ tq;
endmodule

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II Test Bench Module: SR_ff_test.v

module srff_test;
reg clk, s, r, rst;
wire q, qbar;
srff sr1(q, qbar, s,r, clk, rst);
initial
clk = 1'b0;
always
#10 clk = ~ clk;
initial
begin
rst = 1'b1;
s = 1'b0; r = 1'b0;
#15 rst = 1'b0;
#25 r = 1'b1;
#20 s = 1'b1; r = 1'b0;
#20 r = 1'b1;
#20 s = 1'b0; r = 1'b0;
#15 rst = 1'b1;
end
initial
#130 $finish;
endmodule

Following is the simulation result snapshot for the SR flip-flop

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III Constraints file for Synthesis: Constraints_SR_ff.g

create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"]
set_clock_transition -rise 0.1 [get_clocks "clk"]
set_clock_transition -fall 0.1 [get_clocks "clk"]
set_clock_uncertainty 1.0 [get_ports "clk"]
set_input_delay -max 1.0 [get_ports "rst"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_ports "s"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_ports "r"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "q"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "qbar"] -clock [get_clocks "clk"]
Following is the synthesis result snapshot for the SR flip-flop

Note: After synthesis, the command report timing -lint can be used in the rc prompt, to verify
whether all the timing constraints are applied or not.
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b) JK FLIP-FLOP
I Main Design Module: JK_ff.v
module jkff (q, qbar, j, k, clk, rst);
output q, qbar;
input clk, j, k, rst;
reg tq;
always @(posedge clk or posedge rst)
begin
if (rst)
tq <= 1'b0;
else
begin
if (j == 1'b0 && k == 1'b0)
tq <= tq;
else if (j == 1'b0 && k == 1'b1)
tq <= 1'b0;
else if(j == 1'b1 && k == 1'b0)
tq <= 1'b1;
else if(j == 1'b1 && k == 1'b1)
tq <= ~ tq;
end
end
assign q = tq;
assign qbar = ~ tq;
endmodule

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II Test Bench Module: JK_ff_test.v

module jkff_test;
reg clk, j, k, rst;
wire q, qbar;
jkff jk1(q, qbar, j, k, clk, rst);
initial
clk = 1'b0;
always
#10 clk = ~ clk;
initial
begin
rst = 1'b1;
j = 1'b0; k = 1'b0;
#15 rst = 1'b0;
#25 k = 1'b1;
#20 j = 1'b1; k = 1'b0;
#20 k = 1'b1;
#20 j = 1'b0; k = 1'b0;
#15 rst = 1'b1;
end
initial
#130 $finish;
endmodule

Following is the simulation result snapshot for the JK flip-flop

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III Constraints file for Synthesis: Constraints_JK_ff.g

create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"]
set_clock_transition -rise 0.1 [get_clocks "clk"]
set_clock_transition -fall 0.1 [get_clocks "clk"]
set_clock_uncertainty 1.0 [get_ports "clk"]
set_input_delay -max 1.0 [get_ports "rst"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_ports "j"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_ports "k"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "q"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "qbar"] -clock [get_clocks "clk"]

Following is the synthesis result snapshot for the JK flip-flop

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c) D FLIP-FLOP
I Main Design Module: D_ff.v
module dff(q, qbar, d, clk, rst);
output q, qbar;
input clk, d, rst;
reg tq;
always @(posedge clk or posedge rst)
begin
if (rst)
tq <= 1'b0;
else
tq <= d;
end
assign q = tq;
assign qbar = ~ tq;
endmodule

II Test Bench Module: D_ff_test.v

module dff_test;
reg clk, d, rst;
wire q, qbar;
dff d1(q, qbar, d, clk, rst);
initial
clk = 1'b0;
always
#10 clk = ~ clk;
initial
begin
rst = 1'b1;
d = 1'b0;
#15 rst = 1'b0;
#25 d = 1'b1;
#20 d = 1'b0;
#20 d = 1'b1;
end
initial
#110 $finish;
endmodule

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Following is the simulation result snapshot for the D flip-flop

III Constraints file for Synthesis: Constraints_D_ff.g

create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"]
set_clock_transition -rise 0.1 [get_clocks "clk"]
set_clock_transition -fall 0.1 [get_clocks "clk"]
set_clock_uncertainty 1.0 [get_ports "clk"]
set_input_delay -max 1.0 [get_ports "rst"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_ports "d"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "q"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "qbar"] -clock [get_clocks "clk"]

Following is the synthesis result snapshot for the D flip-flop

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d) T FLIP-FLOP
I Main Design Module: T_ff.v
module tff(q, qbar, t, clk, rst);
output q, qbar;
input clk, t, rst;
reg tq;
always @(posedge clk or posedge rst)
begin
if (rst)
tq <= 1'b0;
else
begin
if (t)
tq <= ~ tq;
end
end
assign q = tq;
assign qbar = ~ tq;
endmodule

II Test Bench Module: T_ff_test.v

module T_ff_test;
reg clk, t, rst;
wire q, qbar;
tff t1(q, qbar, t, clk, rst);
initial
clk = 1'b0;
always
#10 clk = ~ clk;
initial
begin
rst = 1'b1; t = 1'b0;
#15 rst = 1'b0;
#25 t = 1'b1;
#300 t = 1'b0;
#100 t = 1'b1;
#200 rst = 1'b1;
end
initial
#800 $finish;
endmodule

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Following is the simulation result snapshot for the T flip-flop

III Constraints file for Synthesis: Constraints_T_ff.g

create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"]
set_clock_transition -rise 0.1 [get_clocks "clk"]
set_clock_transition -fall 0.1 [get_clocks "clk"]
set_clock_uncertainty 1.0 [get_ports "clk"]
set_input_delay -max 1.0 [get_ports "rst"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_ports "t"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "q"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "qbar"] -clock [get_clocks "clk"]

Following is the synthesis result snapshot for the T flip-flop

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e) MS FLIP-FLOP
I Main Design Module: MS_ff.v
module JK_ff(q, qbar, j, k, clk, rst);
output q, qbar;
input j, k, clk, rst;
reg tq;
always @(posedge clk or posedge rst)
begin
if(rst)
tq <= 1'b0;
else
begin
if(j == 1'b0 && k == 1'b0)
tq <= tq;
else if(j == 1'b0 && k == 1'b1)
tq <= 1'b0;
else if(j == 1'b1 && k == 1'b0)
tq <= 1'b1;
else if(j == 1'b1 && k == 1'b1)
tq <= ~ tq;
end
end
assign q = tq;
assign qbar = ~ tq;
endmodule
module MS_ff(s, sbar, m, mbar, inj, ink, clk, rst);
output s, sbar;
inout m, mbar;
input inj, ink, clk, rst;
wire clkbar;
assign clkbar = ~ clk;
JK_ff jk1(m, mbar, inj, ink, clk, rst);
JK_ff jk2(s, sbar, m, mbar, clkbar, rst);
endmodule

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II Test Bench Module: MS_ff_test.v

module MS_ff_test;
reg j, k, clk, rst;
wire q, qbar, m, mbar;
MS_ff ms1(q, qbar, m, mbar, j, k, clk, rst);
initial
clk = 1'b0;
always
#10 clk = ~ clk;
initial
begin
rst = 1'b1; j = 1'b0; k = 1'b0;
#15 rst = 1'b0;
#25 k = 1'b1;
#20 j = 1'b1; k = 1'b0;
#20 k = 1'b1;
#20 j = 1'b0; k = 1'b0;
#25 rst = 1'b1;
end
initial
#140 $finish;
endmodule

Following is the simulation result snapshot for the MS flip-flop

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III Constraints file for Synthesis: Constraints_MS_ff.g

create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"]
set_clock_transition -rise 0.1 [get_clocks "clk"]
set_clock_transition -fall 0.1 [get_clocks "clk"]
set_clock_uncertainty 1.0 [get_ports "clk"]
set_input_delay -max 1.0 [get_ports "rst"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_ports "inj"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_ports "ink"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_ports "m"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_ports "mbar"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "m"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "mbar"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "s"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "sbar"] -clock [get_clocks "clk"]

Note: As the masters output ports are declared as inout, those ports have to be given with both input
as well as output timing constraints.

Following is the synthesis result snapshot for the MS flip-flop

When double-clicked inside the blocks shown, the subsystem JK flip-flop gets displayed.

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EXPERIMENT NO. 6
SERIAL AND PARALLEL ADDERS
Aim: To compile and to simulate the Verilog code for the serial and parallel adders, and then to
synthesize those designs for the given constraints.
Design Files: The main design modules and the respective test bench modules are given as follows,
in the order of serial adder, and then parallel adder. Both are assumed to be of 4-bit.

a) SERIAL ADDER
Block diagram

Load Add

Add

Data1
[3:0]

Sum
[3:0]

Sum_int
Shift Register - 1

Clk

Shift Register - Sum

Clk

FULL
ADDER

Reset

Reset
Carry

Shift Register - 2
Data2
[3:0]

C_out_final
C_out

C_int

Add
Reset Add

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I Main Design Module: Serial_adder.v

module serial_adder(load, add, clk, reset, data1, data2, sum, carry, ready);
input load, add, clk, reset;
input [3:0] data1, data2;
output [3:0] sum;
output carry, ready;
reg [3:0] data1_sr, data2_sr, sum_sr;
reg c_int, c_out_final;
wire sum_int, c_out;
always @(posedge clk or posedge reset)
if (reset)
data1_sr <= 4'h0;
else if (load)
data1_sr <= data1;
else if (add)
data1_sr <= {1'b0, data1_sr[3:1]};
else
data1_sr <= data1_sr;
always @(posedge clk or posedge reset)
if (reset)
data2_sr <= 4'h0;
else if (load)
data2_sr <= data2;
else if (add)
data2_sr <= {1'b0, data2_sr[3:1]};
else
data2_sr <= data2_sr;
always @(posedge clk or posedge reset)
if (reset)
c_int <= 1'b0;
else if (add)
c_int <= c_out;
always @(posedge clk or posedge reset)
if (reset)
c_out_final <=1'b0;
else if(add)
c_out_final <= c_out;
// Full adder
assign sum_int = data1_sr[0] ^ data2_sr[0] ^ c_int;
assign c_out = (data1_sr[0] & data2_sr[0]) | (data2_sr[0] & c_int) | (c_int & data1_sr[0]);
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always @(posedge clk or posedge reset)

if (reset)
sum_sr <= 4'h0;
else if (add)
sum_sr <= {sum_int, sum_sr[3:1]};
else
sum_sr <= sum_sr;
assign sum = sum_sr;
assign carry = c_out_final;
assign ready = ~ add;
endmodule

II Test Bench Module: Serial_adder_test.v

module serial_adder_tb;
reg load, add, clk, reset;
reg [3:0] data1, data2;
wire [3:0] sum;
wire carry, ready;
serial_adder s1(load, add, clk, reset, data1, data2, sum, carry, ready);
initial
begin
clk = 1'b1;
#250 $finish;
end
always #10 clk = ~ clk;
initial
begin
reset = 1'b0;
#5 reset = ~ reset;
#15 reset = ~ reset;
end

initial
begin
#10 data1 <= 4'he;
data2 <= 4'h9;
end
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initial
begin
load <= 1'b0;
#25 load <= 1'b1;
#15 load <= 1'b0;
end
initial
begin
add <= 1'b0;
#40 add <= 1'b1;
#80 add <= 1'b0;
end
endmodule

Following is the simulation result snapshot for the serial adder

III Constraints file for Synthesis: Constraints_sa.g

create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"]
set_clock_transition -rise 0.1 [get_clocks "clk"]
set_clock_transition -fall 0.1 [get_clocks "clk"]
set_clock_uncertainty 1.0 [get_ports "clk"]
set_input_delay -max 1.0 [get_ports "reset"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_ports "load"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_ports "add"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_ports "data1"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_ports "data2"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "sum"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "carry"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "ready"] -clock [get_clocks "clk"]

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Following is the synthesis result snapshot for the serial adder

Note: After synthesis, in addition to the command report timing -lint that is used for the verification
of the timing constraints, the command report timing -lint -verbose can be used in the rc prompt, for
the detailed observation of the errors that have occurred for the timing constraints that are applied to
the buses and their individual ports.

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b) PARALLEL ADDER
I Main Design Module: Parallel_adder.v
module padder ( x, y, c_in, sum, c_out);
input [3:0] x, y;
input c_in;
output [3:0] sum;
output c_out;
wire c1, c2, c3;
fulladd stage0 (x[0], y[0], c_in, sum[0], c1);
fulladd stage1 (x[1], y[1], c1, sum[1], c2);
fulladd stage2 (x[2], y[2], c2, sum[2], c3);
fulladd stage3 (x[3], y[3], c3, sum[3], c_out);
endmodule
module fulladd (a, b, cin, s, cout);
input a, b, cin;
output s, cout;
assign s = a^b^cin;
assign cout =(a & b)|(b & cin)|(a & cin);
endmodule

II Test Bench Module: Parallel_adder_test.v

module padder_test ;
reg [3:0] x, y;
reg c_in;
wire [3:0] sum;
wire c_out;
padder a1 (x, y, c_in, sum, c_out);
initial
begin
x = 4'b0000; y= 4'b0000; c_in = 1'b0;
#20 x = 4'b1111; y = 4'b1010;
#40 x = 4'b0011; y = 4'b0100;
#40 x = 4'b1001; y = 4'b1011;
#50 $finish;
end
endmodule

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Following is the simulation result snapshot for the parallel adder

III Constraints file for Synthesis: Constraints_pa.g

set_input_delay -max 1.0 [get_ports "x"]
set_input_delay -max 1.0 [get_ports "y"]
set_input_delay -max 1.0 [get_ports "c_in"]
set_output_delay -max 1.0 [get_ports "sum"]
set_output_delay -max 1.0 [get_ports "c_out"]

Following is the synthesis result snapshot for the parallel adder

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When double-clicked inside the blocks shown, the circuit diagram of the full adder gets displayed

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EXPERIMENT NO. 7
4-BIT COUNTERS (SYNCHRONOUS & ASYNCHRONOUS)
Aim: To compile and to simulate the Verilog code for the 4-bit synchronous and asynchronous
counters, and then to synthesize those designs for the given constraints.
Design Files: The main design modules and the respective test bench modules are given as follows,
in the order of synchronous counter, and then asynchronous counter.

a) SYNCHRONOUS COUNTER
I Main Design Module: Sync_counter.v
module s_counter (clk, reset, count);
input wire clk, reset;
output reg [3:0] count;
always @(posedge clk)
if (reset)
count <= 4'b0000;
else
count <= count + 4'b0001;
endmodule

II Test Bench Module: Sync_counter_test.v

module s_counter_test ;
reg clk, reset;
wire [3:0] count;
initial
clk = 1'b0;
always
#5 clk = ~ clk;

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s_counter m1 (clk, reset, count);

initial
begin
reset = 1'b0 ;
#15 reset =1'b1;
#30 reset =1'b0;
#220 reset =1'b1;
#15 $finish;
end
endmodule

Following is the simulation result snapshot for the synchronous counter

III Constraints file for Synthesis: Constraints_sc.g

create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"]
set_clock_transition -rise 0.1 [get_clocks "clk"]
set_clock_transition -fall 0.1 [get_clocks "clk"]
set_clock_uncertainty 1.0 [get_ports "clk"]
set_input_delay -max 1.0 [get_ports "reset"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "count"] -clock [get_clocks "clk"]

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Following is the synthesis result snapshot for the synchronous counter

When double-clicked inside the circular block, the logics get displayed as shown

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b) ASYNCHRONOUS COUNTER
I Main Design Module: Async_counter.v
module a_counter (pulse, toggle, reset, count);
input pulse, toggle, reset;
output reg [3:0] count;
wire c0, c1, c2;
assign c0 = count[0], c1 = count[1], c2 = count[2];
always @ (posedge reset or posedge pulse)
if (reset == 1'b1) count[0] <= 1'b0;
else if (toggle == 1'b1) count[0] <= ~ count[0];
always @ (posedge reset or negedge c0)
if (reset == 1'b1) count[1] <= 1'b0;
else if (toggle == 1'b1) count[1] <= ~ count[1];
always @ (posedge reset or negedge c1)
if (reset == 1'b1) count[2] <= 1'b0;
else if (toggle == 1'b1) count[2] <= ~ count[2];
always @ (posedge reset or negedge c2)
if (reset == 1'b1) count[3] <= 1'b0;
else if (toggle == 1'b1) count[3] <= ~ count[3];
endmodule

II Test Bench Module: Async_counter_test.v

module a_counter_test ;
reg pulse, toggle, reset;
wire [3:0] count ;
a_counter r1 (pulse, toggle, reset, count);
initial
pulse = 1'b0;
always
#5 pulse = ~ pulse;

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initial
begin
reset = 1'b0; toggle = 1'b0;
#10 reset = 1'b1; toggle = 1'b1;
#10 reset = 1'b0;
#190 reset = 1'b1;
#20 reset = 1'b0;
#100 reset = 1'b1;
#40 reset = 1'b0;
#250 $finish;
end
endmodule

Following is the simulation result snapshot for the asynchronous counter

III Constraints file for Synthesis: Constraints_asc.g

create_clock -name pulse -period 10 -waveform {0 5} [get_ports "pulse"]
set_clock_transition -rise 0.1 [get_clocks "pulse"]
set_clock_transition -fall 0.1 [get_clocks "pulse"]
set_clock_uncertainty 1.0 [get_ports "pulse"]
set_input_delay -max 1.0 [get_ports "reset"] -clock [get_clocks "pulse"]
set_input_delay -max 1.0 [get_ports "toggle"] -clock [get_clocks "pulse"]
set_output_delay -max 1.0 [get_ports "count"] -clock [get_clocks "pulse"]

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Following is the synthesis result snapshot for the asynchronous counter

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EXPERIMENT NO. 8
SUCCESSIVE APPROXIMATION REGISTER
Aim: To compile and to simulate the Verilog code for the successive approximation register.
Design Files:

I Main Design Module: sar.v

module sar (digitalout,done,comp,start,reset,clk);
output [3:0] digitalout;
output done;
input clk, start, reset, comp;
reg [3:0]ring_count;
reg [3:0]digital;
wire D4,set0,set1,set2,set3;
assign D4 = ring_count[0];
assign done = !D4;
always @(posedge clk or negedge reset)
begin
if (~reset)
ring_count <= 4'b1000;
else
begin
if (start)
ring_count <= 4'b1000;
else
ring_count <= (ring_count>>1);
end
end
assign set3 = ring_count[3];
assign set2 = ring_count[2];
assign set1 = ring_count[1];
assign set0 = ring_count[0];

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always @(posedge clk or negedge reset)

begin
if(~reset)
digital[3] <= 1'b1;
else
if(start)
digital[3] <= 1'b1;
else if(set3)
digital[3] <= comp;
end
always @(posedge clk or negedge reset)
begin
if(~reset)
digital[2] <= 1'b1;
else
if(start)
digital[2] <= 1'b1;
else if(set2)
digital[2] <= comp;
end
always @(posedge clk or negedge reset)
begin
if(~reset)
digital[1] <= 1'b1;
else
if(start)
digital[1] <= 1'b1;
else if(set1)
digital[1] <= comp;
end
always @(posedge clk or negedge reset)
begin
if(~reset)
digital[0] <= 1'b1;
else
if(start)
digital[0] <= 1'b1;
else if(set0)
digital[0] <= comp;
end
assign digitalout = (digital) | (ring_count);
endmodule
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II Sub Design Module: dac.v

module dac (comp,sar_out,vref_d,vin_d,clk,start);
output comp;
input clk,start;
input [3:0]sar_out;
input [63:0]vref_d;
input [63:0]vin_d;
reg comp;
real v_dac,vref,vin;
always @ (vin_d or start)
begin
vref = $bitstoreal(vref_d);
vin = $bitstoreal(vin_d);
end
always @*
begin
if(start)
comp = 1'b0;
else
begin
v_dac = (vref/15)*(sar_out);
if (vin<v_dac)
comp = 1'b0;
else
comp = 1'b1;
end
end
endmodule

III Test Bench Module: sar_tb.v

module sar_tb;
reg clk,reset,start;
reg [63:0] vref_d,vin_d;
wire done, comp;
wire [3:0] digitalout;
real vref_real = 7.5;

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sar s1 (digitalout,done,comp,start,reset,clk);
dac d1 (comp,digitalout,vref_d,vin_d,clk,start);
initial
begin
clk = 1'b1;
start = 1'b1;
#4000 $finish;
end
always #10 clk = ~clk;
initial
begin
#1;reset = 1'b1;
#10; reset = 1'b0;
#1; reset = 1'b1;
end
initial
begin
#10 ;
stimulus (0.0,0.5,vref_real,8'd5);
end
task stimulus (input analog, input step, input reference, input [7:0]delay);
real analog,step;
real reference;
begin
while(analog <= reference)
begin
repeat(delay)
@(posedge clk);
start <= 1'b0;
vref_d = $realtobits (reference);
vin_d = $realtobits (analog);
@(posedge done)
analog = analog + step;
@(posedge clk);
start <= 1'b1;
end
end
endtask
endmodule
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PROCEDURES FOR ANALOG DESIGN

CUSTOM IC DESIGN FLOW

Specifications

Schematic entry

Circuit simulation

Layout

Design rule check

Layout versus schematic

Parasitic RC extraction

Back annotation

GDS-II to foundry

Note: Schematic entry can be done either through direct circuit entry, or through VerilogA, or
through SPICE netlist. For simulation, a test circuit along with the symbol of the schematic is
required. DRC, LVS and RCX form parts of the physical verification process.
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INITIAL PROCEDURES:
1. After logging in, right click and open terminal.
2. Get into the c shell by typing the command
csh
3. Run the shellscript by typing the command
source cshrc.main
4. Move inside the respective directory using the cd command
cd cadence_analog_labs_613
5. Invoke the analog design tool by using the command
virtuoso &
After the virtuoso console opens up, maximize it. The linux terminal can be minimized.
6. In the virtuoso console, create your own library by following the steps
File New Library

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7. In the New Library window that opens up, fill in your library name (e.g.: Design2), and
then click on the option
Attach to an existing technology library

8. A selection box named Attach Library to Technology Library will open. Select gpdk180
and click on OK.

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I. STEPS FOR DESIGN ENTRY:

1. In the virtuoso console, select the following
File New Cellview
2. In the New File form that opens, browse for your library name, and in front of the Cell, fill
in the name of the schematic that is going to be entered (e.g.: inverter). Later, click on OK.

3. A new design window opens, in which the schematic has to be entered.

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4. After the schematic entry, a symbol for the schematic has to be created in the schematic
editor window, by selecting the following
Create Cellview From Cellview
During these steps, one more editor window will open up for the symbol entry. The
symbol generation procedures will be elaborated while describing the experiments.
5. After symbol creation, both the editor windows can be closed. Now for the test circuit, a
new Cellview has to be created in the virtuoso console. Again, the detailed procedures for
the test circuit are elaborated while discussing the respective experiments.
II. STEPS FOR SIMULATION AND LAYOUT:
The test circuit has to be simulated by launching ADE-L in the schematic editor window, and then by
choosing the respective analyses in ADE. The three main analyses that are performed are transient,
dc and ac. With output plotted in Y-axis, the details of these analyses are summarized below
Type of analysis
Transient
DC
AC

X-axis
Time
Input
Frequency

Observation
Waveform
Transfer characteristics
Bandwidth

After the circuit verification, the layout for the schematic has to be prepared using Layout-XL, and
the same has to be physically verified. The detailed procedures are explained with the experiments.

NOTES

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1. Abbreviations:

av

ADE Analog Design Environment

DRC Design Rule Check

ELW Error Layer Window

gpdk general process design kit

LSW Layer Selection Window

LVS

RCX RC extraction

VLW View Layer Window

2. Cadence tools used:

Virtuoso schematic editor

Virtuoso ADE - for analyses and plots

Spectre - for circuit simulation

Virtuoso layout suite

Assura DRC, LVS, RCX

assura verification

Layout Versus Schematic

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EXPERIMENT NO. 9
INVERTER analog design
Aim: To simulate the schematic of the CMOS inverter, and then to perform the physical verification
for the layout of the same.
Procedure: The three initial steps before simulation are: schematic entry, symbol entry and test
circuit entry. The procedures are as detailed below
I. DESIGN ENTRY:
1. In the schematic editor window, for the addition of instances, press i. This will open the
Add Instance window. In that window, browse for the library gpdk180, select the cell pmos
and then select the view symbol. Click on close.

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2. The properties of the selected instance are displayed in the Add Instance window. There is
no need to modify any properties for this particular experiment. Click on Hide.

3. The pmos symbol will move along with the cursor. Place it in the top mid-position, left-click
and then press Esc.

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4. Similarly place nmos device, and then press Esc.

5. Now, press w for placing wire, click on the respective nodes and connect them through
wire. Place the input and output wires as well. Complete the substrate connections also.

6. After pressing Esc, press p for adding pins to the schematic diagram. In the Add Pin
window, enter the name of the pin (e.g.: in), and ensure its direction as input.

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7. Click on Hide, and place the pin at the input. Later press Esc.

8. Similarly, place the output pin with name out and direction output.

9. Complete the schematic by placing the instances vdd and gnd, which are in the analogLib
library. Finally, click on check & save icon and observe the errors in the virtuoso console.
In the schematic window, the errors will be highlighted with yellow boxes. Move those boxes,
correct the errors, and click on check & save. Correct all the errors that are reported.

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10. After the schematic entry is finished, a symbol for the design has to be created. For this
purpose, click on Create and follow the procedure
Create Cellview From Cellview

The name comes by default, along with the other options. Click on OK.
11. Another window opens, which shows the input and output pin configurations. Click on OK.

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12. A symbol editor window opens up with the default symbol.

13. The default symbol can be deleted and the symbol as per our convention can be created. For
this purpose, click on the green colored edge of the symbol. Now the color of the selected part
changes into magenta. Press Delete and click again on the edge. The default green box gets
deleted, and a new symbol can be created. Now press Esc to come out of the delete mode.

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14. On the pulldown menu, Select Create Shape Line and click on the editor window. Use
the mouse to create the shape of a triangle. Alternatively, you can select Create Shape
Polygon as well. Use right click for making the line slant.

15. After the triangle is complete, select Create Shape Circle, and then bring the cursor in
front of the triangle, and click once. Release the finger and move the mouse. After the circle is
generated, click once again to place it.

16. Now, click on the output wire and drag it in front of the circle. Similarly, join the output pin
to the wire. Later, select Create Selection box and click on Automatic. The tool will adjust
the selection box around the created symbol automatically. You can similarly select and drag
the port names to the respective places. Finally, check & save and observe the errors.

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17. After the schematic and symbol entries, both the editor windows can be closed. Now for
creating a test circuit, create a new cellview from the virtuoso console, and give the name as
inverter_test. When the editor window opens, press i, browse for your library and select
the inverter symbol which was created earlier. Place it in the middle of the screen.

To ensure that the symbol is loaded correctly, you can click on the symbol and then press
Shift E. The schematic editor will move one level down, and the inverters circuit entered
earlier will be displayed on the screen. To come back to the symbol, press Ctrl E; the
symbol will be displayed back. Press Esc to unselect the symbol.
18. Place wires at the input and output, and place an output pin as well. These wires are needed
during simulation, to plot the voltage waveforms.

19. Press i, browse analogLib library and select vpulse and its symbol.

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20. In the property window, enter Voltage1 as 0 and Voltage2 as 1.8. Similarly enter Period as
20n and Pulse width as 10n, without the space in between. No need to enter the units; they
appear automatically. Place the vpulse at the input wire. Connect gnd at the other end.

21. Similarly, browse for the instance vdc, and enter its DC voltage as 1.8.

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22. Place vdc at the front, and connect vdd and gnd accordingly. Finally check & save.
The test circuit is complete now, and ready to be simulated.

Note: The library gpdk180 contains the technology dependent components (180nm), and the library
analogLib contains the technology independent components.
Whenever a component needs to be selected, place the cursor on the component and click on it. The
selected components boundary turns into magenta color. Now the properties of the component can
be verified by pressing q, after which the property window opens.
To zoom a particular portion of the screen, right click, hold, and move the mouse. A yellow colored
boundary will be drawn on the screen. When the finger is released, the highlighted portion gets
zoomed. To come back to the original screen, press f. Alternatively, Ctrl Z and Shift Z can be
used, to zoom in and zoom out.
After the symbol is entered, Shift and E can be used together to move one level down, to view the
schematic diagram. Later, Ctrl and E can be used together to move one level up, to the symbol.
The hot key functions that are used during design entry are summarized as follows
Hot key
i
w
p
m
q
r
u
c
f
Esc
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Function
Instance
Wire
Pin
Stretch
Property
Rotate
Undo
Copy
Fit to screen
Exit
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II. SIMULATION:
1. In the test circuits editor window, click on Launch ADE L. A new window will open.

2. Click on Analyses Choose. A new window will open, in which select tran. Fill the stop
time as 100n, and select liberal. Later, click on Apply.

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3. Now select dc on the Choosing Analyses window, and click on Save DC Operating Point.
Click on the Component Parameter. A Select Component option will pop up.

4. Double click on Select Component. The ADE window gets minimized, and the schematic is
shown. Click on the component vpulse. In the new window that opens up, click on the top
most parameter dc and then click on OK.

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5. Ensure that the component name and parameter name are updated. Now in the Sweep range,
enter 0 and 1.8 in the Start and Stop options respectively. Later, click on Apply.

6. In the ADE window, ensure that the Analyses fields are updated for tran and dc.

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7. Now to select the stimulus and response points, in the ADE window, click on Outputs To
be plotted Select on Schematic. In the schematic window, click on input and output
wires. These wires will become dotted lines when selected. Later, press Esc.

8.

In the ADE window, check that the Outputs fields are updated. Now click on Simulation
Netlist and Run. The waveform window will open and the simulation results are displayed.
Transient response is displayed on the left side and DC response on the right.
Click on the transient response waveform and then click on the fourth icon at the top (Strip
chart mode). The input and output waveforms are displayed separately. You can right click
on each waveform, and then edit the properties of the display such as color and appearance.
Similarly, the transfer characteristics can be observed at the right hand side.

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III. LAYOUT:
1. For preparing the layout of the inverter, all the other windows can be closed, except for the
virtuoso console. In the console, open the schematic of the inverter and click on Launch
Layout XL. In the Startup Option, click on OK.

2. In the New File option, the tool selects the view as layout by default. Click on OK.

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3. The tool opens the LSW and the Layout suite.

4. Maximize the layout suite and click on Connectivity Generate All from Source. A
Generate Layout window will open, with default attributes. Click on OK.

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5. The layout suite displays a cyan colored box in the first quadrant, which is the Photo-Resist
boundary. In addition, in the fourth quadrant, the default layouts of pmos and nmos transistors
are displayed, along with four blue squares, which are the nodes - vdd, gnd, input & output.

6. Press Shift F to see all the layers within the default layout. Hold the right click and move
the mouse to zoom a selected portion, and observe the layout carefully. The color details are
Orange border: n-well, Red border: p-diffusions boundary, Yellow border: n-diffusions
boundary, Green: diffusion, Rose: polysilicon, Yellow square: contact cut, Blue: metal1.

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7. Click on the pmos device and drag it into the PR boundary. The layout can be moved either
vertically or horizontally, not diagonally. During this movement, the tool keeps displaying the
connections of the terminals with the nodes. After placing the pmos device, place the nmos
device below it. If the space is insufficient, the PR boundary can be enlarged, through the top
and the right edges. For this purpose, press s and click on the edge of the PR boundary. (s
is for stretch, in the layout suite). The selected edge will turn into magenta color. Now release
the finger and move the mouse till the desired area, and click again. Later, press Esc.

8. After placing the devices, zoom the space in between the transistors. In the LSW, select Poly.
Now in the layout suite, press p, place the mouse at the middle of the gates lower contact
of pmos device, and click once. (p is for path, in the layout suite). Release the finger and
move the mouse downwards. The poly path will move along with the mouse. Move the mouse
until the gate area of the nmos device gets overlapped. Bring the cursor exactly to the middle
of the path and double click. The poly path between the gates gets realized. The area can be
zoomed further, and the devices can be moved, for the exact overlapping of the poly layers.

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9. In the LSW, select Metal1. Using the same procedure, draw the paths for vdd at the top and
gnd at the bottom. Later, using the same metal path, connect the source of pmos device to
vdd and that of nmos device to gnd. Finally, connect both the drains for the output path.

10. Now move to the fourth quadrant where the four blue squares are displayed. Click on one of
them; it will turn into magenta color. Press q, and then click on Connectivity, to see its
properties. If it is vdd, drag it and place it on the upper metal path. Later, place the gnd on the
lower path; similarly, place the output pin. Now, place the input pin in front of the poly and
connect through a poly path.

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11. Now, for connecting the input metal pin to the poly path, a via needs to be placed. Hence, in
the layout suite click Create Via. In the Via Definition pull-down menu, select the via
M1_POLY1. Click on Hide, and place the via on the input pin. Press Esc.

12. Similarly, for the substrate connections, select the via M1_NWELL and place it touching the
n-well, and connect it to vdd through a metal path. Later, place the via M1_PSUB on the
vss path, for the substrate connection of nmos device; the Black background itself indicates
the p-substrate. (p-device resides on n-well and n-device resides directly on p-substrate).

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13. As the layout is now complete, its verification can be performed. In the layout suite, click on
Assura Run DRC. Give the run name as inverter and verify the output. If there are
errors, the tool will highlight those areas in White color. The errors will be displayed in the
ELW, and the location of each error can be known, by selecting the error in ELW, and then
clicking on the arrow mark available in ELW. Correct those errors and rerun DRC.

14. After the DRC check, click on Assura Run LVS, and verify the output. Correct the errors.

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15. After the LVS check, click on Assura Run RCX. Click OK on the form that appears.

16. After the RCX is run, the output is saved in your library as av_extracted. In the virtuoso
console, open the inverter file with view as av_extracted, and observe the output. The
layout can be enlarged and the parasitic components can be observed. Each components value
can be checked, by selecting the component and pressing q.

If the parasitic component values are beyond the limits, then the layout can be optimized in the layout
suite, for the reduction of the parasitic component values; later on, the layout can be back-annotated
with the existing parasitic components, and simulation can be performed, for verifying the output.
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EXPERIMENT NO. 10
COMMON SOURCE & COMMON DRAIN AMPLIFIERS
Aim: To simulate the schematic diagrams of the common source and common drain amplifiers, and
then to perform the physical verification for the layouts of the same.
Circuit diagrams:
a) Common source amplifier

Vdd

Vbias

Vout
Vin

Vss
b) Common drain amplifier
Vdd

Vin

Vout
Vbias

Vss

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Procedure:
a) COMMON SOURCE AMPLIFIER:
1. For the schematic entry, select pmos device from gpdk180 library, and edit the properties as
Length = 1 micron and Width = 50 microns. (type u for micron). Similarly, place the nmos
device with Length = 1 micron and Width = 20 microns. Place the wires for connection.

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2. Place vdd and vss. Later, place the input pins for Vbias and Vin, and output pin for Vout.
Click on check & save and correct the errors, if any.

3. Create the symbol for the schematic; the default symbol itself can be used.

4. Close the editor windows, and create a new schematic in the virtuoso console, for the test
circuit. In the test circuit, retrieve the symbol from your library, and then place vsin from
the analogLib library for the input signal, with the attributes entered as
AC magnitude = 1mV, Amplitude = 5mV and Frequency = 1KHz. (Dont enter the units).
The AC magnitude is used for ac analysis, and the Amplitude is used for transient analysis.
Place a wire in between vsin and vin.
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5. Now, place vdc for the the biasing voltage, with DC voltage as -0.9V. Place two more
instances of vdc, to be utilized for the attributes of vdd and vss, and edit their values as 2.5V
and -2.5V respectively. Connect the respective vdd and vss symbols, along with gnd. Finally,
place a wire and pin for the output.

6. After saving, launch ADE-L and enter the analyses requirements, as per the procedures given
in the previous experiment. For transient analysis, as the input signal is of period 1ms, enter
the Stop Time as 10m. For dc analysis, Select Component vsin, select dc, and enter the
Sweep Range as Start -2.5 and Stop 2.5. (Units will appear automatically). As this particular
experiment is on amplifiers, ac analysis is also required for finding the bandwidth. Hence,
after tran and dc, click on ac, and enter the Sweep Range of Frequency as 100 Hz till 1GHz.
Select the Sweep Type as Logarithmic and enter the Points per Decade as 20.

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7. Finally, select the wires on the schematic for plotting the outputs, and click on the PLAY icon
in the ADE window, for netlist & run. The output will appear, and the waveforms can be
edited in different colors, for better viewing.
In the Transient Response, for measuring the amplitude, press d. Now two delta cursors are
made available on the screen, one with red pointer and the other with green pointer. Move one
cursor to the positive peak of the waveform and the other cursor to the negative peak. The
values (time & amplitude) corresponding to the cursor positions are displayed at the bottom,
red one first and green one next. The difference in y-values gives the peak-to-peak amplitude.
(The input amplitude in this case is 10 mVpp, as the amplitude given was 5mV). The dx | dy
is also displayed at the right side, and the dy value represents the amplitude.

For measuring the bandwidth, move the trace cursor in the AC Response to the point which
corresponds to 0.707 Vmax, and the display indicates the frequency, which is the bandwidth
corresponding to the -3dB gain.
The DC Response can be observed for the quiescent operation of the amplifier.
8. The gain and phase response can be obtained separately, by following the procedure in the
ADE window as: Results Direct plot AC Gain & Phase. In the schematic window,
click on the output wire first and then on the input wire. Later, press Esc. The phase and gain
curves are displayed in a separate window. Click on the output and then on Strip chart mode,
and observe the output. The gain is displayed in dB, and hence, to check the bandwidth of the
amplifier, the trace cursor can be moved to the -3dB position on the gain curve.
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9. After the completion of the simulation, close all the windows except the virtuoso console. In
the console, open the schematic file of the amplifier and launch the layout suite. Proceed with
the steps as mentioned in the previous experiment, and place the respective paths, pins and the
vias. For change of direction of any path, single click at the center, and then change direction.

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10. As the PMOS device is of 50 microns length, and as substrate connections of the device are
required at every 10 microns (as per the design rules), get a ruler on the screen by pressing
K. Click the mouse adjacent to the top of the device, and move the cursor till the lower end
of the device. Click again to place the ruler. Now, place the via M1_NWELL at every 10
micron distance. Connect all of these vias to vdd by means of the metal path.

11. Similarly, place the via M1_PSUB near the NMOS device, and connect it to vss. Place one
more via at another 10 micron distance.

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12. Press Shift K to delete all the rulers. Save the layout, and run the DRC, LVS and RCX tests.

b) COMMON DRAIN AMPLIFIER:

1. The procedures remain similar to the previous experiment. Enter the schematic diagram with
the upper NMOS device dimensions as Length = 1 micron & Width = 50 microns, and the
lower NMOS device dimensions as Length = 1 micron & Width = 10 microns.
It is not mandatory that the vdd and vss symbols from the analogLib library have to be
used directly. They can be declared as pins, and their voltages can be directly specified in the
test circuit. This alternative method is followed in this experiment, as shown in the circuit
diagram below. Complete the other connections as per the circuit diagram, and click on
check & save and correct the errors, if any.
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2. During the symbol generation, the vdd pin can be placed as the top pin and the vss pin can be
placed as the bottom pin.

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3. The symbol that is generated can be used directly. Click on check & save.

4. The test circuit is similar to the common source amplifier except that vdc can be directly
connected to the vdd and vss pins, and their voltages can be edited respectively. The biasing
voltage for the common drain amplifier is -1.8V.

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5. Perform the simulation on the test circuit, and verify the gain and phase. As the circuit is
similar to the Emitter follower circuit of BJT, there will be no voltage gain as such.

6. As the next step, complete the layout and perform the physical verification. The assura
verification_extracted layout is as shown below

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EXPERIMENT NO. 11
DIFFERENTIAL AMPLIFIER
Aim: To simulate the schematic diagram of the differential amplifier, and then to perform the
physical verification for the layout of the same.
Procedure:
1. Perform the schematic entry as per the following specs: All of the transistors will have the
length = 1 micron; the PMOS load transistors with width = 15 microns; the NMOS input
transistors with width = 3 microns; and finally, the NMOS biasing transistors with width = 4.5
microns. While placing the PMOS transistors, the Sideways option can be used, for having
their position as shown in the schematic diagram.

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2. Create a symbol for the schematic diagram, and place the input V2 as the right pin.

3. Complete the test circuit by placing the current source, the input signal and the power
supplies. Initially, V1 can be used as the input, and V2 can be grounded at that time. The
current source is available as idc in the analogLib library; set its DC current as 30 A.
Connect its positive end to vdd and negative end to the Idc input.

4. For simulation, the transient and dc analyses details remain the same as that of the previous
experiment. In the ac analysis, the frequency range from 100 Hz till 100 MHz.
As V1 is the non-inverting input, the output will be in phase with the input, and the circuit
will provide around 40 dB gain. This can be verified initially, and then the test circuit can be
altered with grounded V1, and input provided to V2. The inverting operation of the circuit can
be verified. The gain and phase responses can also be verified.
The following screenshots indicate both of the functional operations NHCE

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Non-inverting amplifier: (V1 as input)

Its phase and gain response:

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Inverting amplifier: (V2 as input)

5. After the simulation, complete the layout and perform the physical verification. The assura
verification_extracted layout is shown below

.
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EXPERIMENT NO. 12
OPERATIONAL AMPLIFIER
Aim: To simulate the schematic diagram of the operational amplifier, and then to perform the
physical verification for the layout of the same.
Procedure:
1. To obtain the operational amplifiers circuitry, in this particular design, a common source
amplifier with PMOS driver is cascaded with the differential amplifier. Due to the addition of
this high-gain stage, V1 now becomes the inverting input and V2 becomes the non-inverting
input. Select PMOS device width as 50 microns and NMOS device width as 20 microns, the
length of both the transistors remaining at 1 micron. Connect the gate of the NMOS device to
Idc, and complete the substrate and power supply connections. Connect an output pin.
In addition, to ensure the safer phase margin, a compensating capacitor is added between the
gate and drain of the PMOS driver. Select the component mimcap from gpdk180 library,
with its width and length set at 10 microns, and its value will become 104 fF. (mim stands for
metal-insulator-metal; this capacitor is formed in between the two metal layers).

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2. Create a symbol for the op-amp, as shown. Take Idc pin at the top, and widen the gap between
the input pins.

3. Close both the editor windows, and then create the test circuit, initially for the inverting
amplifier, as shown. For the resistors, use polyres from gpdk180 library, with the values 1k
ohms and 500k ohms. Connect the 30 A current source for Idc.

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4. Run the simulation with the same details as that of the previous experiment, except that
choose the frequency range of 100 Hz to 10 MHz for the ac analysis. Verify the output.

5. Verify the phase and gain responses as well, and find out the bandwidth of the op-amp. Vary
the value of the feedback resistor, for obtaining different gains, and verify the bandwidth.

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6. Later, change the input to V2, and check the performance in the non-inverting mode.

7. Verify its phase and gain responses as well. Check the bandwidth for different gains, by
varying the value of the feedback resistor.

8. After the simulation, complete the layout and perform the physical verification.
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EXPERIMENT NO. 13
R-2R DAC
Aim: To simulate the schematic diagram of the R-2R digital-to-analog converter, and then to perform
the physical verification for the layout of the same.
Procedure:
1. Retrieve the op-amp symbol from library, and complete the schematic diagram for the R-2R
DAC, as shown. Connect the op-amp as the buffer amplifier.

2. Create a symbol for the same, as shown below

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3. Use the symbol to create the test circuit, with the input signals connected. Select vpulse
from analogLib library, with Voltage 1 as 0 and Voltage 2 as 2. Place four instances of the
same to the four inputs, and then edit the properties of each instance, as follows
Input
D0
D1
D2
D3

Period
10n
20n
40n
80n

Pulse width
5n
10n
20n
40n

4. Perform the simulation only for the transient analysis with the Stop time as 100 ns.

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5. Change the timings of the input signals from ns to ms, and run the simulation again.

The difference in output is observed, because of the limitation in slew rate of the op-amp. As the
bandwidth of the op-amp is very less, it is not sensitive to the signals of nanosecond width. Hence,
the staircase waveform is distinctly observed in the millisecond width timing, for the input signals
from 1111 till 0000.
The overshoots in between the steps are due to the rise time and fall time values of the inputs, which
are assigned by default, by the tool. For the avoidance of these overshoots, the rise and fall times for
each input signal have to be exclusively specified.
6. After the simulation, complete the layout and perform the physical verification.
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