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VLSI BASIC LANGUAGE ---- VERILOG

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Verilog

VLSI BASIC LANGUAGE ---- VERILOG

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Copyright © 2003 Sun Microsystems, Inc. 2550 Garcia Avenue, Mountain View, California 94043-1100 U.S.A. Allrights reserved. This product or documents protected by copyrightand distributed under licenses restricting its use, copying, distribution and decompilation. No part of this product or document may be reproduced in any form by any means without prior written authorization of Sun and its licensors, if any. Portions of this product may be derived from the UNIX® system and from the Berkeley 4.3 BSD system, licensed from the University of California, Third-party software, including font technology in this product, is protected by copyright and licensed from Sun's Suppliers. RESTRICTED RIGHTS LEGEND: Use, duplication, or disclosure by the government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013 and FAR 2.227-19. ‘The product described in this manual may be protected by ane or more U.S. patents, foreign patents, or pending applications TRADEMARKS Sun, Sun Microsystems, the Sun logo, and Solaris are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and may be protected as trademarks in other countries. UNIX is.a registered trademark in the United States and other countries, exclusively licensed through X/Open Company, Ltd. OPEN LOOK is a registered trademark of Novell, Inc. PostScript and Display PostScript are trademarks of Adobe Systems, Inc. Verilog is a registered trademark of Cadence Design Systems, Inc. Verilog-XL is a trademark of Cadence Design Systems, Inc. VCS is a trade- mark of Viewlogic Systems, Inc. Magellan is a registered trademark of Systems Science, Inc. VirSim is a trademark of Simulation Technologies, Inc. Signalscan is a trademark of Design Acceleration, Inc. All other product, service, or company names mentioned herein are claimed as trademarks and trade names by their respective companies All SPARC trademarks, including the SCD Compliant Logo, are trademarks or registered trade- marks of SPARC International, Inc. in the United States and may be protected as trademarks in other countries. SPARCcenter, SPARCcluster, SPARCompiler, SPARCdesign, SPARC811, SPAR- Cengine, SPARCprinter, SPARCserver, SPARCstation, SPARCstorage, SPARCworks, micro- SPARC, microSPARC-Il, and UltraSPARC are licensed exclusively to Sun Microsystems, Inc. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsys- tems, Inc. The OPEN LOOK™ and Sun™ Graphical User Interfaces were developed by Sun Microsystems, Inc, for its users and licensees. Sun acknowledges the pioneering efforts of Xerox in researching and developing the concept of visual or graphical user interfaces for the computer industry. Sun holds a non-exclusive license from Xerox te the Xerox Graphical User Interface, which license also covers Sun's licensees who implement OPEN LOOK GUI's and otherwise comply with Sun's written license agreements. X Window System is a trademark of X Consortium, Inc. Copyright x The publisher offers discounts on this book when ordered in bulk quantities. For more information, contact: Corporate Sales Department, Prentice Hall PTR, One Lake Street, Upper Saddle River, NJ 07458. Phone: 800-382-3419; FAX: 201- 236-7141. E-mail: . Production supervisor: Wil Mara Cover designer: Nina Scuderi Cover design director: Jemy Votta Manufacturing manager: Alexis R. Heyat-Long Acquisitions editor: Gregory G. Doench Printed in the United States of America 10987654321 SunSoft Press A Prentice Hall Title Dedication Ta Anu, Adiiya, and Sabi, Thank you for everything To our faites, Thank you for your constant encouragement and support. xi About the Author Samir Palnitkar is currently the President of Jamba Systems, Inc., a leading ASIC design and ver- ification services company which specializes in high-end designs for microprocessor, networking, and communications applications. Mr. Palnitkar is a serial entrepreneur. He was the founder of Integrated Intellectual Property, Inc., an ASIC company that was acquired by Lattice Semiconductor, Inc. Later he founded Obongo, Inc., an e-commerce software firm that was acquired by AOL Time Warmer, Inc. Mr. Palnitkar holds a Bachelor of Technology in Electrical Engineering from Indian Institute of Tech- nology, Kanpur, a Master's in Electrical Engineering from University of Washington, Seattle, and an MBA degree from San Jose State University, San Jose, CA. Mr. Palnitkar is a recognized authority on Verilag HDL, modeling, verification, logic synthesis, and EDA-based methodologies in digital design. He has worked extensively with design and verification on various successful microprocessor, ASIC, and system projects. He was the lead developer of the Verilog framework for the shared memory, cache coherent, multiprocessor architecture, popu- larly known as the UltraSPARC Port Architecture, defined for Sun's next generation UltraSPARC- based desktop systems. Besides the UltraSPARC CPU, he has worked on a number of diverse design and verification projects at leading companies including Cisco, Philips, Mitsubishi, Matorola, National, Advanced Micro Devices, and Standard Microsystems. Mr. Painitkar was also a leading member of the group that first experimented with cycle-based simulation technology on joint projects with simulator companies. He has extensive experience with a variety of EDA tools such as Verilag-NC, Synopsys VCS, Specman, Vera, System Verilog, Syn- opsys, SystemC, Verplex, and Design Data Management Systems. Mr. Palnitkar is the author of three US patents, one far a novel method to analyze finite state ma- chines, a second for work on cycle-based simulation technology and a third(pending approval) for a unique e-commerce tool. He has also published several technical papers. In his spare time, Mr. Palnitkar likes to play cricket, read books, and travel the world xii List of Figures Figure 1-1 Typical Design Flow Figure 2-1 Top-down Design Methadology Figure 2-2 Bottom-up Design Methodology Figure 2-3 Ripple Carry Counter Figure 2-4 T-flipflop Figure 2-5 Design Hierarchy Figure 2-6 Stimulus Block Instantiates Design Black Figure 2-7 Stimulus and Design Blocks instantiated in a Dummy Top-Level Module Figure 2-8 Stimulus and Output Waveforms Figure 3-1 Example of Nets Figure 4-1 Components of a Verilog Module Figure 4-2 SR Latch Figure 4-3 lO Ports for Top and Full Adder Figure 4-4 Port Connection Rules Figure 4-5 Design Hierarchy for SR Latch Simulation Figure 5-1 Basic Gates Figure 5-2 Buf and Not Gates Figure 5-3 Gates Bufif and Natif Figure 5-4 4-to-1 Multiplexer Figure 5-5 Logic Diagram for Multiplexer Figure 5-6 1-bit Full Adder Figure 5-7 4-bit Ripple Carry Full Adder Figure 8-8 Module D Figure 5-9 Waveforms for Delay Simulation Figure 6-1 Delays Figure 6-2 4-bit Ripple Carry Counter Figure 6-3 T-flipflop Figure 6-4 Negative Edge-Triggered D-flipflop with Clear Figure 6-5 Master-Slave JK-flipflop Figure 6-6 4-bit Synchronous Counter with clear and count_enable Figure 7-1 FSM for Traffic Signal Controller Figure 9-1 Debugging and Analysis of Simulation with VCD File Figure 10-1 Distributed Delay Figure 10-2 Lumped Delay List of Figures xiii Figure 10-3 Pin-to-Pin Delay Figure 10-4 Parallel Connection Figure 10-5 Full Connection Figure 10-6 Setup and Hold Times Figure 10-7 Delay Back-Annotation Figure 11-1 NMOS and PMOS Switches Figure 11-2 CMOS Switch Figure 11-3 Bidirectional Switches Figure 11-4 Gate and Switch Diagram for Nor Gate Figure 11-5 2-to-1 Multiplexer, Using Switches Figure 11-6 CMOS flipflop Figure 11-7 CMOS Inverter Figure 12-1 Parts of UDP Definition Figure 12-2 4-to-1 Multiplexer with UDP Figure 12-3 Level-Sensitive Latch with clear Figure 12-4 Edge-Sensitive D-flipflop with clear Figure 13-1 PLI Interface Figure 13-2 General Flow of PLI Task Addition and Invecation Figure 13-3 Conceptual Internal Representation of a Module Figure 13-4 2-to-1 Multiplexer Figure 13-5 Internal Data Representation of 2-to-1 Multiplexer Figure 13-6 Role of Access and Utility Routines Figure 14-1 Designer's Mind as the Logic Synthesis Too! Figure 14-2 Basic Computer-Aided Logic Synthesis Process Figure 14-3 Multiplexer Description Figure 14-4 Logic Synthesis Flow from RTL to Gates Figure 14-5 Area vs. Timing Trade-off Figure 14-6 Gate-Level Schematic for the Magnitude Comparator Figure 14-7 Horizontal Partitioning of 16-bit ALU Figure 14-8 Vertical Partitioning of 4-bit ALU Figure 14-9 Parallelizing the Operation of an Adder Figure 14-10 Finite State Machine for Newspaper Vending Machine Figure 14-11 Gate-Level Schematic for the Vending Machine Figure 15-1 Traditional Verification Flow Figure 15-2 Architectural Modeling Figure 15-3 Components of a Functional Verification Environment Figure 15-4 Interaction between HVL and Verilog Simulators Figure 15-5 Hardware Acceleration Figure 15-6 Hardware Emulation Figure 15-7 Assertion Checks Figure 15-8 Formal Verification Flow Figure 15-9 Semi-formal Verification Flow Figure 15-10 Equivalence Checking List of Figures xiv Figure F-1 FIFO Input/Output Ports Figure F-2 DRAM Input/Output Ports xv Table 3-1 Value Levels Table 3-2 Strength Levels Table 3-3 Special Characters Table 3-4 String Format Specifications Table 5-1 Truth Tables for And/Or Gates Table 5-2 Truth Tables for Buf/Not Gates Table 5-3 Truth Tables for Bufif/Notif Gates Table 6-1 Operator Types and Symbols Table 6-2 Equality Operators Table 6-3 Truth Tables for Bitwise Operators Table 6-4 Operator Precedence Table 8-1 Tasks and Functions Table 11-1 Logic Tables tor NMOS and PMOS Table 11-2 Strength Reduction by Resistive Switches Table 11-3 Delay Specification on MOS and CMOS Switches Table 11-4 Delay Specification for Bidirectional Switches Table 12-1 UDP Table Shorthand Symbols Table 13-1 Specifications for $my_stop_finish Table 14-1 Verilog HDL Constructs for Logic Synthesis Table 14-2 Verilog HDL Operators for Logic Synthesis Table A-1 Strength Levels Table B-1 Handle Routines Table 8-2 Next Routines ‘Table 8-3 Value Change Link Routines Table B-4 Fetch Routines Table 8-5 Utility Access Routines Table B-6 Modify Routines Table B-7 Get Calling Task/Function Information ‘Table 8-8 Get Argument List Information Table 8-9 Get Parameter Values Table B-10 Put Parameter Values Table 8-11 Monitor Parameter Value Changes Table B-12 Synchronize Tasks Table B-13 Long Arithmetic List of Tables List of Tables xvi Table B-14 Display Messages Table B-15 Miscellaneous Utility Routines Table 8-16 Housekeeping Tasks xvii List of Examples Example 2-1 Module Instantiation Example 2-2 lilegal Module Nesting Example 2-3 Ripple Carry Counter Tap Block Example 2-4 Flipflop T_FF Example 2-5 Flipflop D_F Example 2-6 Stimulus Block Example 2-7 Output of the Simulation Example 3-1 Example of Register Example 3-2 Signed Register Declaration Example 3-3 $display Task Example 3-4 Special Characters Example 3-5 Monitor Statement Example 3-6 Stop and Finish Tasks Example 3-7 ‘define Directive Example 3-8 ‘include Directive Example 4-1 Components of SR Latch Example 4-2 List of Ports Example 4-3 Port Declarations Example 4-4 Port Declarations for DFF Example 4-5 ANSI C Style Port Declaration Syntax Example 4-6 Illegal Port Connection Example 4-7 Connection by Ordered List Example 4-8 Hierarchical Names Example 5-1 Gate Instantiation of And/Or Gates Example 5-2 Gate Instantiations of Buf/Not Gates Example 5-3 Gate instantiations of Bufif/Notif Gates Example 5-4 Simple Array of Primitive Instances Example 5-5 Verilog Description of Multiplexer Example 5-6 Stimulus for Multiplexer Example 5-7 Verilog Description for 1-bit Full Adder Example 5-8 Verilog Description for 4-bit Ripple Carry Full Adder Example 5-9 Stimulus for 4-bit Ripple Carry Full Adder Example 5-10 Types of Delay Specification Example 5-11 Min, Max, and Typical Delay Values List of Examples xviii Example 5-12 Verilog Definition for Module D with Delay Example 5-13 Stimulus for Module D with Delay Example 6-1 Examples of Continuous Assignment Example 6-2 4-to-4 Multiplexer, Using Logic Equations Example 6-3 4-to-1 Multiplexer, Using Conditional Operators Example 6-4 4-bit Full Adder, Using Dataflow Operators Example 6-5 4-bit Full Adder with Garry Lookahead Example 6-6 Verilog Code for Ripple Counter Example 6-7 Verilog Code for T-flipflop Example 6-8 Verilog Code for Edge-Triggered D-flipflop Example 6-9 Stimulus Module for Ripple Counter Example 7-1 initial Statement Example 7-2 Initial Value Assignment Example 7-3 Combined Port/Data Declaration and Variable Initialization Example 7-4 Combined ANSI C Port Declaration and Variable Initialization Example 7-5 always Statement Example 7-8 Blocking Statements Example 7-7 Nonblocking Assignments Example 7-8 Nonblocking Statements to Eliminate Race Conditions Example 7-9 Implementing Nonblocking Assignments using Blocking Assignments Example 7-10 Regular Delay Control Example 7-11 Intra-assignment Delays Example 7-12 Zero Delay Control Example 7-13 Regular Event Control Example 7-14 Named Event Control Example 7-15 Event OR Control (Sensitivity List) Example 7-16 Sensitivity List with Comma Operator Example 7-17 Use of @* Operator Example 7-18 Conditional Statement Examples Example 7-19 4-to-1 Multiplexer with Case Statement Example 7-20 Case Statement with x and z Example 7-21 casex Use Example 7-22 While Loop Example 7-23 For Loop Example 7-24 Repeat Loop Example 7-25 Forever Loop Example 7-26 Sequential Blocks Example 7-27 Parallel Blocks Example 7-28 Nested Blocks Example 7-29 Named Blocks Example 7-30 Disabling Named Blocks Example 7-31 Bit-wise Xor of Two N-bit Buses Example 7-32 Generated Ripple Adder List of Examples xix Example 7-33 Parametrized Multiplier Using Generate Conditional Example 7-34 Generate Case Example Example 7-35 Behavioral 4-to-1 Multiplexer Example 7-36 Behavioral 4-bit Counter Description Example 7-37 Traffic Signal Controller Example 7-38 Stimulus for Traffic Signal Controller Example 8-1 Syntax for Tasks Example 8-2 Input and Output Arguments in Tasks Example 8-3 Task Definition using ANSI C Style Argument Declaration Example 8-4 Direct Operation on reg Variables Example 8-5 Re-entrant (Automatic) Tasks Example 8-6 Syntax for Functions Example 8-7 Parity Calculation Example 8-8 Function Definition Using ANSI C Style Argument Declaration Example 8-9 Left/Right Shifter Example 8-10 Recursive (Automatic) Functions Example 8-11 Constant Functions Example 8-12 Signed Functions Example 9-1 D-Flipflop with Procedural Continuous Assignments Example 9-2 Defparam Statement Example 9-3 ANSI C Style Parameter Declaration Example 9-4 Module Instance Parameter Values Example 9-5 Conditional Compilation Example 9-6 Conditional Execution with $test$plusargs Example 8-7 Conditional Execution with $valueSplusargs Example 9-8 Time Scales Example 9-9 File Descriptors Example 9-10 Displaying Hierarchy Example 9-11 Strobing Example 9-12 Random Number Generation Example 9-13 Generation of Positive and Negative Numbers Example 9-14 Initializing Memory Example 9-15 VCD File System Tasks Example 10-1 Distributed Delays. Example 10-2 Lumped Delay Example 10-3 Pin-to-Pin Delay Example 10-4 Paraliel Connection Example 10-5 Full Connection Example 10-8 Specparam Example 10-7 Conditional Path Delays Example 10-8 Path Delays Specified by Rise, Fall and Turn-off Values Example 10-9 Path Delays with Min, Max, and Typical Values Example 11-1 instantiation of NMOS and PMOS Switches List of Examples Xx Example 11-2 Instantiation of a CMOS Switch Example 11-3 instantiation of Bidirectional Switches Example 11-4 Switch-Level Verilog for Nor Gate Example 11-5 Switch-Level Verilog Description of 2- Example 11-6 CMOS Inverter Example 11-7 CMOS flipflop Example 12-1 Primitive udp_and Example 12-2 ANSI C Style UDP Declaration Example 12-3 Primitive udp_or Example 12-4 Instantiation of udp Pri Example 12-5 Verilog Description of 4-to-1 Multiplexer with UDP Example 12-6 Stimulus for 4-to-1 Multiplexer with UDP Example 12-7 Verilog Description of Level-Sensitive UDP Example 12-8 ANSI C Style Port Declaration for Sequential UDP Example 12-9 Negative Edge-Triggered D-tlipflop with clear Example 12-10 T-flipflop with UDP Example 12-11 instantiation of T_FF UDP in Ripple Counter Example 13-1 Verilog Description of 2-to-1 Multiplexer Example 13-2 PLI Routine to get Module Port List Example 13-3 PL! Routine to Monitor Nets for Value Changes Example 13-4 Consumer Routine for VCL Example -4 Multiplexer itives Example 13-5 User C Routine my_stop_finish Using Utility Routines Example 14-1 RTL for Magnitude Comparator Example 14-2 Gate-Level Description for the Magnitude Comparator Example 14-3 Stimulus for Magnitude Comparator Example 14-4 Simulation Library Example 14-5 Output from Simulation of Magnitude Comparator Example 14-6 RTL Description for Newspaper Vending Machine FSM Example 14-7 Optimized Gate-Level Netlist for Newspaper oxi Foreword From a modest beginning in early 1984 at Gateway Design Automation, the Verilog hardware de- scription language has become an industry standard as a result of extensive use in the design of integrated circuit chips and digital systems. Verilog came into being as a proprietary language sup- ported by a simulation environment that was the first to support mixed-level design representations comprising switches, gates, RTL, and higher levels of abstractions of digital circuits. The simulation environment provided a powerful and uniform method to express digital designs as well as tests that were meant to verify such designs. There were three key factors that drove the acceptance and dominance of Verilog in the market- place. First, the introduction of the Programming Language Interface (PL!) permitted users of Verilog to literally extend and customize the simulation environment. Since then, users have exploited the PLI and their success at adapting Verilog to their environment has been a real winner for Verilog. The second key factor which drove Verilog's dominance came fram Gateways paying close attention to the needs of the ASIC foundries and enhancing Verilog in close partnership with Motorola, Na- tional, and UTMC in the 1987-1989 time-frame. The realization that the vast majority of logic sim- ulation was being done by designers of ASIC chips drove this effort. With ASIC foundries blessing the use of Verilog and even adopting it as their internal sign-off simulator, the industry acceptance of Verilog was driven even further. The third and final key factor behind the success of Verilog was the introduction of Verilog-based synthesis technology by Synopsys in 1987. Gateway licensed its proprietary Verilog language to Synopsys for this purpose. The combination of the simulation and synthesis technologies served to make Verilog the language of choice for the hardware designers. The arrival of the VHDL (VHSIC Hardware Description Language), along with the powerful alignment of the remaining EDA vendors driving VHDL as an IEEE standard, led to the placement of Verilog in the public domain. Verilog was inducted as the IEEE 136d standard in 1995. Since 1995, many enhancements were made to Verilog HDL based on requests from Verilog users. These changes were incorporated into the latest IEEE 1364-2001 Verilog standard. Today, Verilog has become the language of choice for digital design and is the basis for synthesis, verification, and place and route technologies. Samir's book is an excellent guide to the user of the Verilog language. Not only does it explain the language constructs with a rich variety of examples, it also goes into details of the usage of the PLI and the application of synthesis technology. The topics in the book are arranged logically and flow very smoothly. This book is written from a very practical design perspective rather than with a focus simply on the syntax aspects of the language. This second edition of Samir's book is unique in two ways. Firstly, it incorporates all enhancements described in IEEE 1364-2001 standard. This ensures that the readers of the book are working with the latest information on Verilog. Secondly, a new chapter has been added on advanced verification techniques that are now an integral part of Verilog-based methodolagies. Knowledge of these tech- niques is critical to Verilog users who design and verify multi-million gate systems. Foreword xxii | can still remember the challenges of teaching Verilog and its associated design and verification methodologies to users. By using Samir's book, beginning users of Verilog will become productive sooner, and experienced Verilog users will get the latest in a convenient reference book that can refresh their understanding of Verilog. This book is a must for any Verilog user. Prabhu Goel Fosmer President of Gateway Design Automation xxiii Preface During my earliest experience with Verilog HDL, | was looking for a book that could give me a ‘jump start” on using Verilog HDL. | wanted ta learn basic digital design paradigms and the necessary Verilog HDL constructs that would help me build small digital circuits, using Verilog and run simu- lations. After | had gained some experience with building basic Verilog models, | wanted to learn to use Verilog HDL to build larger designs. At that time, | was searching for a book that broadly dis- cussed advanced Verilog-based digital design concepts and reafdigital design methodologies. Fi- nally, when | had gained enough experience with digital design and verification of real IC chips, though manuals of Verilog-based products were available, from time to time, | felt the need for a Verilog HDL book that would act as a handy reference. A desire to fill this need led to the publication of the first edition of this book. Ithas been more thansix years since the publication of the first edition. Many changes have occurred during these years. These years have added to the depth and richness of my design and verification experience through the diverse variety of ASIC and microprocessor projects that I have successfully completed in this duration. | have also seen state-of-the-art verification methodologies and tools evolve to a high level of maturity. The IEEE 1364-2001 standard for Verilog HDL has been approved. The purpose of this second edition is to incorporate the IEEE 1364-2001 additions and introduce to Verilog users the latest advances in verification. | hope to make this edition a richer learning expe- rience for the reader. This book emphasizes breadth rather than depth. The book imparts to the reader a working knowl- edge of a broad variety of Verilog-based topics, thus giving the reader a global understanding of Verilog HDL-based design. The book leaves the in-depth coverage of each topic to the Verilag HDL language reference manual and the reference manuals of the individual Verilog-based products. This book should be classified not only as a Verilog HDL book but, more generally, as a digital design book. It is important to realize that Verilog HDL is only a tool used in digital design. It is the means to an end—the digital IC chip. Therefore, this book stresses the practical design perspective more than the mere language aspects of Verilog HDL. With HDL-based digital design having become a necessity, no digital designer can afford to ignore HDLs. Who Should Use This Book The book is intended primarily for beginners and intermediate-level Verilog users. However, for advanced Verilog users, the broad coverage of topics makes it an excellent reference book to be used in conjunction with the manuals and training materials of Verilog-based products. The book presents a logical progression of Verilog HDL-based topics. It starts with the basics, such as HDL-based design methodologies, and then gradually builds on the basics to eventually reach advanced topics, such as PLI or logic synthesis. Thus, the book is useful to Verilog users with varying levels of expertise as explained below. + Students In logic design courses at universities Preface xxiv Part 1 of this book is ideal for a foundation semester course in Verilog HDL-based logic design. Students are exposed to hierarchical modeling concepts, basic Verilog constructs and modeling techniques, and the necessary knowledge to write small models and run simulations. + New Verilog users In the industry Companies are moving to Verilog HDL- based design. Part 1 of this book is a perfect jump start for designers who want to orient their skills toward HDL-based design. + Users with basic Verilog knowledge who need to understand advanced concepts Part 2 of this book discusses advanced concepts, such as UDPS, timing simulation, PLI, and logic synthesis, which are necessary for graduation from small Verilog models to larger designs. + Verllog experts All Verilog topics are covered, from the basics modeling constructs to advanced topics like PLIs, logic synthesis, and advanced verification techniques. For Verilog experts, this book is a handy reference ta be used along with the /EEE Standard Verilog Hardware Deseription Language reference manual. The material in the book sometimes leans toward an Application Specific Integrated Circuit (ASIC) design methodology. However, the concepts explained in the book are general enough to be ap- plicable to the design of FPGAs, PALs, buses, boards, and systems. The book uses Medium Scale Integration (MSI) logic examples to simplify discussion. The same concepts apply to VLSI designs. How This Book Is Organized This book is organized into three parts. Part 1, Basic Verllog Topics, covers all information that a new user needs to build small Verilog madels and run simulations. Note thatin Part 1, gate-level modeling is addressed before behavioral madeling. | have chosen to do so because | think that it is easier for a new user to see a 1-1 correspondence between gate-level circuits and equivalent Verilog descriptions. Once gate-level madeling is understood, a new user can move to higher levels of abstraction, such as data flow madeling and behavioral modeling, without losing sight of the fact that Verilog HDL is a language for digital design and is not a programming language. Thus, a new user starts off with the idea that Verilog is a language for digital design. New users who start with behavioral modeling often tend to write Verilog the way they write their C programs. They sometimes lose sight of the fact that they are trying to represent hardware circuits by using Verilog. Part 1 contains nine chapters Part 2, Advanced Verllog Topics, contains the advanced concepts a Verilog user needs to know to graduate from small Verilog models to larger designs. Advanced topics such as timing simulation, switch-level modeling, UDPs, PLI, lagic synthesis, and advanced verification techniques are cov- ered. Part 2 contains six chapters. Part 3, Appendices, contains information useful as a reference. Useful information, such as strength- level modeling, list of PLI routines, formal syntax definition, Verilog tidbits, and large Verilog exam- ples is included. Part 3 contains six appendices Conventions Used in This Book Table PR-1 describes the type changes and symbols used in this book. Table PR-t. Typographic Conventions Typeface or Symbol Description Examples AaBbCel23 Keywords, system tasks and compiler directives thatareapartef and, nand, $display, ‘define Verilog HDL. daBbCe 123 Emphasis ceil characterization, instantiation Names of signals, moclules, ports, et. fillets, DPF. out Preface XW A few other conventions need to be clarified. + Inthe book, use of Verilog and Verilog HDL refers to the “Verilog Hardware Description Lan- guage.” Any reference to a Verilog-based simulator is specifically mentioned, using words such as Verilog simulator or trademarks such as Verilog-XL or VCS. + The word designeris used frequently in the book to emphasize the digital design perspective. However, it is a general term used to refer to a Verilog HDL user or a verification engineer xxv Acknowledgments The first edition of this book was written with the help of a great many people who contributed their energies to this project. Following were the primary contributors to my creation: Yohn Sanguinetti, Stuart Sutherland, Clifford Cummings, Robert Emberley, Ashutosh Mauskar, Jack McKeown, Dr. Arun Somani, Dr. Michael Ciletti, Larry Ke, Sunil Sabat, Cheng-I Huang, Maqsoodu! Mannan, Ashok Mehta, Dick Herlein, Rita Glover, Ming-Hwa Wang, Subramanian Ganesan, Sandeep Aggarwal, Albert Lau, Samir Sanghani, Kitan Buch, Anshuman Saha, Bill Fuchs, Babu Chitukuri, Ramana Kalapatapu, Karin Ellison and Rachel Borden. | would like to start by thanking all those people once again. For this second edition, | give special thanks to the following people who helped me with the review process and provided valuable feedback: Anders Nordstrom Stefen Boyd Clifford Cummings Harry Foster Yatin Trivedi Rajeev Madhavan John Sanguinetti Dr. Arun Somani Michael McNamara Berend Ozceri Shrenik Mehta Mike Meredith ASIC Consultant Boyd Technology Sunburst Design Verpiex Systems Magma Design Automation Magma Design Automation Forte Design Systems lowa State University Verisity Design Cisco Systems Sun Microsystems Forte Design Systems Lalso appreciate the help of the following individuals: Part 1. Basic Verilog Topics Chapter 1. Overview of Digital Design with Verilog HDL Evolution of Computer-Aided Digital Design Digital circuit design has evolved rapidly over the last 25 years. The earliest digital circuits were designed with vacuum tubes and transistors. Integrated circuits were then invented where logic gates were placed on a single chip. The first integrated circuit (IC) chips were SSI (Small Scale integration) chips where the gate count was very small. As technologies became sophisticated designers were able to place circuits with hundreds of gates on a chip. These chips were called MSI (Medium Scale Integration) chips. With the advent of LSI (Large Scale Integration), designers could put thousands of gates on a single chip. At this point, design processes started getting very com- plicated, and designers felt the need to automate these processes. Electronic Design Automation (EDA)' techniques began te evolve. Chip designers began to use circuit and logic simulation tech- niques to verify the functionality of building blocks of the order of about 100 transistors. The circuits were still tested on the breadboard, and the layout was done on paper or by hand on a graphic computer terminal. With the advent of VLSI (Very Large Scale Integration) technology, designers could design single chips with more than 100,000 transistors. Because of the complexity of these circuits, it was not possible to verify these circuits on a breadboard. Computer-aided techniques became critical for verification and design of VLSI digital circuits. Computer programs to do automatic placement and routing of circuit layouts also became popular. The designers were now building gate-level digital circuits manually on graphic terminals. They would build small building blocks and then derive higher-level blocks from them. This process would continue until they had built the top-level block, Logic simulators came into existence to verify the functionality of these circuits before they were fabricated on chip. As designs got larger and mare complex, logic simulation assumed an important role in the design process. Designers could iron out functional bugs in the architecture before the chip was designed further. Emergence of HDLs For a lang time, programming languages such as FORTRAN, Pascal, and C were being used to describe computer programs that were sequential in nature. Similarly, in the digital design field, designers felt the need for a standard language to describe digital circuits. Thus, Mardware De- scription Languages (HDLs) came into existence. HDLs allowed the designers to model the con- "The earlier editian of the book used the term GAD taals. Technically. the team Computer-Aided Design (CAB) tools refers to back-end tools Inst parform functions relatad to place and raute, and layout of the chip . The term Computer-Aided Engineering (CAE) tools reters to tools that are used for front-end processes such HDL simulation, logic synthesis, and imming analysis. Designers used the lerms CAD and CAE intarenangeably. Today, the tarm Electronic Dasign Automation is used for both CAD and CAE. For tha sake of simplicity, m this book, we will afer to all design tools as EDA tools, Overview of Digital Design with Verilog HDL 3 currency of processes found in hardware elements. Hardware description languages such as Ver- jeg HDL and VHDL became popular. Verilog HDL originated in 1983 at Gateway Design Automa- tion. Later, VHDL was developed under contract from DARPA. Both Verilog® and VHDL simulators to simulate large digital circuits quickly gained acceptance from designers. Even though HDLs were popular for logic verification, designers had to manually translate the HDL- based design into a schematic circuit with interconnections between gates. The advent of logic synthesis in the late 1980s changed the design methodology radically. Digital circuits could be de- scribed at a register transfer level (RTL) by use of an HDL. Thus, the designer had to specify how the data flows. between registers and how the design processes the data. The details of gates and their interconnections to implement the circuit were automatically extracted by logic synthesis tools from the RTL description Thus, logic synthesis pushed the HDLs into the forefront of digital design. Designers no longer had to manually place gates to build digital circuits. They could deseribe complex circuits at an abstract level in terms of functionality and data flow by designing those circuits in HDLs. Logic synthesis tools would implement the specified functionality in terms of gates and gate interconnections. HDLs also began to be used for system-level design. HDLs were used for simulation of system boards, interconnect buses, FPGAs (Field Programmable Gate Arrays), and PALs (Programmable Array Logic). A common approach is to design each IC chip, using an HDL, and then verify system functionality via simulation Today, Verilog HDL is an accepted IEEE standard. In 1995, the original standard IEEE 1364-1995 was approved. IEEE 1364-2001 is the latest Verilog HDL standard that made significant improve- ments to the original standard. Typical Design Flow A typical design flow for designing VLSI IC circuits is shown in Figure 1-1. Unshaded blocks show the level of design representation; shaded blocks show processes in the design flow. Overview of Digital Design with Verilog HDL 4 Design Specification Behavioral Description Functional Verification and Testing y Logic Synthesis/ Timing Verification |__| Gate-Level Netlist v Logical Verification and Testing t Floor Planning Automatic Place and Route ’ Physical Layout a, Layout Verification Implementation Figure 1-1. Typical Design Flow The design flow shown in Figure 1-1 is typically used by designers who use HDLs. In any design, specifications are written first. Specifications describe abstractly the functionality, interface, and overall architecture of the digital circuit to be designed. At this point, the architects do not need to think about how they will implement this circuit. A behavioral description is then created to analyze the design in terms of functionality, performance, compliance to standards, and other high-level issues. Behavioral descriptions are often written with HDLs.2 The behavioral description is manually converted to an RTL description in an HDL. The designer has to describe the data flow that will implement the desired digital circuit. From this point onward, the design process is done with the assistance of EDA tools. 2New EDA toola have emerged to simulate behavioral descriptions of cireults. These tools combine the powerful concepts from HDLs and ‘abject oriented languages such as C++. These tools can be used instead of wring behavioral descriptions in Verlag HDL. Overview of Digital Design with Verilog HDL 5 Logic synthesis tools convert the RTL description to a gate-level netlist. A gate-level netlist is a description of the circuit in terms of gates and connections between them. Logie synthesis tools ensure that the gate-level netlist meets timing, area, and power specifications. The gate-level netlist is input to an Automatic Place and Route tool, which creates a layout. The layoutis verified and then fabricated on a chip. Thus, most digital design activity is concentrated on manually optimizing the RTL description of the circuit. After the RTL description is frozen, EDA tools are available to assist the designer in further processes. Designing at the RTL level has shrunk the design cycle times from years toa few months. Itis also possible to do many design iterations in a short period of time. Behavioral synthesis tools have begun to emerge recently. These tools can create RTL descriptions from a behavioral or algorithmic description of the circuit. As these tools mature, digital circuitdesign will become similar to high-level computer programming. Designers will simply implement the al- gorithm in an HDL ata very abstract level. EDA tools will help the designer convert the behavioral description to a final IC chip. It is important to note that, although EDA tools are available to automate the processes and cut design cycle times, the designer is still the person who controls how the tool will perform. EDA tools are alsa susceptible to the *“G/GO : Garbage In Garbage Out phenamenon. If used improperly, EDA tools will lead to inefficient designs. Thus, the designer still needs to understand the nuances of design methodologies, using EDA tools to obtain an optimized design Importance of HDLs HDLs have many advantages compared to traditional schematic-based design. + Designs can be described ata very abstract level by use of HDLs. Designers can write their RTL description withaut choosing a specific tabrication technology. Logic synthesis tools can auto- matically convert the design to any fabrication technology. If a new technology emerges, de- signers do not need to redesign their circuit. They simply input the RTL description to the logic synthesis tool and create a new gate-level netlist, using the new fabrication technology. The logic synthesis tool will optimize the circuit in area and timing for the new technology. + By describing designs in HDLs, functional verification of the design can be done early in the design cycle, Since designers work at the RTL level, they can optimize and modify the RTL description until it meets the desired functionality. Most design bugs are eliminated at this point. This cuts down design cycle time significantly because the probability of hitting a functional bug ata later time in the gate-level netlist or physical layout is minimized. + Designing with HDLs is analogous to computer programming. A textual description with com- ments is an easier way to develop and debug circuits. This also provides a concise represen- tation of the design, compared to gate-level schematics. Gate-level schematics are almost in- comprehensible for very complex designs. HDL-based design is here to stay. With rapidly increasing complexities of digital circuits and in- creasingly sophisticated EDA tools, HDLs are now the dominant method for large digital designs. No digital circuit designer can afford to ignore HDL-based design Popularity of Verilog HDL Verilog HDL has evolved as a standard hardware description language. Verilog HDL offers many useful features New tools and languages focused an veriieation have emerged in the past few years. Thase languages are better sulted far functional verification. However, for logic design, HDLs continue as the preferred choice, Overview of Digital Design with Verilog HDL 6 + Verilog HDL is a general-purpose hardware description language that is easy to learn and easy to use. It is similar in syntax to the C programming language. Designers with C programming ‘experience will find it easy to learn Verilog HDL. + Verilog HDL allows different levels of abstraction to be mixed in the same model. Thus, a de- signer can define a hardware model in terms of switches, gates, RTL, or behavioral code. Also, a designer needs to learn only one language for stimulus and hierarchical design. + Most popular logic synthesis tools support Verilog HDL. This makes it the language of choice for designers. + All fabrication vendors provide Verilog HDL libraries for postlogic synthesis simulation. Thus, designing a chip in Verilog HDL allows the widest choice of vendors. + The Programming Language Interface (PL!) is a powerful feature that allows the user to write custom C code to interact with the internal data structures of Verilog. Designers can customize a Verilog HDL simulator to their needs with the PLI. Trends in HDLs The speed and complexity of digital circuits have increased rapidly. Designers have responded by designing at higher levels of abstraction. Designers have to think only in terms of functionality. EDA tools take care of the implementation details. With designer assistance, EDA tools have become sophisticated enough to achieve a close-to-optimum implementation. The most popular trend currently is to design in HDL at an RTL level, because logic synthesis tools can create gate-level netlists from RTL level design. Behavioral synthesis allowed engineers to design directly in terms of algorithms and the behavior of the circuit, and then use EDA tools te do the translation and optimization in each phase of the design. However, behavioral synthesis did not gain widespread acceptance. Today, RTL design continues to be very popular. Verilag HDL is also being constantly enhanced to meet the needs of new verification methodologies. Formal verification and assertion checking techniques have emerged. Formal verification applies formal mathematical techniques to verify the correctness of Verilog HDL descriptions and to estab- lish equivalency between RTL and gate-level netlists. However, the need to describe a design in Verilog HDL will not go away. Assertion checkers allow checking to be embedded in the RTL code. This is a convenient way to do checking in the most important parts of a design. New verification languages have also gained rapid acceptance. These languages combine the par- allelism and hardware constructs from HDLs with the object oriented nature of C++. These lan- guages also provide support for automatic stimulus creation, checking, and coverage. However, these languages do not replace Verilog HDL. They simply boost the productivity of the verification process. Verilog HDL is still needed to describe the design For very high-speed and timing-critical circuits like microprocessors, the gate-level netlist provided by logic synthesis tools is not optimal. In such cases, designers often mix gate-level description directly into the RTL description to achieve optimum results. This practice is oppasite to the high- level design paradigm, yet it is frequently used for high-speed designs because designers need to squeeze the last bit of timing out of circuits, and EDA tools sometimes prove to be insufficient to achieve the desired results. Anather technique that is used far system-level design is a mixed bottom-up methodology where the designers use either existing Verilog HDL modules, basic building blocks, or vendor-supplied core blocks ta quickly bring up their system simulation. This is done to reduce development costs and compress design schedules. For example, consider a system that has a CPU, graphics chip, VO chip, and a system bus. The GPU designers wauld build the next-generation CPU themselves Overview of Digital Design with Verilog HDL 7 at an RTL level, but they would use behavioral models for the graphics chip and the VO chip and would buy a vendor-supplied model for the system bus. Thus, the system-level simulation for the CPU could be up and running very quickly and long before the RTL descriptions for the graphics chip and the I/O chip are completed. Chapter 2. Hierarchical Modeling Concepts Before we discuss the details of the Verilog language, we must first understand basic hierarchical modeling concepts in digital design. The designer must use a "good" design methodology to do efficient Verilog HDL-based design. In this chapter, we discuss typical design methodologies and illustrate how these concepts are translated to Verilog. A digital simulation is made up of various components. We talk abaut the components and their interconnections. Learning Objectives + Understand top-down and bottom-up design methodologies for digital design. + Explain differences between modules and module instances in Verilog. + Describe four levels of abstraction—behavioral, data flow, gate level, and switch level—to rep- resent the same module. + Describe components required for the simulation of a digital design. Define a stimulus block and a design block. Explain two methods of applying stimulus. Design Methodologies There are two basic types of digital design methodologies: a top-down design methodology and a bottom-up design methodology. In a top-down design methodology, we define the top-level block and identify the sub-blocks necessary to build the top-level block. We further subdivide the sub- blocks until we come to leaf cells, which are the cells that cannot further be divided. Figure 2-1 shows the top-down design process. Top-level 7 * a sub- sub- block 3 block 4 leaf leaf leat leaf leaf leaf cell cell cell cell cell cell cell Figure 2-1. Top-down Design Methodology In a bottom-up design methodology, we first identify the building blocks that are available to us. We build bigger cells, using these building blocks. These cells are then used for higher-level blocks until we build the tap-level block in the design. Figure 2-2 shows the bottom-up design process Hierarchical Modeling Concepts 9 Top-level macro macro macro | mac cell 2 cell 3 cell 4 leat leat leat cell cell cell Figure 2-2. Bottom-up Besign Methodology Typically, a combination of top-down and bottom-up flows is used. Design architects define the specifications of the top-level block. Logic designers decide how the design should be structured by breaking up the functionality into blocks and sub-blocks. Al the same time, circuit designers are designing optimized circuits for leaf-level cells. They build higher-level cells by using these leaf cells. The flow meets at an intermediate point where the switch-level circuit designers have created a library of leaf cells by using switches, and the logic level designers have designed from top-down until all modules are defined in terms of leaf cells, To illustrate these hierarchical modeling concepts, let us consider the design of a negative edge- triggered 4-bit ripple carry counter described in Section 2.2, 4-bit Ripple Carry Counter 4-bit Ripple Carry Counter The ripple carry counter shown in Figure 2-3 is made up of negative edge-triggered toggle flipflaps (7_F8). Each of the T_FFs can be made up from negative edge-triggered D-tlipflops (D_FF) and verters (assuming q_baroutput is not available on the O_FF), as shown in Figure 2-4. Ripple 0 3 Carry q ql 2 4 Counter jp Sg ee Se 4 I I | 4. q q | clock ——-C)) 7 _FF LoS 7 EF > T_EF| | | +f 12 tff3 I | | | | ! Teset T | eee eee See ee ee ee ee 4 Figura 2-3. Ripple Camy Counter Hierarchical Modeling Concepts 10 T_FF poo | <4 1 0 0 0 0 1 clock =—o) | 0 1 0 | 0 0 0 ——— reset Figure 2-4. T-fiptop Thus, the ripple carry counter is built in a hierarchical fashion by using building blocks. The diagram for the design hierarchy is shawn in Figure 2-5. pple Carry ‘ounte DIFF) | tener ate liveries DIFF] | merter D_FF gate gate Figure 2-5. Besign Hierarchy In a top-down design methodology, we first have to specify the functionality of the ripple carry coun- ter, which is the top-level block. Then, we implement the counter with 7_FFS. We build the 7_FFs from the B_FF and an additional inverter gate. Thus, we break bigger blacks into smaller building sub-blocks until we decide that we cannot break up the blacks any further. A bottom-up methodology flows in the opposite direction. We combine small building blocks and build bigger blocks; e.g., we could build 2 FF from and and or gates, or we could build a custom D_FF from transistors. Thus, the bottom-up flow meets the top-down flow at the level of the DF. Modules We now relate these hierarchical modeling concepts to Verilog. Verilog provides the concept of a module. A module is the basic building block in Verilog. A module can be an element or a collection of lower-level design blocks. Typically, elements are grouped into modules to provide common functionality thatis used at many places in the design. A module provides the necessary functionality to the higher-level block through its port interface (inputs and outputs), but hides the internal impie- mentation. This allows the designer to modify module internals without affecting the rest of the design. Hierarchical Madeling Concepts 1 In Figure 2-5, ripple carry counter, T_FF, D_#F are examples of modules. In Verilog, a module is declared by the keyword module. A corresponding keyword endmodule must appear at the end of the module definition. Each module must have a madule_name, which is the identifier for the madule, and a module_terminal_list, which describes the input and output terminals of the module. module

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