System Verilog Class

A MemTrans class is defined with an 8-bit data_in and 4-bit address. The class includes a print function that displays the values of data_in and address. An object of the MemTrans class is instantiated in an initial block in the top module, and its print function is called to output the values.

Uploaded by

Melody Shields

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PPTX, PDF, TXT or read online on Scribd

0% found this document useful (0 votes)

127 views3 pages

System Verilog Class

Uploaded by

Melody Shields

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PPTX, PDF, TXT or read online on Scribd

You are on page 1/ 3

System Verilog Class

Example
Requirement:
Create a class called MemTrans that
contains the following members, then
construct a MemTrans object in an initial
block.
a. An 8-bit data_in of logic type
b. A 4-bit address of logic type
c. A void function called print that prints
out the value of data_in and address

Solution:
Class MemTrans;
logic [7:0] data
logic [3:0] addr;
function void print();
$display(data = %h ,data);
$display(addr = %h ,addr);
endfunction
endclass

Top Module
module top;
initial
begin
memTrans obj; //creating an object handle
obj = new(); //Allocating Memory
obj.print();
end
endmodule

Analysis and Design of Analog Integrated Circuits (4th Edition, 2000) - Gray & Meyer - Solution Manual
83% (6)
Analysis and Design of Analog Integrated Circuits (4th Edition, 2000) - Gray & Meyer - Solution Manual
401 pages
Chap5 Oops Concepts
No ratings yet
Chap5 Oops Concepts
50 pages
Himani Codes
No ratings yet
Himani Codes
49 pages
System Verilog Material - Final
100% (3)
System Verilog Material - Final
285 pages
Just Enough Verilog For PSoC
No ratings yet
Just Enough Verilog For PSoC
15 pages
SystemVerilog Oops
No ratings yet
SystemVerilog Oops
19 pages
System Verilog Classes
100% (2)
System Verilog Classes
101 pages
SV Session 5
No ratings yet
SV Session 5
68 pages
L05 - Verilog - Operators Instantiation Parametrization
No ratings yet
L05 - Verilog - Operators Instantiation Parametrization
30 pages
Introduction To Verilog Hardware Description Language
No ratings yet
Introduction To Verilog Hardware Description Language
108 pages
Arrays SV Ex
No ratings yet
Arrays SV Ex
20 pages
Verilog HDL
No ratings yet
Verilog HDL
74 pages
Enc Encoded U 3 V RN RQN BBKF ZFAt 7 K LCB TD TJ QGi 5 ML Uh P4 V D141 Aylmh QG 3 PSH 6 DTF P09 G8
No ratings yet
Enc Encoded U 3 V RN RQN BBKF ZFAt 7 K LCB TD TJ QGi 5 ML Uh P4 V D141 Aylmh QG 3 PSH 6 DTF P09 G8
33 pages
Verilog HDL
No ratings yet
Verilog HDL
51 pages
SystemVerilog Part I
No ratings yet
SystemVerilog Part I
74 pages
Verilog Modeling&syntax
No ratings yet
Verilog Modeling&syntax
48 pages
Chapter10 Verilog
No ratings yet
Chapter10 Verilog
62 pages
Prelim Module2 - B
No ratings yet
Prelim Module2 - B
17 pages
EE344 - Digital Systems Desgin
No ratings yet
EE344 - Digital Systems Desgin
27 pages
DV Courses Structure
No ratings yet
DV Courses Structure
7 pages
Introduction Verilog
100% (1)
Introduction Verilog
193 pages
Introduction To Verilog Hardware Description Language
No ratings yet
Introduction To Verilog Hardware Description Language
108 pages
DigitalLogic ComputerOrganization L9 10 FPGA Verilog Handout
No ratings yet
DigitalLogic ComputerOrganization L9 10 FPGA Verilog Handout
37 pages
Verilog Intro
No ratings yet
Verilog Intro
31 pages
System Verilog OOP
No ratings yet
System Verilog OOP
51 pages
Verilog GATE AND DATA FLOW
No ratings yet
Verilog GATE AND DATA FLOW
64 pages
(Ebook - PDF) Synthesizable Verilog-HDL Code - Circuit Design
No ratings yet
(Ebook - PDF) Synthesizable Verilog-HDL Code - Circuit Design
63 pages
SystemVerilog Interview Questions PART-1
No ratings yet
SystemVerilog Interview Questions PART-1
17 pages
System Verilog Imp
No ratings yet
System Verilog Imp
59 pages
NC Launch
No ratings yet
NC Launch
40 pages
Introduction To Verilog HDL
100% (1)
Introduction To Verilog HDL
48 pages
System Verilog
No ratings yet
System Verilog
44 pages
Verilog Tutorial: Chin-Lung Su
No ratings yet
Verilog Tutorial: Chin-Lung Su
42 pages
SystemVerilog Veriflcation
No ratings yet
SystemVerilog Veriflcation
68 pages
Verilog Fundamentals
No ratings yet
Verilog Fundamentals
49 pages
System Verilog Tutorial
100% (1)
System Verilog Tutorial
44 pages
Design Domain and Levels of Abstraction
No ratings yet
Design Domain and Levels of Abstraction
68 pages
System Verilog Tutorial
No ratings yet
System Verilog Tutorial
44 pages
Biofeedback Resource Books
100% (1)
Biofeedback Resource Books
9 pages
SystemVerilog Veriflcation
No ratings yet
SystemVerilog Veriflcation
68 pages
Verilog Cheatsheet
No ratings yet
Verilog Cheatsheet
2 pages
Verilog Fundamentals: Shubham Singh
No ratings yet
Verilog Fundamentals: Shubham Singh
49 pages
ASIC Assignment - 2
No ratings yet
ASIC Assignment - 2
9 pages
System Verilog Lecture
No ratings yet
System Verilog Lecture
82 pages
Unit 2 Advsv
No ratings yet
Unit 2 Advsv
32 pages
Verilog (R) QRC 02
100% (1)
Verilog (R) QRC 02
2 pages
Introduction To Verilog HDL: Presented by K.Swathi
No ratings yet
Introduction To Verilog HDL: Presented by K.Swathi
35 pages
Verilog Language: Lexical Conventions Examples
No ratings yet
Verilog Language: Lexical Conventions Examples
4 pages
Enhanced Timing Closure Using Latches
No ratings yet
Enhanced Timing Closure Using Latches
6 pages
Cs6304-Adc QB Ans Rejinpaul
No ratings yet
Cs6304-Adc QB Ans Rejinpaul
11 pages
Cs6304-Adc QB Ans Rejinpaul
No ratings yet
Cs6304-Adc QB Ans Rejinpaul
11 pages
Polymorphism System Verilog
No ratings yet
Polymorphism System Verilog
5 pages
Lecture Slides 3 3capacitors
No ratings yet
Lecture Slides 3 3capacitors
12 pages
Linear Circuits: An Introduction To Linear Electric Circuit Elements and A Study of Circuits Containing Such Devices
No ratings yet
Linear Circuits: An Introduction To Linear Electric Circuit Elements and A Study of Circuits Containing Such Devices
14 pages
Enhancing System Verilog - AOP
No ratings yet
Enhancing System Verilog - AOP
3 pages
Poly
No ratings yet
Poly
1 page
Lec Week6
No ratings yet
Lec Week6
3 pages
Essential VHDL
No ratings yet
Essential VHDL
127 pages
The Unit Impulse Function
No ratings yet
The Unit Impulse Function
3 pages

System Verilog Class

Uploaded by

System Verilog Class

Uploaded by

System Verilog Class

You might also like