EXPERIMENT NO: 1

HALF ADDER USING DIFFERENT DATA FLOW

MODELS
1. Using when else
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ha is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end ha;
architecture Behavioral of ha is
begin
sum <= '0' when (a='0' and b='0') or (a='1' and b='1') else
'1' when (a='0' and b='1') or (a='1' and b='0') else
'Z';
carry <= '0' when (a='0' and b='0') or (a='1' and b='0') or (a='0' and b='1') else
'1' when (a='1' and b='1') else
'Z';
end Behavioral;

RTL SCHEMATIC:

TEST BENCH WAVEFORMS:

Summary
Design Name

ha

Fitting Status

Successful

Software Version

J.36

Device Used

XA9536XL-15-VQ44

Date

10-23-2015, 8:00AM
RESOURCES SUMMARY

Macrocells Used

Pterms Used

Registers Used

Pins Used

2/36 (6%)

3/180 (2%)

0/36 (0%)

4/34 (12%)

Function Block
Inputs Used
4/108 (4%)

PIN RESOURCES

Signal Type
Input
Output
Bidirectional
GCK
GTS
GSR

Required
2
2
0
0
0
0

Mapped
2
2
0
0
0
0

Pin Type
I/O
GCK/IO
GTS/IO
GSR/IO

Used
4
0
0
0

Total
28
3
2
1

GLOBAL RESOURCES

Global clock net(s) used

Global output enable net(s) used
Global set/rest net(s) used

0
0
0
POWER DATA

Macrocells in high performance mode

(MCHP)
Macrocells in low power mode (MCLP)
Total macrocells used (MC)
back to top

0
2
2
print page

2. Using with select

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity hax is
Port ( a : in STD_LOGIC_VECTOR(0 to 1);
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end hax;
architecture Behavioral of hax is
begin
with a select
sum<= '0' when "00",
'0' when "11",
'1' when "01",
'1' when "10",
'Z' when others;
with a select
carry<= '0' when "00",
'0' when "01",
'0' when "10",
'1' when "11",
'Z' when others;
end Behavioral;

RTL SCHEMATIC:

TEST BENCH WAVEFORMS:

Summary
Design Name

hax

Fitting Status

Successful

Software Version

J.36

Device Used

XA9536XL-15-VQ44

Date

10-23-2015, 10:02AM
RESOURCES SUMMARY

Macrocells Used

Pterms Used

Registers Used

Pins Used

2/36 (6%)

3/180 (2%)

0/36 (0%)

4/34 (12%)

Function Block
Inputs Used
4/108 (4%)

PIN RESOURCES

Signal Type
Input
Output
Bidirectional
GCK
GTS
GSR

Required
2
2
0
0
0
0

Mapped
2
2
0
0
0
0

Pin Type
I/O
GCK/IO
GTS/IO
GSR/IO

Used
4
0
0
0

Total
28
3
2
1

GLOBAL RESOURCES

Global clock net(s) used

Global output enable net(s) used
Global set/rest net(s) used

0
0
0
POWER DATA

Macrocells in high performance mode

(MCHP)
Macrocells in low power mode (MCLP)
Total macrocells used (MC)
back to top

0
2
2
print page

EXPERIMENT NO: 2

FULL ADDER USING DATA FLOW AND

BEHAVIOURAL MODEL
1. Implement a full adder using data flow modelling
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fulladd is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
cout: out STD_LOGIC);
end fulladd;
architecture Behavioral of fulladd is
begin
sum <= a xor b xor cin;
cout <= (a and b) or (b and cin) or (cin and a);
end Behavioral;

RTL SCHEMATIC:

TEST BENCH WAVEFORMS:

Summary
Design Name

fulladd

Fitting Status

Successful

Software Version

J.36

Device Used

XA9536XL-15-VQ44

Date

10-23-2015, 10:38AM
RESOURCES SUMMARY

Macrocells Used

Pterms Used

Registers Used

Pins Used

2/36 (6%)

6/180 (4%)

0/36 (0%)

5/34 (15%)

Function Block
Inputs Used
6/108 (6%)

PIN RESOURCES

Signal Type
Input
Output
Bidirectional
GCK
GTS
GSR

Required
3
2
0
0
0
0

Mapped
3
2
0
0
0
0

Pin Type
I/O
GCK/IO
GTS/IO
GSR/IO

Used
5
0
0
0

Total
28
3
2
1

GLOBAL RESOURCES

Global clock net(s) used

Global output enable net(s) used
Global set/rest net(s) used

0
0
0
POWER DATA

Macrocells in high performance mode

(MCHP)
Macrocells in low power mode (MCLP)
Total macrocells used (MC)
back to top

0
2
2
print page

2. Implement a full adder using behavioural modelling

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fulladdb is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end fulladdb;
architecture Behavioral of fulladdb is
begin
process(a,b,cin)
begin
sum<='1';
cout<='1';
if(cin=(a xor b)) then
sum<='0';
end if;
if((a and b)='0' and (a and cin)='0' and (b and cin)='0') then
cout<='0';
end if;
end process;
end Behavioral;

RTL SCHEMATIC:

TEST BENCH WAVEFORMS:

Summary
Design Name

fulladdb

Fitting Status

Successful

Software Version

J.36

Device Used

XA9536XL-15-VQ44

Date

10-23-2015, 10:56AM
RESOURCES SUMMARY

Macrocells Used

Pterms Used

Registers Used

Pins Used

2/36 (6%)

6/180 (4%)

0/36 (0%)

5/34 (15%)

Function Block
Inputs Used
6/108 (6%)

PIN RESOURCES

Signal Type
Input
Output
Bidirectional
GCK
GTS
GSR

Required
3
2
0
0
0
0

Mapped
3
2
0
0
0
0

Pin Type
I/O
GCK/IO
GTS/IO
GSR/IO

Used
5
0
0
0

Total
28
3
2
1

GLOBAL RESOURCES

Global clock net(s) used

Global output enable net(s) used
Global set/rest net(s) used

0
0
0
POWER DATA

Macrocells in high performance mode

(MCHP)
Macrocells in low power mode (MCLP)
Total macrocells used (MC)
back to top

0
2
2
print page

EXPERIMENT NO: 3

2-BIT COMPARATOR
1. Design and Implement a 2-bit comparator using data flow modelling.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity compd is
Port ( a : in STD_LOGIC_VECTOR(0 to 1);
b : in STD_LOGIC_VECTOR(0 to 1);
f : out STD_LOGIC_VECTOR (0 to 2));
end compd;
architecture Behavioral of compd is
begin
f <=

"100" when (a>b) else

"010" when (a=b) else
"001" when (a<b) else
"000";

end Behavioral;

RTL SCHEMATIC:

TEST BENCH WAVEFORMS:

Summary
Design Name

compd

Fitting Status

Successful

Software Version

J.36

Device Used

XA9536XL-15-VQ44

Date

10-23-2015, 11:27AM
RESOURCES SUMMARY

Macrocells Used

Pterms Used

Registers Used

Pins Used

3/36 (9%)

6/180 (4%)

0/36 (0%)

7/34 (21%)

Function Block
Inputs Used
7/108 (7%)

PIN RESOURCES

Signal Type
Input
Output
Bidirectional
GCK
GTS
GSR

Required
4
3
0
0
0
0

Mapped
4
3
0
0
0
0

Pin Type
I/O
GCK/IO
GTS/IO
GSR/IO

GLOBAL RESOURCES

Global clock net(s) used

Global output enable net(s) used
Global set/rest net(s) used

0
0
0
POWER DATA

Macrocells in high performance mode

(MCHP)
Macrocells in low power mode (MCLP)
Total macrocells used (MC)

0
3
3

Used
7
0
0
0

Total
28
3
2
1

2. Design and Implement a 2-bit comparator using behavioural modelling

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity compb is
Port ( a : in STD_LOGIC_VECTOR (1 downto 0);
b : in STD_LOGIC_VECTOR (1 downto 0);
f : out STD_LOGIC_VECTOR (2 downto 0));
end compb;
architecture Behavioral of compb is
begin
process(a,b)
begin
if(a>b) then f<="100";
elsif(a=b) then f<="010";
elsif(a<b) then f<="001";
else f<="000";
end if;
end process;
end Behavioral;

RTL SCHEMATIC:

TEST BENCH WAVEFORMS:

Summary
Design Name

compb

Fitting Status

Successful

Software Version

J.36

Device Used

XA9536XL-15-VQ44

Date

10-23-2015, 11:40AM
RESOURCES SUMMARY

Macrocells Used

Pterms Used

Registers Used

Pins Used

3/36 (9%)

5/180 (3%)

0/36 (0%)

7/34 (21%)

Function Block
Inputs Used
5/108 (5%)

PIN RESOURCES

Signal Type
Input
Output
Bidirectional
GCK
GTS
GSR

Required
4
3
0
0
0
0

Mapped
4
3
0
0
0
0

Pin Type
I/O
GCK/IO
GTS/IO
GSR/IO

Used
7
0
0
0

Total
28
3
2
1

GLOBAL RESOURCES

Global clock net(s) used

Global output enable net(s) used
Global set/rest net(s) used

0
0
0
POWER DATA

Macrocells in high performance mode

(MCHP)
Macrocells in low power mode (MCLP)
Total macrocells used (MC)
back to top

0
3
3
print page

EXPERIMENT NO: 4

MULTIPLEXER AND DEMULTIPLEXER

1. Implement a 4 by 1 mux

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mux41 is
Port ( i : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC_VECTOR (1 downto 0);
f : out STD_LOGIC);
end mux41;
architecture Behavioral of mux41 is
begin
f<= i(0) when( s="00") else
i(1) when (s="01") else
i(2) when (s="10") else
i(3) when (s="11") else
'Z';
end Behavioral;

RTL SCHEMATIC:

TEST BENCH WAVEFORMS:

Summary
Design Name

mux41

Fitting Status

Successful

Software Version

J.36

Device Used

XA9536XL-15-VQ44

Date

10-23-2015, 11:56AM
RESOURCES SUMMARY

Macrocells Used

Pterms Used

Registers Used

Pins Used

1/36 (3%)

4/180 (3%)

0/36 (0%)

7/34 (21%)

Function Block
Inputs Used
6/108 (6%)

PIN RESOURCES

Signal Type
Input
Output
Bidirectional
GCK
GTS
GSR

Required
6
1
0
0
0
0

Mapped
6
1
0
0
0
0

Pin Type
I/O
GCK/IO
GTS/IO
GSR/IO

Used
7
0
0
0

Total
28
3
2
1

GLOBAL RESOURCES

Global clock net(s) used

Global output enable net(s) used
Global set/rest net(s) used

0
0
0
POWER DATA

Macrocells in high performance mode

(MCHP)
Macrocells in low power mode (MCLP)
Total macrocells used (MC)
back to top

0
1
1
print page

2. Implement a 1 by 4 demux
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity demux14 is
Port ( i : in STD_LOGIC;
s : in STD_LOGIC_VECTOR (1 downto 0);
f : out STD_LOGIC_VECTOR (3 downto 0));
end demux14;
architecture Behavioral of demux14 is
begin
f(0)<= i when s="00" else '0';
f(1)<= i when s="01" else '0';
f(2)<= i when s="10" else '0';
f(3)<= i when s="11" else '0';
end Behavioral;

RTL SCHEMATIC:

TEST BENCH WAVEFORMS:

Summary
Design Name

demux14

Fitting Status

Successful

Software Version

J.36

Device Used

XA9536XL-15-VQ44

Date

10-23-2015, 12:10PM
RESOURCES SUMMARY

Macrocells Used

Pterms Used

Registers Used

Pins Used

4/36 (12%)

4/180 (3%)

0/36 (0%)

7/34 (21%)

Function Block
Inputs Used
6/108 (6%)

PIN RESOURCES

Signal Type
Input
Output
Bidirectional
GCK
GTS
GSR

Required
3
4
0
0
0
0

Mapped
3
4
0
0
0
0

Pin Type
I/O
GCK/IO
GTS/IO
GSR/IO

Used
7
0
0
0

Total
28
3
2
1

GLOBAL RESOURCES

Global clock net(s) used

Global output enable net(s) used
Global set/rest net(s) used

0
0
0
POWER DATA

Macrocells in high performance mode

(MCHP)
Macrocells in low power mode (MCLP)
Total macrocells used (MC)
back to top

0
4
4
print page

EXPERIMENT NO: 5

4 bit RIPPLE CARRY ADDER

1. Implement a 4 bit ripple carry adder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ripple is
Port ( cin : in STD_LOGIC;
x : in STD_LOGIC_VECTOR (3 downto 0);
y : in STD_LOGIC_VECTOR (3 downto 0);
s : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end ripple;
architecture Behavioral of ripple is
begin
process(x,y,cin)
variable c : std_logic_vector(4 downto 0);
begin
c(0):=cin;
for i in 0 to 3 loop
s(i) <= (x(i) xor y(i) xor c(i));
c(i+1):=( (x(i) and y(i)) or (x(i) and c(i)) or (y(i) and c(i)) );
end loop;
cout<= c(4);
end process;
end Behavioral;

RTL SCHEMATIC:

TEST BENCH WAVEFORMS:

Summary
Design Name

ripple

Fitting Status

Successful

Software Version

J.36

Device Used

XA9536XL-15-VQ44

Date

10-23-2015, 12:34PM
RESOURCES SUMMARY

Macrocells Used

Pterms Used

Registers Used

Pins Used

8/36 (23%)

28/180 (16%)

0/36 (0%)

14/34 (42%)

Function Block
Inputs Used
14/108 (13%)

PIN RESOURCES

Signal Type
Input
Output
Bidirectional
GCK
GTS
GSR

Required
9
5
0
0
0
0

Mapped
9
5
0
0
0
0

Pin Type
I/O
GCK/IO
GTS/IO
GSR/IO

Used
14
0
0
0

Total
28
3
2
1

GLOBAL RESOURCES

Global clock net(s) used

Global output enable net(s) used
Global set/rest net(s) used

0
0
0
POWER DATA

Macrocells in high performance mode

(MCHP)
Macrocells in low power mode (MCLP)
Total macrocells used (MC)
back to top

0
8
8
print page

EXPERIMENT NO: 6

8 BY 3 ENCODER AND 3 BY 8 DECODER

1. Implement an 8 by 3 encoder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity encoder is
Port ( i : in STD_LOGIC_VECTOR (0 to 7);
e : out STD_LOGIC_VECTOR (0 to 2));
end encoder;
architecture Behavioral of encoder is
begin

e<=

"000" when i="10000000" else

"001" when i="01000000" else
"010" when i="00100000" else
"011" when i="00010000" else
"100" when i="00001000" else
"101" when i="00000100" else
"110" when i="00000010" else
"111" when i="00000001" else
"000";

end Behavioral;

RTL SCHEMATIC:

TEST BENCH WAVEFORMS:

Summary
Design Name

encoder

Fitting Status

Successful

Software Version

J.36

Device Used

XA9536XL-15-VQ44

Date

10-23-2015, 9:07AM
RESOURCES SUMMARY

Macrocells Used

Pterms Used

Registers Used

Pins Used

3/36 (9%)

12/180 (7%)

0/36 (0%)

11/34 (33%)

Function Block
Inputs Used
16/108 (15%)

PIN RESOURCES

Signal Type
Input
Output
Bidirectional
GCK
GTS
GSR

Required
8
3
0
0
0
0

Mapped
8
3
0
0
0
0

Pin Type
I/O
GCK/IO
GTS/IO
GSR/IO

Used
11
0
0
0

Total
28
3
2
1

GLOBAL RESOURCES

Global clock net(s) used

Global output enable net(s) used
Global set/rest net(s) used

0
0
0
POWER DATA

Macrocells in high performance mode

(MCHP)
Macrocells in low power mode (MCLP)
Total macrocells used (MC)
back to top

0
3
3
print page

2.

Implement an 3 by 8 decoder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity decoder is
Port ( i : in STD_LOGIC_VECTOR (2 downto 0);
d : out STD_LOGIC_VECTOR (0 to 7));
end decoder;
architecture Behavioral of decoder is
begin
d <=

"10000000" when i= "000" else

"01000000" when i="001" else
"00100000" when i="010" else
"00010000" when i="011" else
"00001000" when i="100" else
"00000100" when i="101" else
"00000010" when i="110" else
"00000001";

end Behavioral;

RTL SCHEMATIC:

TEST BENCH WAVEFORMS:

Summary
Design Name

decoder

Fitting Status

Successful

Software Version

J.36

Device Used

XA9536XL-15-VQ44

Date

10-23-2015, 9:45AM
RESOURCES SUMMARY

Macrocells Used

Pterms Used

Registers Used

Pins Used

8/36 (23%)

8/180 (5%)

0/36 (0%)

11/34 (33%)

Function Block
Inputs Used
6/108 (6%)

PIN RESOURCES

Signal Type
Input
Output
Bidirectional
GCK
GTS
GSR

Required
3
8
0
0
0
0

Mapped
3
8
0
0
0
0

Pin Type
I/O
GCK/IO
GTS/IO
GSR/IO

Used
10
0
0
1

Total
28
3
2
1

GLOBAL RESOURCES

Global clock net(s) used

Global output enable net(s) used
Global set/rest net(s) used

0
0
0
POWER DATA

Macrocells in high performance mode

(MCHP)
Macrocells in low power mode (MCLP)
Total macrocells used (MC)
back to top

0
8
8
print page

EXPERIMENT NO: 7

D FLIP-FLOP
1. Design and Implement a D flip-flop.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dff is
Port ( d : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC);
end dff;
architecture Behavioral of dff is
begin
process(d,clk)
begin
if(clk'event and clk = '1') then
q <= d;
end if;
end process;
end Behavioral;

RTL SCHEMATIC:

TEST BENCH WAVEFORMS:

Summary
Design Name

dff

Fitting Status

Successful

Software Version

J.36

Device Used

XA9536XL-15-VQ44

Date

10-23-2015, 12:46PM
RESOURCES SUMMARY

Macrocells Used

Pterms Used

Registers Used

Pins Used

1/36 (3%)

1/180 (1%)

1/36 (3%)

3/34 (9%)

Function Block
Inputs Used
1/108 (1%)

PIN RESOURCES

Signal Type
Input
Output
Bidirectional
GCK
GTS
GSR

Required
1
1
0
1
0
0

Mapped
1
1
0
1
0
0

Pin Type
I/O
GCK/IO
GTS/IO
GSR/IO

Used
2
1
0
0

Total
28
3
2
1

GLOBAL RESOURCES

Signal mapped onto global clock net

(GCK1)

clk
POWER DATA

Macrocells in high performance mode

(MCHP)
Macrocells in low power mode (MCLP)
Total macrocells used (MC)
back to top

0
1
1
print page

EXPERIMENT NO: 8

PARALLEL IN PARALLEL OUT SHIFT REGISTER

1. Design and Implement an 8-bit parallel in parallel out shift register.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pipo is
Port ( d : in STD_LOGIC_VECTOR (7 downto 0);
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (7 downto 0));
end pipo;
architecture Behavioral of pipo is
begin
process
begin
wait until (clk='1');
q<=d;
end process;
end Behavioral;

RTL SCHEMATIC:

TEST BENCH WAVEFORMS:

Summary
Design Name

pipo

Fitting Status

Successful

Software Version

J.36

Device Used

XA9536XL-15-VQ44

Date

10-24-2015, 7:54AM
RESOURCES SUMMARY

Macrocells Used

Pterms Used

Registers Used

Pins Used

8/36 (23%)

8/180 (5%)

8/36 (23%)

17/34 (50%)

Function Block
Inputs Used
8/108 (8%)

PIN RESOURCES

Signal Type
Input
Output
Bidirectional
GCK
GTS
GSR

Required
8
8
0
1
0
0

Mapped
8
8
0
1
0
0

Pin Type
I/O
GCK/IO
GTS/IO
GSR/IO

Used
13
1
2
1

Total
28
3
2
1

GLOBAL RESOURCES

Signal mapped onto global clock net

(GCK1)

clk
POWER DATA

Macrocells in high performance mode

(MCHP)
Macrocells in low power mode (MCLP)
Total macrocells used (MC)
back to top

0
8
8
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EXPERIMENT NO: 9

SHIFT REGISTER
1. Design an 8 bit shift register.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity shiftreg is
Port ( d : in STD_LOGIC_VECTOR (7 downto 0);
q : inout STD_LOGIC_VECTOR (7 downto 0);
load : in STD_LOGIC;
datain : in STD_LOGIC;
clk : in STD_LOGIC);
end shiftreg;
architecture Behavioral of shiftreg is
begin
process(clk)
begin
if(clk'event and clk='1') then
if(load='1') then
q<=d;
else
q(0)<=q(1);
q(1)<=q(2);
q(2)<=q(3);
q(3)<=q(4);
q(4)<=q(5);
q(5)<=q(6);
q(6)<=q(7);
q(7)<=datain;
end if;
end if;
end process;
end Behavioral;

RTL SCHEMATIC:

TEST BENCH WAVEFORMS:

Summary
Design Name

shiftreg

Fitting Status

Successful

Software Version

J.36

Device Used

XA9536XL-15-VQ44

Date

10-24-2015, 10:07AM
RESOURCES SUMMARY

Macrocells Used

Pterms Used

Registers Used

Pins Used

8/36 (23%)

16/180 (9%)

8/36 (23%)

19/34 (56%)

Function Block
Inputs Used
18/108 (17%)

PIN RESOURCES

Signal Type
Input
Output
Bidirectional
GCK
GTS
GSR

Required
10
8
0
1
0
0

Mapped
10
8
0
1
0
0

Pin Type
I/O
GCK/IO
GTS/IO
GSR/IO

Used
15
1
2
1

Total
28
3
2
1

GLOBAL RESOURCES

Signal mapped onto global clock net

(GCK1)

clk
POWER DATA

Macrocells in high performance mode

(MCHP)
Macrocells in low power mode (MCLP)
Total macrocells used (MC)
back to top

0
8
8
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EXPERIMENT NO: 10

SEQUENCE DETECTOR
1. Design a circuit to detect 101 in a given sequence.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity seq is
Port ( rst : in STD_LOGIC;
w : in STD_LOGIC;
clk : in STD_LOGIC;
z : out STD_LOGIC);
end seq;
architecture Behavioral of seq is
type statetype is (A,B,C,D);
signal y:statetype;
begin
process(rst,clk)
begin
if(rst='0') then
y<=A;
elsif(clk'event and clk='1') then
case y is
when A =>

when B =>

when C =>

if (w='0') then
y<=A; else
y<=B;
end if;
if (w='0') then
y<=C; else
y<=B;
end if;
if (w='0') then
y<=A; else
y<=D;
end if;

when D =>

if(w='0') then
y<=C; else
y<=B;
end if;

end case;
end if;
end process;
z<='1' when (y=D) else '0';
end Behavioral;

RTL SCHEMATIC:

TEST BENCH WAVEFORMS:

Summary
Design Name

seq

Fitting Status

Successful

Software Version

J.36

Device Used

XA9536XL-15-VQ44

Date

10-24-2015, 8:35AM
RESOURCES SUMMARY

Macrocells Used

Pterms Used

Registers Used

Pins Used

3/36 (9%)

4/180 (3%)

2/36 (6%)

4/34 (12%)

Function Block
Inputs Used
3/108 (3%)

PIN RESOURCES

Signal Type
Input
Output
Bidirectional
GCK
GTS
GSR

Required
1
1
0
1
0
1

Mapped
1
1
0
1
0
1

Pin Type
I/O
GCK/IO
GTS/IO
GSR/IO

Used
2
1
0
1

Total
28
3
2
1

GLOBAL RESOURCES

Signal mapped onto global clock net

(GCK1)
Signal mapped onto global output enable
net (GSR)

clk
rst

POWER DATA

Macrocells in high performance mode

(MCHP)
Macrocells in low power mode (MCLP)
Total macrocells used (MC)
back to top

0
3
3
print page