0% found this document useful (0 votes)
2K views6 pages

Analog Electronics Assignment (Ee001-3-2-Ae)

When the input voltage is positive: 1) The output of OP-AMP A1 inverts the signal to negative. 2) D1 is forward biased and D2 is reverse biased, allowing the negative signal to pass. 3) The signal returns to positive through feedback and passes through D2 to the output. When the input voltage is negative: 1) The signal passes directly to OP-AMP A2 without passing through diodes. 2) The positive output signal is obtained at Vout. The frequency difference between simulation and hardware is 1 Hz, with the practical frequency being 0.33 Hz.
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
2K views6 pages

Analog Electronics Assignment (Ee001-3-2-Ae)

When the input voltage is positive: 1) The output of OP-AMP A1 inverts the signal to negative. 2) D1 is forward biased and D2 is reverse biased, allowing the negative signal to pass. 3) The signal returns to positive through feedback and passes through D2 to the output. When the input voltage is negative: 1) The signal passes directly to OP-AMP A2 without passing through diodes. 2) The positive output signal is obtained at Vout. The frequency difference between simulation and hardware is 1 Hz, with the practical frequency being 0.33 Hz.
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 6

ANALOG ELECTRONICS ASSIGNMENT (EE001-3-2-AE)

NAME : MAULANA AJI MARWANTO


ID NUMBER : TP017422
INTAKE CODE : UC2F0909ME
SUBMISSION DATE: 28 JANUARY 2010

LECTURER NAME : HARIKRISHNAN RAMIAH


SCHEMATIC
6 R3

Calculation for C1
R1 D1

7
D2 1
V1
A1 >ω
A2 R A 3 C1
81
5 Vrms 0 6
50 Hz A3
0° 1
0 12 R2 13 C 1< C1 D3 D4
R A 3 (2 f )
7 R4

1 8
C 1<
75(2 ×6 0) C2
0
Figure1: Schematic circuit
C 1<1.11 x 10−4 F
Calculation for R1 and R3

Ideal OPAMP condition (virtual ground) V +¿ ≅ V−¿≅ 0 ¿ ¿


Calculation for C2
Apply KCL to the inverting node:
π
( R 4 +r ) C2= 5 ω
I ¿ + I out + I −¿=0 ¿

V −¿−V V −¿−V π 1
Out C 2=
+ +0=0 ¿ ¿ 5 (2 f ) ( R 4 +r )
¿

R1 R3
π 1
0−V ¿ 0−V Out C 2=
+ + 0=0 5 (2 x 6 0) (1 0 000+0 )
R1 R3

−V Out V ¿ C 2=52.3 ×10−6 F


=
R3 R1 C 2=52.3 μF
V Out −R 3
=
V¿ R1

Calculation for R2

Ideal OPAMP condition (virtual ground) V +¿ ≅ V−¿≅ 0 ¿ ¿

Apply KCL to the non-inverting node

V +¿−V
+ 0+0=0 ¿
¿

R2

V +¿ V ¿
= ¿
R2 R 2

V Out V ¿
=
R2 R 2

V Out R 2
=
V ¿ R2

V Out
=1
V¿
SIMULATION RESULT
R3

10kΩ
D1
4
D1N4148
R1 U1
2 D2 7 U2
10kΩ 6 3 7 U3
V1 3 D1N4148 6 3

7 2 6
LM107J
12 Vrms 2
4 LM107J
60 Hz
4 LM107J C1 D3
0° 3.3pF D4
GND D1N4148
D1N4148
R2

10kΩ R4

10kΩ
C2
1µF
GND

Figure 2: Simulation circuit GND

Figure 3: V out (simulation)

Figure 4: Vs out (simulation)

Figure 5: V peak (simulation)


HARDWARE OUTPUT

A2 R3 A3 C1 D3
A1 D1 D2
R1 D4

C2

R4
R2

Figure 6: Schematic circuit

Figure 7: V out (practical)

Figure 8: Vs out (practical)

Figure 9: V peak (practical)

1 box in the oscilloscope is equal with 1 s. The frequency difference from simulation and the practical is:

1
f ¿= =1 Hz
1

1
f prac = =0.33 Hz
3s
EXPLANATION
 Positive half cycle on the AC signal

R1 D1
4 1
V1 2 5
A1
5 Vrms 3
50 Hz 0 D2 A2

0

When positive input voltage signal going to OP-AMP A1 the output in A1 is inverted to the negative output
signal voltage. The negative voltage signal is now able to pass through to the D1 because the negative
voltage signal forward-biased and D2 is in Reverse-bias, so we don’t have some signals passing through on
the that place. Therefore, the negative signal will going back because there is a feedback to the inverting
input of A1 and change to positive signal voltage. And then the signal will pass through D2. This signal
will be same at Vout because input for Op-Amp A2 that acts as a buffer is non-inverting.
3 R2 2
V1 1
5 Vrms A2
50 Hz
0° 0

When positive input voltage signal going to this part, the input voltage signal will go to OP-AMP A2
directly and will not pass through Diode (D2) because it’s an open circuit. Positive voltage signal can be
obtain in Vout.

 Negative half cycle in the AC Signal

R3

4 R1 6
V1 D2
1 2
A1
5 Vrms 0 3
50 Hz A2
0° 0

When negative input voltage signal going to the output in Op-Amp A1, it’s inverted to positive output
voltage signal. This voltage signal will pass to the D2, because of the Forward-biases diode. Then the
voltage signal will pass to Op-Amp A2, positive voltage signal can be obtain in Vout.

3 R3

D1
D2
2 4
A1
V1 0 5
5 Vrms A2
50 Hz
0° 0
1 R2

When negative input voltage signal will going straight away to OP-AMP A2 and will also pass through D2
and D1. This is because the negative voltage signal has Forward-biases at the D2 and D1. Both negative
voltage signals will feedback to the same path.
 Peak Detector
Vout 1
A3
6

C1 D3 D4

7 R4

8
Vpeak
C2
0

During the positive half-cycle the output of Op-Amp A3 is positive because the input is non-inverting.
Therefore, D3 is in Reverse-bias and D4 is in Forward-bias. C2 is charges through D4 until V peak reaches the
highest positive value of Vout. Ideally Vout will be decay or discharge as fast as the envelope of V out changes.
That decay will be through the R4 and D3. And because of this decay, there is a small peak formed in signal
wave.

CONCLUSION
Full wave Rectifier operational amplifier with peak detector circuit is the circuit that has a function to
detect the amplitude of audio signal.
During the assignment, we must do the calculation well, because if we don’t do that we can’t reach the
signal waveform that we suppose to find them in the basic shape of Full wave rectifier. And there are some
different output results if we compare from the simulation and the practical. It happen because of there aren’t a
same component when I search in the market .So, I used the different component in my practical.

You might also like