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Vlsi Lab Manual

This document describes the objectives and list of experiments for the VLSI Design Laboratory course EC6612. The objectives are to learn hardware description languages like Verilog and VHDL, fundamental principles of VLSI circuit design in digital and analog domains, and hands-on design experience using EDA tools. The list of experiments includes FPGA-based experiments involving HDL design, simulation, synthesis, mapping, and testing of modules like counters and adders. It also includes IC design experiments involving design and simulation of a differential amplifier, layout generation, and synthesis of circuits using standard cells.

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Sathya Vignesh
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153 views

Vlsi Lab Manual

This document describes the objectives and list of experiments for the VLSI Design Laboratory course EC6612. The objectives are to learn hardware description languages like Verilog and VHDL, fundamental principles of VLSI circuit design in digital and analog domains, and hands-on design experience using EDA tools. The list of experiments includes FPGA-based experiments involving HDL design, simulation, synthesis, mapping, and testing of modules like counters and adders. It also includes IC design experiments involving design and simulation of a differential amplifier, layout generation, and synthesis of circuits using standard cells.

Uploaded by

Sathya Vignesh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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EC6612

VLSI DESIGN LABORATORY

LTPC
0032

OBJECTIVES:
To learn Hardware Descriptive Language(Verilog/VHDL)
To learn the fundamental principles of VLSI circuit design in digital and
analog domain
To familiarise fusing of logical modules on FPGAs
To provide hands on design experience with professional design (EDA)
platforms.
LIST OF EXPERIMENTS FPGA BASED EXPERIMENTS.
1. HDL based design entry and simulation of simple counters, state machines,
adders (min 8 bit) and multipliers (4 bit min).
2. Synthesis, P&R and post P&R simulation of the components simulated in (I)
above. Critical paths and static timing analysis results to be identified. Identify and
verify possible conditions under which the blocks will fail to work correctly.
3. Hardware fusing and testing of each of the blocks simulated in (I). Use of either
chipscope feature (Xilinx) or the signal tap feature (Altera) is a must. Invoke the
PLL and demonstrate the use of the PLL module for clock generation in FPGAs.
IC DESIGN EXPERIMENTS: (BASED ON CADENCE / MENTOR
GRAPHICS / EQUIVALENT)
4. Design and simulation of a simple 5 transistor differential amplifier. Measure
gain, ICMR, and CMRR
5. Layout generation, parasitic extraction and resimulation of the circuit designed
in (I)
6. Synthesis and Standard cell based design of an circuits simulated in 1(I) above.
Identification of critical paths, power consumption

UP COUNTER
//----------------------------------------------------// Design Name : up_counter
// File Name
: up_counter.v
// Function
: Up counter
// Coder
: Deepak
//----------------------------------------------------module up_counter
(
out
, // Output of the counter
enable , // enable for counter
clk
, // clock Input
reset
// reset Input
);
//----------Output Ports-------------output [7:0] out;
//------------Input Ports-------------input enable, clk, reset;
//------------Internal Variables-------reg [7:0] out;
//-------------Code Starts Here------always @(posedge clk)
if (reset) begin
out <= 8'b0 ;
end else if (enable) begin
out <= out + 1;
end
endmodule

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