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Design of Io Pad

This document describes the design of an I/O PAD circuit and calculates its power consumption in two modes: as an input and as an output. The objectives are to study the I/O PAD design and calculate power for a bidirectional I/O PAD. Schematics and transistor sizing are provided for the I/O PAD circuit. Transient analyses are performed to calculate current and power dissipation, which is found to be 82.67 femtowatts for input mode and 890 picowatts for output mode.

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Ravi Tej Gunisetty
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81 views

Design of Io Pad

This document describes the design of an I/O PAD circuit and calculates its power consumption in two modes: as an input and as an output. The objectives are to study the I/O PAD design and calculate power for a bidirectional I/O PAD. Schematics and transistor sizing are provided for the I/O PAD circuit. Transient analyses are performed to calculate current and power dissipation, which is found to be 82.67 femtowatts for input mode and 890 picowatts for output mode.

Uploaded by

Ravi Tej Gunisetty
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Digital IC Design Lab (Fall Sem 2014-15)

Experiment Date:
Submitted Date:
Name:
M.Tech-VLSI DESIGN
15MVDxxxx

TITLE: Design of I/O PAD


OBJECTIVES:
1. To study the I/O PAD design and calculate the Power for
Bidirectional I/O PAD i.e. I/O PAD as Input and Output.
CIRCUIT DIAGRAM:
Transistor Sizing:
PMOS Transistor (M1):-

NMOS Transistor (M2):-

NMOS transistor: gpdk090_nmos1v


Width: 310nm
Length: 100nm

NMOS transistor: gpdk090_nmos1v


Width: 120nm Length: 100nm

A) Schematic diagram of I/O PAD as Input

B) Power calculation for I/O PAD as Input :1. VDD = 1.5 V

3. Enable = 1 (1.5 V)

2. Data In

LOW LEVEL
0V

PULSE VOLTAGE (Vpulse) Data In


HIGH LEVEL WIDTH PERIOD DELAY TIME
1.5 V
10ns
20ns
0ns
1

RISE TIME
1ps

FALL TIME
1ps

Digital IC Design Lab (Fall Sem 2014-15)


Transient Analysis of I/O PAD as Input

IC = 55.11 fA
Input Power= (VDD * IC)/No. of cycles
= (1.5 * 55.11)/3 fA = 82.67 fW
C) Schematic diagram of I/O PAD as Output

D) Power calculation for I/O PAD as Output


1. VDD = 1.5 V

3. Enable = 0 (0 V)

3. Data In

LOW LEVEL
1.5

PULSE VOLTAGE (Vpulse) Data In


HIGH LEVEL PERIOD WIDTH DELAY TIME
1.5
20ns
10ns
0ns
2

RISE TIME
1ps

FALL TIME
1ps

Digital IC Design Lab (Fall Sem 2014-15)


4. PAD In

LOW LEVEL
1.5

PULSE VOLTAGE (Vpulse) Data In


HIGH LEVEL PERIOD WIDTH DELAY TIME
1.5
10ns
5ns
0ns

RISE TIME
1ps

FALL TIME
1ps

Transient Analysis of I/O PAD as Output

IC = 3.56 fA
Input Power= (VDD * IC)/No. of cycles
= (1.5 * 3.56)/6 fA = 890 pW

CONCLUSION:
1. Power Dissipation when I/O PAD work as Input is 82.67fW.
2. Power Dissipation when I/O PAD work as Output is 890 pW.

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