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Design For Testability Syllabus

This document outlines the units of study for an M.Tech course focused on VLSI design. The 5 units cover: 1) introduction to testing philosophy and fault modeling; 2) logic and fault simulation algorithms; 3) testability measures including controllability, observability, and scan design; 4) built-in self-test techniques like BIST and delay fault testing; 5) the boundary scan standard for testing connections between integrated circuits. Students will use textbooks on electronic testing, digital systems design, and testing and testability of digital circuits to support their learning across these topics.

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Ashraf Ali
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739 views

Design For Testability Syllabus

This document outlines the units of study for an M.Tech course focused on VLSI design. The 5 units cover: 1) introduction to testing philosophy and fault modeling; 2) logic and fault simulation algorithms; 3) testability measures including controllability, observability, and scan design; 4) built-in self-test techniques like BIST and delay fault testing; 5) the boundary scan standard for testing connections between integrated circuits. Students will use textbooks on electronic testing, digital systems design, and testing and testability of digital circuits to support their learning across these topics.

Uploaded by

Ashraf Ali
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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M.Tech.

(VLSI/ VLSI DESIGN/VLSI SYSTEM DESIGN)-R13 Regulations


JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
M. Tech I Year II Sem. (VLSI/VLSI Design/VLSI System Design)
DESIGN FOR TESTABILITY
UNIT -I:
Introduction to Testing:
Testing Philosophy, Role of Testing, Digital and Analog VLSI Testing, VLSI Technology Trends
affecting Testing, Types of Testing, Fault Modeling: Defects, Errors and Faults, Functional Versus
Structural Testing, Levels of Fault Models, Single Stuck-at Fault.
UNIT -II:
Logic and Fault Simulation:
Simulation for Design Verification and Test Evaluation, Modeling Circuits for Simulation, Algorithms
for True-value Simulation, Algorithms for Fault Simulation, ATPG.
UNIT -III:
Testability Measures:
SCOAP Controllability and Observability, High Level Testability Measures, Digital DFT and Scan
Design: Ad-Hoc DFT Methods, Scan Design, Partial-Scan Design, Variations of Scan.
UNIT -IV:
Built-In Self-Test:
The Economic Case for BIST, Random Logic BIST: Definitions, BIST Process, Pattern Generation,
Response Compaction, Built-In Logic Block Observers, Test-Per-Clock, Test-Per-Scan BIST
Systems, Circular Self Test Path System, Memory BIST, Delay Fault BIST.
UNIT -V:
Boundary Scan Standard:
Motivation, System Configuration with Boundary Scan: TAP Controller and Port, Boundary Scan Test
Instructions, Pin Constraints of the Standard, Boundary Scan Description Language: BDSL
Description Components, Pin Descriptions.
TEXT BOOKS:
1. Essentials of Electronic Testing for Digital, Memory and Mixed Signal VLSI Circuits - M.L.
Bushnell, V. D. Agrawal, Kluwer Academic Pulishers.
REFERENCE BOOKS:
1. Digital Systems and Testable Design - M. Abramovici, M.A.Breuer and A.D Friedman, Jaico
Publishing House.
Digital Circuits Testing and Testability - P.K. Lala, Academic Press.

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