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Precision-Aware Self-Quantizing Hardware Architectures For The Discrete Wavelet Transform

This paper proposes precision-aware hardware architectures for implementing the discrete wavelet transform (DWT) in a bit-parallel or digit-serial manner. The architectures allow customizing the precision of a multilevel DWT to a given error tolerance requirement, ensuring an energy-efficient implementation. This increases the applicability of DWT-based algorithms like JPEG 2000 to energy-constrained platforms.

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Vij Ay
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24 views2 pages

Precision-Aware Self-Quantizing Hardware Architectures For The Discrete Wavelet Transform

This paper proposes precision-aware hardware architectures for implementing the discrete wavelet transform (DWT) in a bit-parallel or digit-serial manner. The architectures allow customizing the precision of a multilevel DWT to a given error tolerance requirement, ensuring an energy-efficient implementation. This increases the applicability of DWT-based algorithms like JPEG 2000 to energy-constrained platforms.

Uploaded by

Vij Ay
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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PRECISION-AWARE SELF-QUANTIZING HARDWARE

ARCHITECTURES FOR THE DISCRETE WAVELET


TRANSFORM
ABSTRACT:
This paper presents designs for both bit-parallel (BP) and digit-serial (DS) precisionoptimized implementations of the discrete wavelet transform (DWT), with specific consideration
given to the impact of depth (the number of levels of DWT) on the overall computational
accuracy. These methods thus allow customizing the precision of a multilevel DWT to a given
error tolerance requirement and ensuring an energy-minimal implementation, which increases the
applicability of DWT-based algorithms such as JPEG 2000 to energy-constrained platforms and
environments.

EXISTING SYSTEM:
The basic principle behind the lifting based scheme is to decompose the finite impulse
response (FIR) filters in wavelet transform into a finite sequence of simple filtering steps.

EXISTING SYSTEM ALGORITHM:


Lifting Based Discrete wavelet Transform

EXISTING SYSTEM DRAWBACKS:

Increase the area


Latency will be high

PROPOSED SYSTEM BLOCK DIAGRAM:

PROPOSED SYSTEM ADVANTAGES:

Improve the in hardware resources


Improve the execution time
Avoiding overflows

SOFTWARE REQUIREMENTS:

ModelSim 6.4c
Xilinx 13.2
Matlab 7.14(R2012a)

HARDWARE REQUIREMENT:

FPGA Spartan 3(xc3s400 pq 208)

REAL TIME EXAMPLE:

Signal coding,
data compression.
Implemented as analog filter bank in biomedical signal processing for design of lowpower pacemakers
Ultra-wideband (uwb) wireless communication

FUTURE ENHANCEMENT:
For future using Matlab software, we obtain the PSNR value is better than our proposed
method.

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