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Systemverilog For Verification Training: Session 7

This document contains an agenda for a SystemVerilog for Verification training session covering randomization and constraints. The session includes topics such as constraint blocks, dynamic constraint changes, randomize() functions, random variable control, random case statements, random sequences, and a lab exercise. The training is presented by Sameh El-Ashry, a hardware design verification engineer at Mentor Graphics Egypt.

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Youssef M. Ramzy

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0% found this document useful (0 votes)

42 views27 pages

Systemverilog For Verification Training: Session 7

Uploaded by

Youssef M. Ramzy

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

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SystemVerilog For Verification Training

Session 7
Sameh El-Ashry
Hardware Design Verification Engineer
Mentor-Graphics Egypt

Randomization & Constraints

(2)

9 Oct 2015

Constraint Block

9 Oct 2015

Constraint Block Examples

9 Oct 2015

Constraint Block : Overriding

9 Oct 2015

Constraint Block : Iteration

9 Oct 2015

Dynamic Constraint Changes

9 Oct 2015

Dynamic Constraint Changes in SV

9 Oct 2015

Constraint Block : Implication ( ->, if else )

9 Oct 2015

Constraint Block : dist - 1

9 Oct 2015

Constraint Block : dist - 2

9 Oct 2015

randomize()

9 Oct 2015

randomize() with

9 Oct 2015

randomize() Inline Control

9 Oct 2015

Non-OO Randomization

9 Oct 2015

Random Variable Control

9 Oct 2015

Constraint Control

9 Oct 2015

Pre and Post Randomization

9 Oct 2015

Random Case

9 Oct 2015

Random Sequences

9 Oct 2015

Weighted Random Sequences

9 Oct 2015

Random Sequence Conditionals

9 Oct 2015

Random Sequence Jumps

9 Oct 2015

Lab for Session 6(Lab -)

Instructions:

9 Oct 2015

(Lab) Simulation output

9 Oct 2015

Thank You !

Presented by Sameh El-Ashry

[email protected]
https://eg.linkedin.com/pub/sameh-el-ashry/3b/560/22b

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Systemverilog For Verification Training: Session 7

Uploaded by

Systemverilog For Verification Training: Session 7

Uploaded by

SystemVerilog For Verification Training

Randomization & Constraints

Constraint Block Examples

Constraint Block : Overriding

Constraint Block : Iteration

Dynamic Constraint Changes

Dynamic Constraint Changes in SV

Constraint Block : Implication ( ->, if else )

Constraint Block : dist - 1

Constraint Block : dist - 2

randomize() Inline Control

Random Variable Control

Pre and Post Randomization

Weighted Random Sequences

Random Sequence Conditionals

Random Sequence Jumps

Lab for Session 6(Lab -)

(Lab) Simulation output

Presented by Sameh El-Ashry

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