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Async Fifo Project

This document describes an asynchronous FIFO design. It contains an introduction stating that an asynchronous FIFO uses two asynchronous clock domains for writing and reading data from a FIFO buffer. It then discusses the FIFO structure using write and read pointers, gray code counters to generate the pointers, and asynchronous logic to compare the pointers and generate full and empty signals across clock domains. The architecture partitions the design into the FIFO buffer and asynchronous pointer comparison logic.

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Vamsikrishna Vanapalli
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2K views11 pages

Async Fifo Project

This document describes an asynchronous FIFO design. It contains an introduction stating that an asynchronous FIFO uses two asynchronous clock domains for writing and reading data from a FIFO buffer. It then discusses the FIFO structure using write and read pointers, gray code counters to generate the pointers, and asynchronous logic to compare the pointers and generate full and empty signals across clock domains. The architecture partitions the design into the FIFO buffer and asynchronous pointer comparison logic.

Uploaded by

Vamsikrishna Vanapalli
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Asynchronous FIFO

By
Sampath .G (4009)
Vamsi krishna .V (4021)

Contents
Introduction
FIFO structure
Architecture
Asynchronous FIFO pointers
Gray code counters
Full and Empty detection
Asynchronous generation of full and empty

Introduction
An asynchronous FIFO refers to a FIFO design where data
values are written sequentially into a FIFO buffer using one clock
domain, and the data values are sequentially read from the same
FIFO buffer using another clock domain, where the two clock
domains are asynchronous to each other.
One common technique for designing an asynchronous FIFO is
to use Gray code pointers that are synchronized into the opposite
clock domain before generating synchronous FIFO full or empty
status signals.

FIFO structure
Data in

FIFO full
FIFO half

Write to FIFO
Clk write
Rst

FIFO
Buffer

FIFO empty
Data out
Read from FIFO
Clk read

Architecture

Figure: FIFO partitioning with asynchronous pointer comparison logic

Asynchronous FIFO pointers


Write Pointer:
The write pointer always points to the next word to be written;
therefore, on reset, both pointers are set to zero, which also happens
to be the next FIFO word location to be written.
Read Pointer:
The read pointer always points to the current FIFO word to be read.
The fact that the read pointer is always pointing to the next FIFO
word to be read means that the receiver logic does not have to use
two clock periods to read the data word.

Gray code counter

Figure: Dual n-bit Gray code counter style

Full and empty detection

Figure: FIFO direction quadrant detection circuitry

Contd..

Figure: FIFO is going full because the wptr trails the rptr by one quadrant

Asynchronous generation of Full and empty

Figure: Asynchronous pointer comparison to assert full and empty

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