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Digital System Design Homework

This document contains VHDL code for a digital system design homework assignment. It includes code for a 4-to-1 multiplexer, 4-to-1 demultiplexer, and a combined multiplexer/demultiplexer system. The multiplexer takes 4 inputs and selects one to output based on a 2-bit selection signal. The demultiplexer takes one input and directs it to one of 4 outputs based on a 2-bit selection signal. The combined system uses a multiplexer and demultiplexer connected by a signal wire to route any of the 4 inputs to any of the 4 outputs based on the 2 selection signals.

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HassanNajjar
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48 views5 pages

Digital System Design Homework

This document contains VHDL code for a digital system design homework assignment. It includes code for a 4-to-1 multiplexer, 4-to-1 demultiplexer, and a combined multiplexer/demultiplexer system. The multiplexer takes 4 inputs and selects one to output based on a 2-bit selection signal. The demultiplexer takes one input and directs it to one of 4 outputs based on a 2-bit selection signal. The combined system uses a multiplexer and demultiplexer connected by a signal wire to route any of the 4 inputs to any of the 4 outputs based on the 2 selection signals.

Uploaded by

HassanNajjar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Ajman University of Science & Technology

College Engineering
Department of Electrical Engineering

AJM 2134400 Digital System Design : 20131

Digital System Design


Homework
Done by:
Yahya Mohamed Noureldin 201110319

21th of October 2013

1-Demultiplexer Part

Library ieee;
use ieee.std_logic_1164.all;
Entity DemuxMine is
PORT(
I: in std_logic;
SS: in std_logic_vector(1 downto
0);
O0: out std_logic;
O1: out std_logic;
O2: out std_logic;
O3: out std_logic
);
end DemuxMine;

Architecture behav2 of DemuxMine is


begin
Process(I,SS)
Begin
if(SS="00") then
O0 <= I; O1 <= '0'; O2 <= '0'; O3 <= '0';
elsif(SS="01") then
O0 <= '0'; O1 <= I; O2 <= '0'; O3 <= '0';
elsif(SS="10") then
O0 <= '0'; O1 <= '0'; O2 <= I; O3 <= '0';
elsif(SS="11") then
O0 <= '0'; O1 <= '0'; O2 <= '0'; O3 <= I;
else
O0 <= 'X'; O1 <= 'X'; O2 <= 'X'; O3 <= 'X';
end if;
end Process;
End behav2;

2-Multiplexer Part

Library ieee;
use ieee.std_logic_1164.all;
Entity MuxMine is
PORT(
I0: in std_logic;
I1: in std_logic;
I2: in std_logic;
I3: in std_logic;
S: in std_logic_vector(1 downto
0);
O: out std_logic
);
end MuxMine;

Architecture behavio of MuxMine is


BEGIN
Process(I0,I1,I2,I3,S)
Begin
if(S="00") then
O <= I0;
elsif(S="01") then
O <= I1;
elsif(S="10") then
O <= I2;
elsif(S="11") then
O <= I3;
else
O <= 'X';
end if;
end Process;
end behavio;

Final Solution
--Mux part
Library ieee;
use ieee.std_logic_1164.all;
Entity MuxMine is
PORT(
I0: in std_logic;
I1: in std_logic;
I2: in std_logic;
I3: in std_logic;
S: in std_logic_vector(1
downto 0);
O: out std_logic
);
end MuxMine;
Architecture behavio of
MuxMine is
BEGIN
Process(I0,I1,I2,I3,S)
Begin
if(S="00")
then
O <= I0;
elsif(S="01")
then
O <= I1;
elsif(S="10")
then
O <= I2;
elsif(S="11")
then
O <= I3;
else
O <= 'X';

--Demux part
--Combination part
Library ieee;
Library ieee;
use
use ieee.std_logic_1164.all;
ieee.std_logic_1164.all;
Entity DemuxMine is
PORT(
I: in std_logic;
SS: in
std_logic_vector(1
downto 0);
O0: out std_logic;
O1: out std_logic;
O2: out std_logic;
O3: out std_logic
);
end DemuxMine;
Architecture behav2 of
DemuxMine is
begin
Process(I,SS)
Begin
if(SS="00")
then
O0 <=
I; O1 <= '0'; O2 <= '0';
O3 <= '0';
elsif(SS="01")
then
O0 <=
'0'; O1 <= I; O2 <= '0';
O3 <= '0';
elsif(SS="10")

end if;

end Process;
end behavio;

then
O0 <=
'0'; O1 <= '0'; O2 <= I;
O3 <= '0';
elsif(SS="11")
then
O0 <=
'0'; O1 <= '0'; O2 <=
'0'; O3 <= I;
else
O0 <=
'X'; O1 <= 'X'; O2 <=
'X'; O3 <= 'X';
end if;
end Process;
End behav2;

Entity Combo is
PORT(
i0: in std_logic; i1: in std_logic; i2: in std_logic; i3: in
std_logic;
S1: in std_logic_vector(1 downto 0); S2: in std_logic_vector(1
downto 0);
OT0:out std_logic; OT1:out std_logic; OT2:out std_logic;
OT3:out std_logic
);
end Combo;
Architecture FullDesign of Combo is
Signal wire: std_logic;
--------------------------Component #1 defin:Component MuxMine is
PORT(
I0: in std_logic;
I1: in std_logic;
I2: in std_logic;
I3: in std_logic;
S: in std_logic_vector(1 downto 0);
O: out std_logic
);
end Component;
----------------------------Component #2 defin:Component DemuxMine is
PORT(
I: in std_logic;
SS: in std_logic_vector(1 downto 0);
O0: out std_logic;
O1: out std_logic;
O2: out std_logic;
O3: out std_logic
);
end Component;
--------------------------Begin
Block1: MuxMine PORT MAP(
I0=>i0, I1=>i1, I2=>i2, I3=>i3, S=>S1, O=>wire
);
Block2:
DemuxMine PORT MAP(
I=>wire, SS=>S2, O0=>OT0, O1=>OT1, O2=>OT2, O3=>OT3
);
End FullDesign;

Simulation

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