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SOC Design Verif White Paper

The document discusses verification methodologies for system-on-chip (SoC) designs including software simulation, hardware acceleration, emulation, formal verification techniques like equivalence checking and model checking, and semi-formal verification using assertions and coverage. It also covers languages for SoC design like SystemC, SystemVerilog, and challenges in verifying designs with embedded processors.

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Srinivas Cheruku

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0% found this document useful (0 votes)

109 views44 pages

SOC Design Verif White Paper

Uploaded by

Srinivas Cheruku

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

You are on page 1/ 44

intelop

SoC/ASIC/SoC-FPGA/S-ASIC
Design and Verification
Methodology

Intelop Corporation
4800 Great America Pkwy.
Ste-201
Santa Clara, CA. 95054
Ph: 408-496-0333, Fax: 408-496-0444
www.intelop.com
Courtesy of Cadence design

intelop

Challenges in Embedded Systems Design

intelop

Critical Issues

intelop

Verification Effort size

intelop

Overview of Verification Methodologies

intelop

Software Simulation

intelop

Software Simulation

intelop

Hardware Acceleration

intelop

Emulation

intelop

Overview of Verification Methodologies

Formal Verification

intelop

Formal Verification : equivalence Check

intelop

Formal Verification : equivalence Check

intelop

Theorem Proving

intelop

Formal Verification : Model Check

intelop

Formal Verification : Model Checking

intelop

Formal Verification : Challenges

intelop

Semi-Formal Verification : Assertion

intelop

Semi-Formal Verification : Coverage

intelop

Semi-Formal Verification : Coverage

intelop

Semi-Formal Verification : Coverage

intelop

Semi-Formal Verification

intelop

Design Complexity

intelop

Language Heritage for SoC Design

intelop

SystemC in SoC Design

intelop

SystemC in SoC Design

intelop

Abstraction Levels of SystemC

intelop

Vera (Synopsys)

intelop

Vera (Synopsys)

intelop

System Verilog

intelop

System Verilog

intelop

Key Components of System Verilog

intelop

System Design Language Summary

intelop

SoC Verification

intelop

Embedded Processor Cores in SoC

intelop

Models of Embedded Processor

intelop

Models of Embedded Processor

intelop

Models of Embedded Processor

intelop

Verification with Embedded Processor

intelop

Verification with Embedded Processor

intelop

Simultaneous SoC design Flow

intelop

Tool utilized in HW-SW Co-Verification

intelop

Tool utilized in Co-Simulation

intelop

Conclusion

intelop

Conclusion

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SOC Design Verif White Paper

Uploaded by

SOC Design Verif White Paper

Uploaded by

intelop

Challenges in Embedded Systems Design

Verification Effort size

Overview of Verification Methodologies

Overview of Verification Methodologies

Formal Verification : equivalence Check

Formal Verification : equivalence Check

Formal Verification : Model Check

Formal Verification : Model Checking

Formal Verification : Challenges

Semi-Formal Verification : Assertion

Semi-Formal Verification : Coverage

Semi-Formal Verification : Coverage

Semi-Formal Verification : Coverage

Language Heritage for SoC Design

SystemC in SoC Design

SystemC in SoC Design

Abstraction Levels of SystemC

Key Components of System Verilog

System Design Language Summary

Embedded Processor Cores in SoC

Models of Embedded Processor

Models of Embedded Processor

Models of Embedded Processor

Verification with Embedded Processor

Verification with Embedded Processor

Simultaneous SoC design Flow

Tool utilized in HW-SW Co-Verification

Tool utilized in Co-Simulation

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