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EXP 1: To Model Logic Gates (A) As Indivisible Entities, (B) Using NAND Gates and (C) Using NOR Gates

The document describes experiments modeling logic gates and adders in VHDL. It includes: 1. Modeling basic logic gates like AND, OR, NOT using both NAND and NOR gates. 2. Modeling a half adder and full adder, with the full adder composed of two half adders. 3. Modeling a 4-bit adder-subtractor using four full adders, where the B input is XOR'd with a mode select to determine whether addition or subtraction occurs.

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28 views5 pages

EXP 1: To Model Logic Gates (A) As Indivisible Entities, (B) Using NAND Gates and (C) Using NOR Gates

The document describes experiments modeling logic gates and adders in VHDL. It includes: 1. Modeling basic logic gates like AND, OR, NOT using both NAND and NOR gates. 2. Modeling a half adder and full adder, with the full adder composed of two half adders. 3. Modeling a 4-bit adder-subtractor using four full adders, where the B input is XOR'd with a mode select to determine whether addition or subtraction occurs.

Uploaded by

Lakshay
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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EXP 1 : To model logic gates (a) as indivisible entities, (b) using NAND gates and

(c) using NOR gates.


entity basicGates_entity is
port (
inp1,inp2:in bit;
and_out,or_out,not_out,nand_and,nand_or,nand_not,nor_and,nor_or,nor_not:out bit
);
end basicGates_entity;

architecture basicGates_arch of basicGates_entity is


begin
and_out <= inp1 and inp2;
or_out <= inp1 or inp2;
not_out <= not(inp1);
nand_and <= (inp1 nand inp2) nand (inp1 nand inp2);
nand_or <= (inp1 nand inp1) nand (inp2 nand inp2);
nand_not <= inp1 nand inp1;
nor_and <= (inp1 nor inp1) nor (inp2 nor inp2);
nor_or <= (inp1 nor inp2) nor (inp1 nor inp2);
nor_not <= inp1 nor inp1;
end architecture;

EXP 2: To model (a) a half adder, (b) a full adder using two half adders and (c) a
4-bit adder-subtractor.
Code for part (a) and (b)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity half_adder_entity is
port(
a,b : in std_logic;
s,c : out std_logic
);
end half_adder_entity;
architecture half_adder_arch of half_adder_entity is
begin
s <= a xor b;
c <= a and b;
end half_adder_arch;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity full_adder_entity is
port(
inp1,inp2,inp3 : in std_logic;
sum,carry : out std_logic
);
end full_adder_entity;
architecture full_adder_arch of full_adder_entity is
signal x,y,z:std_logic;
component half_adder_entity
port(
a,b:in std_logic;
s,c:out std_logic
);
end component;
begin
H1:half_adder_entity port map(inp1,inp2,x,y);
H2:half_adder_entity port map(x,inp3,sum,z);
carry <= y or z;
end full_adder_arch;

Code for part (b)

LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity fulladder_entity is
port (
inp1,inp2,cin:in std_logic;
s,c:out std_logic
);
end fulladder_entity;
architecture fulladder_arch of fulladder_entity is
begin
s <= inp1 xor inp2 xor cin;
c <= (inp1 and inp2) or (inp2 and cin) or (inp1 and cin);
end architecture;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity addersubtractor_entity is
port(
a0,a1,a2,a3,b0,b1,b2,b3,mode:in std_logic;
out0,out1,out2,out3,carry:out std_logic
);
end addersubtractor_entity;
architecture addersubtractor_arch of addersubtractor_entity is
signal carry0,carry1,carry2,temp0,temp1,temp2,temp3:std_logic;
component fulladder_entity
port (
inp1,inp2,cin:in std_logic;
s,c:out std_logic
);
end component;
begin
temp0<=b0 xor mode;
temp1<=b1 xor mode;
temp2<=b2 xor mode;
temp3<=b3 xor mode;
FA1:fulladder_entity port map(a0,temp0,mode,out0,carry0);
FA2:fulladder_entity port map(a1,temp1,carry0,out1,carry1);
FA3:fulladder_entity port map(a2,temp2,carry1,out2,carry2);

FA4:fulladder_entity port map(a3,temp3,carry2,out3,carry);


end architecture;

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