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Analog and Digital VLSI Design: Lecture 2: VLSI Design Flow & Challenges in VLSI Design

The document discusses the VLSI design flow, which includes steps from design specification to fabrication. It involves behavioral description, RTL description using HDL, logic synthesis, verification and testing at different levels, layout including floorplanning and placement & routing, and layout verification and testing. The document also discusses challenges in digital design such as issues related to scaling, complexity, abstraction levels, and design for test. It emphasizes that with each generation, more functionality can be integrated due to technology shrinkage.

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Amandeep Gupta
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38 views

Analog and Digital VLSI Design: Lecture 2: VLSI Design Flow & Challenges in VLSI Design

The document discusses the VLSI design flow, which includes steps from design specification to fabrication. It involves behavioral description, RTL description using HDL, logic synthesis, verification and testing at different levels, layout including floorplanning and placement & routing, and layout verification and testing. The document also discusses challenges in digital design such as issues related to scaling, complexity, abstraction levels, and design for test. It emphasizes that with each generation, more functionality can be integrated due to technology shrinkage.

Uploaded by

Amandeep Gupta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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CKV

Analog and Digital VLSI Design


EEE F313/INSTR
F313

Lecture 2: VLSI Design Flow & Challenges in


VLSI Design

CKV

Front
End

VLSI Design Flow

FAB

Layout
Verification
and Testing

Design
Specification
Behavioral
Description

Physical layout

RTL Description
(HDL)

Floor planning and


Automatic Place
and Route

Functional
Verification
and Testing

Logic
Synthesis

CKV

Process
es

Logical
Verification
and Testing
Gate-level Netlist

Back
End

Challenges in Digital Design

CKV

Microscopic issues

ultra-high speeds

power dissipation and


supply rail drop

growing importance of
interconnect

noise, crosstalk

reliability,
manufacturability

clock distribution

Macroscopic issues

time-to-market

design complexity
(millions of gates)

high levels of
abstractions

design for test

reuse and IP, portability

systems on a chip (SoC)

CKV

Scaling
Technology shrinks by 0.7 times every
generation
With every generation we can integrate 2x
more functionality
Cost of a function decreases by 2x
How to design chips with more and more
functions ??
Need for Efficient
Methodologies

Design

CKV

Design Abstraction
SYSTEM

MODULE
+
GATE

CIRCUIT

DEVICE
G
S
n+

D
n+

Next Class
Design Metrics

CKV

CKV

Thank You

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