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    Lec2.2 Timing Up

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    LoiLeVan
    This document discusses timing and clocking examples in high-speed digital systems. It addresses the challenges of distributing clock signals across multiple chips with low skew. It presents solutions like using a two-step process to first get the clock to each chip and then distribute it on-chip. It also discusses clock networks in FPGAs and timing analysis in ASIC design flows. Key timing issues addressed include cell delays, clock tree insertion delays, skew between clocks and signals, and timing constraints and reports.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Lec2.2 Timing Up

    Uploaded by

    LoiLeVan
    30 views20 pages
    This document discusses timing and clocking examples in high-speed digital systems. It addresses the challenges of distributing clock signals across multiple chips with low skew. It presents solutions like using a two-step process to first get the clock to each chip and then distribute it on-chip. It also discusses clock networks in FPGAs and timing analysis in ASIC design flows. Key timing issues addressed include cell delays, clock tree insertion delays, skew between clocks and signals, and timing constraints and reports.

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    Lec2.2 Timing Up

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    This document discusses timing and clocking examples in high-speed digital systems. It addresses the challenges of distributing clock signals across multiple chips with low skew. It presents solutions like using a two-step process to first get the clock to each chip and then distribute it on-chip. It also discusses clock networks in FPGAs and timing analysis in ASIC design flows. Key timing issues addressed include cell delays, clock tree insertion delays, skew between clocks and signals, and timing constraints and reports.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    30 views20 pages

    Lec2.2 Timing Up

    Uploaded by

    LoiLeVan
    This document discusses timing and clocking examples in high-speed digital systems. It addresses the challenges of distributing clock signals across multiple chips with low skew. It presents solutions like using a two-step process to first get the clock to each chip and then distribute it on-chip. It also discusses clock networks in FPGAs and timing analysis in ASIC design flows. Key timing issues addressed include cell delays, clock tree insertion delays, skew between clocks and signals, and timing constraints and reports.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 20

    EE7605 Signal Integrity in HighSpeed Digital Systems

    Lecture 2.2: Timing and


    Clocking Examples

    EE7605 Lecture 2.2

    Chip to Chip Timing

    Problem
    Some systems have large
    synchronous clock
    domains
    10s - 100s of chips
    103 - 105 clock loads
    per chip
    Need to distribute the
    clock to
    within 10% of tck
    200ps for a 500MHz
    clock
    Solution: two step process
    Get the clock to each
    chip with low skew
    Distribute the clock on
    chip with low skew

    EE7605 Lecture 2.2

    Off Chip Solutions

    EE7605 Lecture 2.2

    Spartan-3 FPGA Clock Network

    EE7605 Lecture 2.2

    Spartan-3 FPGA Clock Network

    EE7605 Lecture 2.2

    Timing in ASIC Design Flow


    front end

    EE7605 Lecture 2.2

    Timing Constraints

    EE7605 Lecture 2.2

    Model Source Latency

    EE7605 Lecture 2.2

    Pre/Post Layout Clock

    EE7605 Lecture 2.2

    Multiple Clock Domains

    Many large ASICs, and systems built with these ASICs, have several
    synchronous clock domains connected by asynchronous
    communication

    Clock domain 3

    Clock
    domain 1

    Clock
    domain 2
    Chip A

    Clock
    domain 6

    Asynch.
    channel

    Clock
    domain 5

    Chip C

    Clock
    domain 4

    Chip B

    10

    EE7605 Lecture 2.2

    Multiple Clock Domains

    5.5 input delay


    11

    EE7605 Lecture 2.2

    Clock Tree

    12

    EE7605 Lecture 2.2

    Timing Analysis
    Paths

    13

    Start point:
    Clk pin of FF
    Primary input
    Endpoint
    D pin of FF
    Primary output

    EE7605 Lecture 2.2

    Timing Analysis
    Cell Delay

    14

    EE7605 Lecture 2.2

    Timing Analysis
    Cell Delay

    15

    EE7605 Lecture 2.2

    Timing Analysis
    Report

    16

    EE7605 Lecture 2.2

    Timing Analysis
    Report

    17

    EE7605 Lecture 2.2

    Timing in ASIC Design Flow


    back end (Cadence based)

    18

    EE7605 Lecture 2.2

    Timing in ASIC Design Flow


    back end (Cadence based)

    19

    Clock Tree
    Heavy clock net
    loading
    Long clock insertion
    delay
    Clock skew
    Skew across clocks
    Clock to signal
    coupling effect
    Clock is power hungry
    Electromigration on
    clock net

    EE7605 Lecture 2.2

    Clock Tree

    20

    EE7605 Lecture 2.2

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