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Karaikudi Institute of Technology: Year/Dept: Ii/Cse Date: 07.08.2014 Time:09:20 A.M. - 11:00 A.M

This document contains an internal test for a Computer Architecture course taken by a student in their second year of a Computer Science program. The test has two parts worth 10 and 40 marks respectively and covers topics such as dynamic scheduling, branch prediction, pipelining, hazards, MIPS architecture, and single vs. multicycle implementation. It provides the student with questions to answer on these topics within the allotted time of 50 minutes.

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74 views2 pages

Karaikudi Institute of Technology: Year/Dept: Ii/Cse Date: 07.08.2014 Time:09:20 A.M. - 11:00 A.M

This document contains an internal test for a Computer Architecture course taken by a student in their second year of a Computer Science program. The test has two parts worth 10 and 40 marks respectively and covers topics such as dynamic scheduling, branch prediction, pipelining, hazards, MIPS architecture, and single vs. multicycle implementation. It provides the student with questions to answer on these topics within the allotted time of 50 minutes.

Uploaded by

rathiramsha7
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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KARAIKUDI INSTITUTE OF TECHNOLOGY

KIT AND KIM TECHNICAL CAMPUS


Keeranipatti, Thalakkavur, Karaikudi 630 307

INTERNAL TEST II AUG-2014


Year/Dept:
II/CSE

Reg.
No:

CS630
3

07.08.2014

Date:

COMPUTER ARCHITECTURE
Time:09:20 a.m. 11:00

50
Marks

a.m.
Answer ALL Questions
PART A 10 Marks

1. What is Dynamic Scheduling? Write its advantage


2. Draw the state diagram for 2-bit branch predictor
3. What is branch taken or not taken?
4. Define Pipelining? And write 5 stages of pipelining.
5. What is structural Hazard

PART B 40 Marks

6. What is Exception? Explain the types with example

7. (a) What is MIPS? Explain datapath in instruction and memory in


detail.
Or
(b) Explain Single cycle and multicycle implementation in detail.

1
6

8. a (i) What is hazard? Explain data hazards in detail


(ii) Write characteristics & register for MIPS
Or
b (i)What is Branch prediction? With neat diagram explain control
hazards in detail
Prepared by R.SusilKumar, AP/CSE

1
6
1
0
6
1
6

KARAIKUDI INSTITUTE OF TECHNOLOGY


KIT AND KIM TECHNICAL CAMPUS
Keeranipatti, Thalakkavur, Karaikudi 630 307

INTERNAL TEST II AUG-2014


Year/Dept:
II/CSE

Reg.
No:

CS630
3

07.08.2014

Date:

COMPUTER ARCHITECTURE
Time:09:20 a.m. 11:00

50
Marks

a.m.
Answer ALL Questions
PART A 10 Marks

1. What is Dynamic Scheduling? Write its advantage


2. Draw the state diagram for 2-bit branch predictor
3. What is branch taken or not taken?
4. Define Pipelining? And write 5 stages of pipelining.
5. What is structural Hazard

PART B 40 Marks

6. What is Exception? Explain the types with example

7. (a) What is MIPS? Explain datapath in instruction and memory in


detail.
Or
(b) Explain Single cycle and multicycle implementation in detail.

1
6

8. a (i) What is hazard? Explain data hazards in detail


(ii) Write characteristics & register for MIPS
Or
b (i)What is Branch prediction? With neat diagram explain control
hazards in detail
Prepared by R.SusilKumar, AP/CSE

1
6
1
0
6
1
6

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