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Design Viterbi Decoder: Embedded System

This document presents a design for a Viterbi decoder. It contains 4 sections: an introduction to channel encoders/decoders and convolutional codes, an overview of the Viterbi decoder including its structure and characteristics, details of the Viterbi algorithm and its hardware implementation including the branch metric unit, path metric unit, and traceback unit, and references. The project will design a Viterbi decoder with a constraint length of 2, 1 input bit, and 2 output bits to decode an 8-bit input signal.

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42 views14 pages

Design Viterbi Decoder: Embedded System

This document presents a design for a Viterbi decoder. It contains 4 sections: an introduction to channel encoders/decoders and convolutional codes, an overview of the Viterbi decoder including its structure and characteristics, details of the Viterbi algorithm and its hardware implementation including the branch metric unit, path metric unit, and traceback unit, and references. The project will design a Viterbi decoder with a constraint length of 2, 1 input bit, and 2 output bits to decode an 8-bit input signal.

Uploaded by

Phan Di Di
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Embedded system

Presentation

Design Viterbi Decoder


Lecturer:
PhD. Ngo Vu Duc
Students:
Vu Manh Cuong
Hoang Manh Cuong
Tran Anh Duc
Nguyen Quang Truong

Contents

Introduction

Overview of Viterbi Decoder

Viterbi Algorithm

References

1. Introduction
The important of channel encoder/decoder in communication
system

1. Introduction
Some kinds of encoder/decoder:
Linear block codes:
Hamming codes
Parity codes
Reed Solomon codes
BCH code
.
Convolutional codes
Viterbi codes

2. Overview of Viterbi Decoder


Is a type of convolutional code
Can be represented as a convolution calculation of
polynomial code generation and the input signal
Structure:

2. Overview of Viterbi Decoder


Some characteristic of
Viterbi Decoder:
Number of Flipflop: m
No. of input bits: k
No. of output bits : n
Code speed: R = k/n
Constraint length:
L = k(m-1)

3. Viterbi Algorithm
In this project, we will design
a Viterbi decoder with m = 2,
k = 1, n = 2, L = 2 and the
length of input signal is 8 bits
- Structure:

- State transition diagram of


the encoder

3. Viterbi Algorithm
Viterbi Algorithm: Maximum Likelihood
Trellis diagram:

3. Viterbi Algorithm
Hardware implementation:

3. Viterbi Algorithm
Hardware implementation:
- Branch metric unit BMU

3. Viterbi Algorithm
Hardware implementation:
- Path metric unit PMU
Accumulated metric of each state
is Da, Db, Dc and Dd
D1 = Da + Daa; D2 = Db + Dba
Da(new) = D1<D2?D1:D2
D3 = Dc + Dcb; D4 = Dd + Ddb
Db(new) = D3<D4?D3:D4
D5 = Da + Dac; D6 = Db + Dbc
Dc(new) = D5<D6?D5:D6
D7 = Dc + Dcd; D8 = Dd + Ddd
Dd(new) = D7<D8?D7:D8

Da

Db

Dc

Dd

3. Viterbi Algorithm
Hardware implementation:
- Path metric unit PMU
Input bits corresponding to the
states
Bita(new) = D1<D2?Bita+0:Bitb+0
Bitb(new) = D3<D4?Bitc+0:Bitd+0
Bitc(new) = D5<D6?Bita+1:Bitb+1
Bitd(new) = D7<D8?Bitc+1:Bitd+1

Da

Db

Dc

Dd

3. Viterbi Algorithm
Hardware implementation:
- Traceback unit TBU: restores an (almost) maximumlikelihood path from the decisions made by PMU (the
minium accumulated metric)

4. References
References:
L.Van de Meeberg, A Viterbi Decoder, October 1974
http://en.wikipedia.org/wiki/Viterbi_decoder
Huynh Minh Kha, Le Duy, Implement Viterbi Decoder on FPGA,
Ho Chi Minh City January 2011

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