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Testing of Vlsi Circuits: Answer All Questions Each Question Carries 25 Marks

This document contains exam questions for a testing of VLSI circuits course. The questions cover a range of topics related to testing digital and analog circuits at different stages of design and manufacturing. Specifically, the questions address: 1) Types of tests used at various stages of microprocessor chip manufacturing to control failure rates. 2) Definitions of fault models such as bridging faults, potentially-detectable stuck-at faults, hyperactive stuck-at faults, IDDQ faults, and transition faults. 3) Concepts of fault equivalence and dominance as well as an example circuit.

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533 views2 pages

Testing of Vlsi Circuits: Answer All Questions Each Question Carries 25 Marks

This document contains exam questions for a testing of VLSI circuits course. The questions cover a range of topics related to testing digital and analog circuits at different stages of design and manufacturing. Specifically, the questions address: 1) Types of tests used at various stages of microprocessor chip manufacturing to control failure rates. 2) Definitions of fault models such as bridging faults, potentially-detectable stuck-at faults, hyperactive stuck-at faults, IDDQ faults, and transition faults. 3) Concepts of fault equivalence and dominance as well as an example circuit.

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Anonymous gwdxvOcoq
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Reg. No.:................

Name: ...................
M.TECH DEGREE EXAMINATION, 2012
Second Semester
Branch: Electronics and Communication Engineering
Specialization: VLSI and Embedded Systems
MEC VE 206 TESTING OF VLSI CIRCUITS
(Regular-2011 Admissions)
Time: Three Hours
Maximum: 100 marks
Answer all questions
Each question carries 25 marks.
1.

a) You are making microprocessor chips, and need to have a very low product failure rate in
the field to control your warranty costs. Describe the various types of tests that you would use
on the microprocessor chips at their various stages of processing.
(10)
b) Define the following fault models using examples where possible:
(1) Bridging fault
(2) Potentially-detectable stuck-at fault
(3) Hyperactive stuck-at fault
(4)IDDQ fault
(5) Transition fault

(15)

Or
2.
a)

1. Explain fault equivalence and fault dominance.


2. Show that the two faults c s-a-0 and f s-a-1 are equivalent in the circuit of Figure
below

(7+8)
b) Write a note on test economics

(10)

3. a) Explain in detail PODEM

(15)

-1-

b) Explain why a concurrent fault simulator requires more memory than a deductive fault
simulator.
(10)

Or
4. a)
1. Explain what action an event-driven true-value simulator will take when it evaluates
a zero-delay gate.
2. Write a note on Event Driven simulation
(5+5)
b) Explain SCOAP controllability and obsevability.

5. a) Explain in detail scan design rules

(15)

(15)

b) If N= 15 patterns are produced by an LFSR, and 2 of those patterns detect a given fault,
say e stuck-at 0, what is the average test length T to detect e stuck-at-0?
(10)
Or
6.

(a) Describes the modes of operation of boundary scan architecture.

(13)

(b) Explain LFSR for memory testing and compare it with other memory test methods.
(12)
7.

a) Write notes on
1) Path delay test
2) Delay test methodologies
3) IDDQ TEST
(3*5)
(b) Discuss various analog testing methods
Or

8. (a) Compare digital testing methods and analog testing methods

(10)
(10)

(b) Write detailed notes on


1) ATPG
2) Analog testing difficulties

(7+8)

---------------------------------------------------2-

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