Scribd
Upload
475 views

5 Bit Multiplier

This document describes a 5-bit multiplier implemented in VHDL. It includes the VHDL code for the multiplier, as well as simulation, area, timing, and power reports. The code uses procedures like half adder, full adder, and multiplexers to build basic multiplier cells that are then combined to perform the full 5x5 bit multiplication, outputting a 10-bit result.

Uploaded by

innovatorinnovator
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
475 views

5 Bit Multiplier

This document describes a 5-bit multiplier implemented in VHDL. It includes the VHDL code for the multiplier, as well as simulation, area, timing, and power reports. The code uses procedures like half adder, full adder, and multiplexers to build basic multiplier cells that are then combined to perform the full 5x5 bit multiplication, outputting a 10-bit result.

Uploaded by

innovatorinnovator
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 10

5 BIT MULTIPLIER

BIRLA INSTITUE OF TECHNOLOGY AND SCIENCE, PILANI

CAD FOR IC DESIGN ASSIGNMENT 1


ON
5 BIT MULTIPLIER

Submitted by:
Devendra S. Bilaye
2013H123158P
M.E. Microelectronics

5 BIT MULTIPLIER

Contents
1.
2.
3.
4.
5.

VHDL code......3
Simulation results .......9
Area report9
Timing report......10
Power report...10

VHDL code

5 BIT MULTIPLIER
Code for package:
library IEEE;
library WORK;
use IEEE.STD_LOGIC_1164.all;

package mul_pack is
procedure HA ( variable s : out bit;
variable c : out bit;
variable a: in bit;
variable b: in bit);

procedure FA ( variable s : out bit;


variable c : out bit;
variable a: in bit;
variable b: in bit;
variable cin : in bit);

procedure cla2 (variable s1,s0,c2 : out bit;


variable a1,b1,a0,b0,c0 : in bit);
procedure cell1 (variable xi_out,yi_out,si_out,xj_out,yj_out,cout,sout : out bit;
variable sin,xj_in,yj_in,cin,xi_in,yi_in,si_in : in bit);
procedure mux41(variable d0,d1,d2,d3,s1,s0 : in

bit;

variable y: out bit);

procedure cell2(variable xi,yi,si,cj_n,cout,sout,xiyi : out bit;


variable sin,xj,yj,cin,cj : in bit);
end mul_pack;

5 BIT MULTIPLIER
------------------------------------------BODY
package body mul_pack is
procedure HA ( variable s : out bit;
variable c : out bit;
variable a: in bit;
variable b: in bit) is
begin
s := a xor b;
c := a and b;
end HA;

procedure FA ( variable s : out bit;


variable c : out bit;
variable a: in bit;
variable b: in bit;
variable cin : in bit) is
begin
s := a xor b xor cin;
c := (a and b) or (cin and b) or (a and cin);
end FA;

procedure cla2 (variable s1,s0,c2 : out bit;


variable a1,b1,a0,b0,c0 : in bit) is
variable g0,p0,g1,p1,c1 : bit;
begin

g0 := a0 and b0;

5 BIT MULTIPLIER
p0 := a0 xor b0;
--HA(p0,g0,a0,b0);
g1 := a1 and b1;
p1 := a1 xor b1;
--HA(p1,g1,a1,b1);
c1 := (c0 and p0) or (g0);
c2 := (c0 and p0 and p1) or (g0 and p1) or (g1);
s0 := p0 xor c0;
s1 := p1 xor c1;
end cla2;

procedure mux41(variable d0,d1,d2,d3,s1,s0 : in


variable y

bit;

: out bit) is

begin
y := (d0 and (not s1) and (not s0)) or (d1 and (not s1) and s0) or
(d2 and s1 and (not s0)) or (d3 and s1 and s0);
end mux41;

procedure cell1 (variable xi_out,yi_out,si_out,xj_out,yj_out,cout,sout : out bit;


variable sin,xj_in,yj_in,cin,xi_in,yi_in,si_in : in bit) is
variable fa_cin,tp : bit;
begin
xi_out := xi_in;
yi_out := yi_in;
si_out := si_in;
tp := '0';
xj_out := xj_in;

5 BIT MULTIPLIER
yj_out := yj_in;

mux41 (tp,xi_in,yi_in,si_in,xj_in,yj_in,fa_cin);
FA(sout,cout,sin,cin,fa_cin);
end cell1;

procedure cell2(variable xi,yi,si,cj_n,cout,sout,xiyi : out bit;


variable sin,xj,yj,cin,cj : in bit) is
variable xjyjcj,temp : bit;
begin
xi := xj;
yi := yj;
FA (si,cj_n,xj,yj,cj);
--FA (cj_n,si,xj,yj,cj);
temp := xj and yj;
xiyi := temp;
xjyjcj := temp and cj;
FA (sout,cout,sin,cin,xjyjcj);
end cell2;
end mul_pack;

Main multiplier VHDL code:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use WORK.mul_pack.all;

entity mul5_main is

5 BIT MULTIPLIER
port (x,y : in bit_vector (4 downto 0); p : out bit_vector (9 downto 0));
end mul5_main;

architecture Behavioral of mul5_main is


begin
process(x,y)
variable xi,yi,si : bit_vector (10 downto 1);----horzntl lines i/p to cell1
variable xj,yj,cout,sout : bit_vector (10 downto 1);-------o/p lines for cell1
variable cj_n,cout2,sout2,xiyi : bit_vector (5 downto 1);----o/p lines for cell2
variable cin : bit_vector (15 downto 1);------i/p lines for both cell1 n cell2
variable xv,yv : bit_vector (4 downto 0);

-----------for x,y i/ps

variable pv : bit_vector (9 downto 0);-------------for p o/p


variable xiw,yiw,siw,cjw,coutw : bit;
variable sin,cj : bit;
variable cla_cout1,cla_cout2,cla_cout3,cla_cin : bit;

begin
xv := x;
yv := y;
sin:='0';
cin(1) := '0'; cin(2) := '0'; cin(3) := '0'; cin(4) := '0'; cin(5) := '0';
cj := '0';
-----------------------row 1
cell2 (xi(1),yi(1),si(1),cj_n(1),cout2(1),sout2(1),pv(0),sin,xv(0),yv(0),cin(1),cj);
cell1 (xi(2),yi(2),si(2),xj(1),yj(1),cout(1),pv(1),sin,xv(1),yv(1),cin(2),xi(1),yi(1),si(1));
cell1 (xi(3),yi(3),si(3),xj(2),yj(2),cout(2),sout(2),sin,xv(2),yv(2),cin(3),xi(2),yi(2),si(2));
cell1 (xi(4),yi(4),si(4),xj(3),yj(3),cout(3),sout(3),sin,xv(3),yv(3),cin(4),xi(3),yi(3),si(3));

5 BIT MULTIPLIER
cell1 (xiw,yiw,siw,xj(4),yj(4),cout(4),sout(4),sin,xv(4),yv(4),cin(5),xi(4),yi(4),si(4));
-------------------------row 2
cell2 (xi(5),yi(5),si(5),cj_n(2),cout2(2),sout2(2),xiyi(2),sout(2),xj(1),yj(1),cout(1),cj_n(1));
cell1 (xi(6),yi(6),si(6),xj(5),yj(5),cout(5),sout(5),sout(3),xj(2),yj(2),cout(2),xi(5),yi(5),si(5));
cell1 (xi(7),yi(7),si(7),xj(6),yj(6),cout(6),sout(6),sout(4),xj(3),yj(3),cout(3),xi(6),yi(6),si(6));
cell1 (xiw,yiw,siw,xj(7),yj(7),cout(7),sout(7),sin,xj(4),yj(4),cout(4),xi(7),yi(7),si(7));
---------------------row 3
cell2 (xi(8),yi(8),si(8),cj_n(3),cout2(3),sout2(3),xiyi(3),sout(6),xj(5),yj(5),cout(5),cj_n(2));
cell1 (xi(9),yi(9),si(9),xj(8),yj(8),cout(8),sout(8),sout(7),xj(6),yj(6),cout(6),xi(8),yi(8),si(8));
cell1 (xiw,yiw,siw,xj(9),yj(9),cout(9),sout(9),sin,xj(7),yj(7),cout(7),xi(9),yi(9),si(9));
-----------------------row 4
cell2 (xi(10),yi(10),si(10),cj_n(4),cout2(4),sout2(4),xiyi(4),sout(9),xj(8),yj(8),cout(8),cj_n(3));
cell1 (xiw,yiw,siw,xj(10),yj(10),cout(10),sout(10),sin,xj(9),yj(9),cout(9),xi(10),yi(10),si(10));
----------------------------row 5
cell2 (xiw,yiw,siw,cjw,coutw,sout2(5),xiyi(5),sin,xj(10),yj(10),cout(10),cj_n(4));
cla_cin := '0';
cla2 (pv(3),pv(2),cla_cout1,sout(5),cout2(2),sout2(2),xiyi(2),cla_cin);
cla2 (pv(5),pv(4),cla_cout2,sout(8),cout2(3),sout2(3),xiyi(3),cla_cout1);
cla2 (pv(7),pv(6),cla_cout3,sout(10),cout2(4),sout2(4),xiyi(4),cla_cout2);
FA (pv(8),pv(9),sout2(5),xiyi(5),cla_cout3);
p <= pv;
end process;
end Behavioral;

Simulation Result:

5 BIT MULTIPLIER

Area Report:

Timing Report:

5 BIT MULTIPLIER

Power Report:

10

You might also like