ADC Guide, Part 1: The Ideal ADC: Sachin Gupta and Akshay Phatak, Cypress Semiconductor Corp
ADC Guide, Part 1: The Ideal ADC: Sachin Gupta and Akshay Phatak, Cypress Semiconductor Corp
As it can be seen in Figure 2, the response of an ideal ADC is perfectly linear. This means that
none of the digital codes are missing in the output of the ADC and every successive code occurs at the
output exactly after a definite increment in the input voltage. In this diagram, the entire input range of
the ADC is divided into 8 equal parts and each of these parts corresponds to a digital output code.
This span of analog voltage after which an ADC changes its output is known as one LSB for the
ADC based on the fact that this much change in ADC input will change the output of the ADC by one bit.
The LSB of an ADC is also known as the Step Size of the ADC. The terms are often used interchangeably.
Step size
Step size is the minimum change in input voltage which can be resolved by the ADC. The
concept of step size is closely associated with the resolution of ADC.
Resolution
The resolution of an ADC refers to the number of bits in the digital output code of the ADC.
Thus, for an ADC with a response as shown in Figure 2, the resolution will be 3 bits. The relation
between step size, resolution, and input range can be given by:
is the step size of the ADC. Figure 3 shows the variation of quantization noise throughout the
As stated previously, the only noise source for an ideal ADC is quantization noise. Thus, to find
the SNR of an ideal ADC, we replace signal amplitude by the root mean square (RMS) value of a full scale
sine wave signal and noise amplitude by the RMS value of quantization noise throughout the input
range. Considering these definitions, the SNR of an ideal ADC is:
to
as it is repetitive,
Replacing these values in Equation (2), we get a SNR for an ideal ADC as follows:
As seen in Equation (3), the SNR of an ideal ADC depends solely on the resolution of the ADC. As
we increase the resolution, we keep adding quantization levels exponentially. This reduces the step size
and increases the possibility of finding a digital code nearer to any given analog input voltage within the
input range of ADC. This results in a reduction of quantization noise, as well as a corresponding increase
in the SNR.
Next time, we will look more into the practical aspects of an ADC. The second part of this series
will cover sample rate and the effects of sampling rate on the output of an ADC.