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Sequential ATPG

This document discusses methods for automatic test pattern generation (ATPG) for sequential circuits. It describes how sequential circuits can be modeled as combinational circuits by expanding the circuit across multiple timeframes. ATPG for sequential circuits involves initializing the circuit to a known state, activating the fault, and propagating the fault effect to an output. Test generation involves unrolling the sequential circuit into a larger combinational one using timeframe expansion, then applying ATPG algorithms to determine test vectors across the different timeframes.
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0% found this document useful (0 votes)
148 views9 pages

Sequential ATPG

This document discusses methods for automatic test pattern generation (ATPG) for sequential circuits. It describes how sequential circuits can be modeled as combinational circuits by expanding the circuit across multiple timeframes. ATPG for sequential circuits involves initializing the circuit to a known state, activating the fault, and propagating the fault effect to an output. Test generation involves unrolling the sequential circuit into a larger combinational one using timeframe expansion, then applying ATPG algorithms to determine test vectors across the different timeframes.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Combinational ATPG

VLSI Design Verification


and Testing

Time-frame expansion methods


Simulation-based
Simulation
based methods

Methods of sequential circuit ATPG

Initializes the circuit to a known state


Activates the fault, and
Propagates the fault effect to a primary output

Test for a fault in a sequential circuit is a sequence of vectors,


which

A sequential circuit has memory in addition to combinational


logic.

Sequential ATPG

Muths nine-valued logic

Time-frame expansion methods


Simulation-based
Simulation
based methods

Methods of sequential circuit ATPG

Initializes the circuit to a known state


Activates the fault, and
Propagates the fault effect to a primary output

Test for a fault in a sequential circuit is a sequence of vectors,


which

A sequential circuit has memory in addition to combinational


logic.

Time-frame expansion

CLOCK

Memory block

Combinatory block

Pseudo
POs

POs

This sequential circuit can be unrolled into a larger


combinational circuit; this process is called time-frame
expansion

Pseudo
PIs

PIs

Implementation (1)

s- k

input, binary
state vector, nine-valued logic
g

Pseudo
memory

s- k+1
C

timeframe -1

s- 1

v- 1

s0
M

s0

timeframe 0

Fault-detection
timeframe
v0

Temporal copies of the combinational part are linked with pseudocombinational memory elements
Each temporal copy belongs to a unique timeframe

vk
sk

timeframe -k

v- k

Implementation (2)

s- k

Pseudo
memory

s- k+1
M

timeframe -1

s- 1

v- 1

s0
M

s0

timeframe 0

v0

3. apply 2 until reaching timeframe -k, where a given initial


state is reached

2. use ATPG justification part to justify across timeframe -1

1. use ATPG algorithms (PODEM/FAN) to determine the test


vector of the timeframe 0 (the final one)

timeframe -k

v- k

Implementation (3)

J. P. Roth, Diagnosis of Automata Failures: A Calculus and a Method,


IBM Journal, pp. 278-291, July 1966
T. Kirkland,, M. R. Mercier,, Algorithms
g
for Automatic Test Pattern
Generation, IEEE Design and Test of Computers, pp. 43-55, June 1988
R.H. Klenke, R.D. Williams, J.H. Aylor, Parallel-processing techniques for
automatic test pattern generation, Computer, Vol. 25, No. 1, pp. 71-84,
1992
SP. Goel, An Implicit Enumeration Algorithm to Generate Tests for
Combinational Logic Circuits, IEEE T. Computers, Vol. C30, pp. 215-222,
1981

Additional readings and references

M. L. Bushnel and W. D. Agrawal, Essential of Electronic Testing for


Digital, Memory, and Mixed Signal VLSI Circuits, Springer, 2005
L.-T. Wang,
g, C.-W. Wu,, X. Wen,, Edts.,, VLSI Test Principles
p
and
Architecture, Morgan Kaufmann, 2006

References

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