//128 bit carry select adder//

module csla128bit_modified(sum,
carry,
a,
b,
cin);
input [127:0] a,
b;
input cin;
output [127:0] sum;
output carry;
//wire declaration for mux selection lines
wire wmc1,
wmc2,
wmc3,
wmc4,
wmc5,
wmc6,

wmc7,
wmc8,
wmc9,
wmc10,
wmc11,
wmc12,
wmc13;
//Internal Wire Declarartion for Sum data Connections
wire [2:0] ws1;
wire [3:0] ws2;
wire [4:0] ws3;
wire [5:0] ws4;
wire [7:0] ws5;
wire [8:0] ws6;
wire [9:0] ws7;
wire [10:0] ws8;
wire [11:0] ws9;
wire [12:0] ws10;
wire [13:0] ws11;

wire [14:0] ws12;

wire [15:0] ws13;

// Wire Declaration for BEC interconection

wire [3:0] we1;
wire [4:0] we2;
wire [5:0] we3;
wire [6:0] we4;
wire [8:0] we5;
wire [9:0] we6;
wire [10:0] we7;
wire [11:0] we8;
wire [12:0] we9;
wire [13:0] we10;
wire [14:0] we11;
wire [15:0] we12;
wire [16:0] we13;

rca2bit
u1(.sum(sum[1:0]),.carry(wmc1),.a(a[1:0]),.b(b[1:0]),.cin(
cin));
rca3bit
u21(.sum(ws1),.carry(wc1),.a(a[4:2]),.b(b[4:2]),.cin(1'b0))
;
bec4bit u22(.x(we1),.b({wc1,ws1}));
mux8_4
u23(.out(sum[4:2]),.cout(wmc2),.cin(wmc1),.s0(ws1),.s1(
we1[2:0]),.c0(wc1),.c1(we1[3]));
rca4bit
u31(.sum(ws2),.carry(wc2),.a(a[8:5]),.b(b[8:5]),.cin(1'b0))
;
bec5bit u32(.x(we2),.b({wc2,ws2}));
mux10_5
u33(.out(sum[8:5]),.cout(wmc3),.cin(wmc2),.s0(ws2),.s1(
we2[3:0]),.c0(wc2),.c1(we2[4]));
rca5bit
u41(.sum(ws3),.carry(wc3),.a(a[13:9]),.b(b[13:9]),.cin(1'b
0));

bec6bit u42(.x(we3),.b({wc3,ws3}));
mux12_6
u43(.out(sum[13:9]),.cout(wmc4),.cin(wmc3),.s0(ws3),.s1
(we3[4:0]),.c0(wc3),.c1(we3[5]));
rca6bit
u51(.sum(ws4),.carry(wc4),.a(a[19:14]),.b(b[19:14]),.cin(
1'b0));
bec7bit u52(.x(we4),.b({wc4,ws4}));
mux14_7
u53(.out(sum[19:14]),.cout(wmc5),.cin(wmc4),.s0(ws4),.s
1(we4[5:0]),.c0(wc4),.c1(we4[6]));
rca8bit
u61(.sum(ws5),.carry(wc5),.a(a[27:20]),.b(b[27:20]),.cin(
1'b0));
bec9bit u62(.x(we5),.b({wc5,ws5}));
mux18_9
u63(.out(sum[27:20]),.cout(wmc6),.cin(wmc5),.s0(ws5),.s
1(we5[7:0]),.c0(wc5),.c1(we5[8]));

rca9bit
u71(.sum(ws6),.carry(wc6),.a(a[36:28]),.b(b[36:28]),.cin(
1'b0));

bec10bit u72(.x(we6),.b({wc6,ws6}));
mux20_10
u73(.out(sum[36:28]),.cout(wmc7),.cin(wmc6),.s0(ws6),.s
1(we6[8:0]),.c0(wc6),.c1(we6[9]));
rca10bit
u81(.sum(ws7),.carry(wc7),.a(a[46:37]),.b(b[46:37]),.cin(
1'b0));
bec11bit u82(.x(we7),.b({wc7,ws7}));
mux22_11
u83(.out(sum[46:37]),.cout(wmc8),.cin(wmc7),.s0(ws7),.s
1(we7[9:0]),.c0(wc7),.c1(we7[10]));
rca11bit
u91(.sum(ws8),.carry(wc8),.a(a[57:47]),.b(b[57:47]),.cin(
1'b0));
bec12bit u92(.x(we8),.b({wc8,ws8}));
mux24_12
u93(.out(sum[57:47]),.cout(wmc9),.cin(wmc8),.s0(ws8),.s
1(we8[10:0]),.c0(wc8),.c1(we8[11]));
rca12bit
ua1(.sum(ws9),.carry(wc9),.a(a[69:58]),.b(b[69:58]),.cin(1
'b0));
bec13bit ua2(.x(we9),.b({wc9,ws9}));

mux26_13
ua3(.out(sum[69:58]),.cout(wmc10),.cin(wmc9),.s0(ws9),.
s1(we9[11:0]),.c0(wc9),.c1(we9[12]));
rca13bit
ub1(.sum(ws10),.carry(wc10),.a(a[82:70]),.b(b[82:70]),.ci
n(1'b0));
bec14bit ub2(.x(we10),.b({wc10,ws10}));
mux28_14
ub3(.out(sum[82:70]),.cout(wmc11),.cin(wmc10),.s0(ws1
0),.s1(we10[12:0]),.c0(wc10),.c1(we10[13]));
rca14bit
uc1(.sum(ws11),.carry(wc11),.a(a[96:83]),.b(b[96:83]),.ci
n(1'b0));
bec15bit uc2(.x(we11),.b({wc11,ws11}));
mux30_15
uc3(.out(sum[96:83]),.cout(wmc12),.cin(wmc11),.s0(ws11
),.s1(we11[13:0]),.c0(wc11),.c1(we11[14]));
rca15bit
ud1(.sum(ws12),.carry(wc12),.a(a[111:97]),.b(b[111:97]),
.cin(1'b0));
bec16bit ud2(.x(we12),.b({wc12,ws12}));

mux32_16
ud3(.out(sum[111:97]),.cout(wmc13),.cin(wmc12),.s0(ws
12),.s1(we12[14:0]),.c0(wc12),.c1(we12[15]));
rca16bit
ue1(.sum(ws13),.carry(wc13),.a(a[127:112]),.b(b[127:112
]),.cin(1'b0));
bec17bit ue2(.x(we13),.b({wc13,ws13}));
mux34_17
ue3(.out(sum[127:112]),.cout(carry),.cin(wmc13),.s0(ws1
3),.s1(we13[15:0]),.c0(wc13),.c1(we13[16]));
endmodule

///////

//////

/////

//////

//////

Ripple Carry Designs

/////////
//////////////

////////////
//////////

//rca 2bit
module rca2bit(sum,carry,a,b,cin);

///////

input[1:0] a,b;
input cin;
output [1:0] sum;
output carry;
wire w1;
fa u1(.sum(sum[0]),.carry(w1),.a(a[0]),.b(b[0]),.cin(cin));
fa
u2(.sum(sum[1]),.carry(carry),.a(a[1]),.b(b[1]),.cin(w1));
endmodule

//rca 3bit
module rca3bit(sum,carry,a,b,cin);
input[2:0] a,b;
input cin;
output [2:0] sum;
output carry;
wire w1,w2;
fa u1(.sum(sum[0]),.carry(w1),.a(a[0]),.b(b[0]),.cin(cin));
fa u2(.sum(sum[1]),.carry(w2),.a(a[1]),.b(b[1]),.cin(w1));
fa
u3(.sum(sum[2]),.carry(carry),.a(a[2]),.b(b[2]),.cin(w2));

endmodule

//RCA 4bit
module rca4bit(sum,carry,a,b,cin);
input[3:0] a,b;
input cin;
output [3:0] sum;
output carry;
wire w1,w2,w3;
fa u1(.sum(sum[0]),.carry(w1),.a(a[0]),.b(b[0]),.cin(cin));
fa u2(.sum(sum[1]),.carry(w2),.a(a[1]),.b(b[1]),.cin(w1));
fa u3(.sum(sum[2]),.carry(w3),.a(a[2]),.b(b[2]),.cin(w2));
fa
u4(.sum(sum[3]),.carry(carry),.a(a[3]),.b(b[3]),.cin(w3));
endmodule

//rca5bit
module rca5bit(sum,carry,a,b,cin);
input[4:0] a,b;
input cin;
output [4:0] sum;

output carry;
wire w1,w2,w3,w4;
fa u1(.sum(sum[0]),.carry(w1),.a(a[0]),.b(b[0]),.cin(cin));
fa u2(.sum(sum[1]),.carry(w2),.a(a[1]),.b(b[1]),.cin(w1));
fa u3(.sum(sum[2]),.carry(w3),.a(a[2]),.b(b[2]),.cin(w2));
fa u4(.sum(sum[3]),.carry(w4),.a(a[3]),.b(b[3]),.cin(w3));
fa
u5(.sum(sum[4]),.carry(carry),.a(a[4]),.b(b[4]),.cin(w4));
endmodule

//rca6bit
module rca6bit(sum,carry,a,b,cin);
input[5:0] a,b;
input cin;
output [5:0] sum;
output carry;
wire w1,w2,w3,w4,w5;
fa u1(.sum(sum[0]),.carry(w1),.a(a[0]),.b(b[0]),.cin(cin));
fa u2(.sum(sum[1]),.carry(w2),.a(a[1]),.b(b[1]),.cin(w1));
fa u3(.sum(sum[2]),.carry(w3),.a(a[2]),.b(b[2]),.cin(w2));
fa u4(.sum(sum[3]),.carry(w4),.a(a[3]),.b(b[3]),.cin(w3));

fa u5(.sum(sum[4]),.carry(w5),.a(a[4]),.b(b[4]),.cin(w4));
fa
u6(.sum(sum[5]),.carry(carry),.a(a[5]),.b(b[5]),.cin(w5));
endmodule

//rca8bit
module rca8bit(sum,carry,a,b,cin);
input[7:0] a,b;
input cin;
output [7:0] sum;
output carry;
wire w1,w2,w3,w4,w5,w6,w7;
fa u1(.sum(sum[0]),.carry(w1),.a(a[0]),.b(b[0]),.cin(cin));
fa u2(.sum(sum[1]),.carry(w2),.a(a[1]),.b(b[1]),.cin(w1));
fa u3(.sum(sum[2]),.carry(w3),.a(a[2]),.b(b[2]),.cin(w2));
fa u4(.sum(sum[3]),.carry(w4),.a(a[3]),.b(b[3]),.cin(w3));
fa u5(.sum(sum[4]),.carry(w5),.a(a[4]),.b(b[4]),.cin(w4));
fa u6(.sum(sum[5]),.carry(w6),.a(a[5]),.b(b[5]),.cin(w5));
fa u7(.sum(sum[6]),.carry(w7),.a(a[6]),.b(b[6]),.cin(w6));
fa
u8(.sum(sum[7]),.carry(carry),.a(a[7]),.b(b[7]),.cin(w7));

endmodule

//rca9bit
module rca9bit(sum,carry,a,b,cin);
input[8:0] a,b;
input cin;
output [8:0] sum;
output carry;
wire w1,w2,w3,w4,w5,w6,w7,w8;
fa u1(.sum(sum[0]),.carry(w1),.a(a[0]),.b(b[0]),.cin(cin));
fa u2(.sum(sum[1]),.carry(w2),.a(a[1]),.b(b[1]),.cin(w1));
fa u3(.sum(sum[2]),.carry(w3),.a(a[2]),.b(b[2]),.cin(w2));
fa u4(.sum(sum[3]),.carry(w4),.a(a[3]),.b(b[3]),.cin(w3));
fa u5(.sum(sum[4]),.carry(w5),.a(a[4]),.b(b[4]),.cin(w4));
fa u6(.sum(sum[5]),.carry(w6),.a(a[5]),.b(b[5]),.cin(w5));
fa u7(.sum(sum[6]),.carry(w7),.a(a[6]),.b(b[6]),.cin(w6));
fa u8(.sum(sum[7]),.carry(w8),.a(a[7]),.b(b[7]),.cin(w7));
fa
u9(.sum(sum[8]),.carry(carry),.a(a[8]),.b(b[8]),.cin(w8));
endmodule

//rca10bit
module rca10bit(sum,carry,a,b,cin);
input[9:0] a,b;
input cin;
output [9:0] sum;
output carry;
wire w1,w2,w3,w4,w5,w6,w7,w8,w9;
fa u1(.sum(sum[0]),.carry(w1),.a(a[0]),.b(b[0]),.cin(cin));
fa u2(.sum(sum[1]),.carry(w2),.a(a[1]),.b(b[1]),.cin(w1));
fa u3(.sum(sum[2]),.carry(w3),.a(a[2]),.b(b[2]),.cin(w2));
fa u4(.sum(sum[3]),.carry(w4),.a(a[3]),.b(b[3]),.cin(w3));
fa u5(.sum(sum[4]),.carry(w5),.a(a[4]),.b(b[4]),.cin(w4));
fa u6(.sum(sum[5]),.carry(w6),.a(a[5]),.b(b[5]),.cin(w5));
fa u7(.sum(sum[6]),.carry(w7),.a(a[6]),.b(b[6]),.cin(w6));
fa u8(.sum(sum[7]),.carry(w8),.a(a[7]),.b(b[7]),.cin(w7));
fa u9(.sum(sum[8]),.carry(w9),.a(a[8]),.b(b[8]),.cin(w8));
fa
u10(.sum(sum[9]),.carry(carry),.a(a[9]),.b(b[9]),.cin(w9));
endmodule

//rca11bit
module rca11bit(sum,carry,a,b,cin);
input[10:0] a,b;
input cin;
output [10:0] sum;
output carry;
wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10;
fa u1(.sum(sum[0]),.carry(w1),.a(a[0]),.b(b[0]),.cin(cin));
fa u2(.sum(sum[1]),.carry(w2),.a(a[1]),.b(b[1]),.cin(w1));
fa u3(.sum(sum[2]),.carry(w3),.a(a[2]),.b(b[2]),.cin(w2));
fa u4(.sum(sum[3]),.carry(w4),.a(a[3]),.b(b[3]),.cin(w3));
fa u5(.sum(sum[4]),.carry(w5),.a(a[4]),.b(b[4]),.cin(w4));
fa u6(.sum(sum[5]),.carry(w6),.a(a[5]),.b(b[5]),.cin(w5));
fa u7(.sum(sum[6]),.carry(w7),.a(a[6]),.b(b[6]),.cin(w6));
fa u8(.sum(sum[7]),.carry(w8),.a(a[7]),.b(b[7]),.cin(w7));
fa u9(.sum(sum[8]),.carry(w9),.a(a[8]),.b(b[8]),.cin(w8));
fa
u10(.sum(sum[9]),.carry(w10),.a(a[9]),.b(b[9]),.cin(w9));

fa
u11(.sum(sum[10]),.carry(carry),.a(a[10]),.b(b[10]),.cin(w
10));
endmodule

//rca12bit
module rca12bit(sum,carry,a,b,cin);
input[11:0] a,b;
input cin;
output [11:0] sum;
output carry;
wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11;
fa u1(.sum(sum[0]),.carry(w1),.a(a[0]),.b(b[0]),.cin(cin));
fa u2(.sum(sum[1]),.carry(w2),.a(a[1]),.b(b[1]),.cin(w1));
fa u3(.sum(sum[2]),.carry(w3),.a(a[2]),.b(b[2]),.cin(w2));
fa u4(.sum(sum[3]),.carry(w4),.a(a[3]),.b(b[3]),.cin(w3));
fa u5(.sum(sum[4]),.carry(w5),.a(a[4]),.b(b[4]),.cin(w4));
fa u6(.sum(sum[5]),.carry(w6),.a(a[5]),.b(b[5]),.cin(w5));
fa u7(.sum(sum[6]),.carry(w7),.a(a[6]),.b(b[6]),.cin(w6));
fa u8(.sum(sum[7]),.carry(w8),.a(a[7]),.b(b[7]),.cin(w7));
fa u9(.sum(sum[8]),.carry(w9),.a(a[8]),.b(b[8]),.cin(w8));

fa
u10(.sum(sum[9]),.carry(w10),.a(a[9]),.b(b[9]),.cin(w9));
fa
u11(.sum(sum[10]),.carry(w11),.a(a[10]),.b(b[10]),.cin(w1
0));
fa
u12(.sum(sum[11]),.carry(carry),.a(a[11]),.b(b[11]),.cin(w
11));
endmodule

//rca13bit
module rca13bit(sum,carry,a,b,cin);
input[12:0] a,b;
input cin;
output [12:0] sum;
output carry;
wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12;
fa u1(.sum(sum[0]),.carry(w1),.a(a[0]),.b(b[0]),.cin(cin));
fa u2(.sum(sum[1]),.carry(w2),.a(a[1]),.b(b[1]),.cin(w1));
fa u3(.sum(sum[2]),.carry(w3),.a(a[2]),.b(b[2]),.cin(w2));
fa u4(.sum(sum[3]),.carry(w4),.a(a[3]),.b(b[3]),.cin(w3));
fa u5(.sum(sum[4]),.carry(w5),.a(a[4]),.b(b[4]),.cin(w4));

fa u6(.sum(sum[5]),.carry(w6),.a(a[5]),.b(b[5]),.cin(w5));
fa u7(.sum(sum[6]),.carry(w7),.a(a[6]),.b(b[6]),.cin(w6));
fa u8(.sum(sum[7]),.carry(w8),.a(a[7]),.b(b[7]),.cin(w7));
fa u9(.sum(sum[8]),.carry(w9),.a(a[8]),.b(b[8]),.cin(w8));
fa
u10(.sum(sum[9]),.carry(w10),.a(a[9]),.b(b[9]),.cin(w9));
fa
u11(.sum(sum[10]),.carry(w11),.a(a[10]),.b(b[10]),.cin(w1
0));
fa
u12(.sum(sum[11]),.carry(w12),.a(a[11]),.b(b[11]),.cin(w1
1));
fa
u13(.sum(sum[12]),.carry(carry),.a(a[12]),.b(b[12]),.cin(w
12));
endmodule

//rca14bit
module rca14bit(sum,carry,a,b,cin);
input[13:0] a,b;
input cin;
output [13:0] sum;
output carry;

wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13;
fa u1(.sum(sum[0]),.carry(w1),.a(a[0]),.b(b[0]),.cin(cin));
fa u2(.sum(sum[1]),.carry(w2),.a(a[1]),.b(b[1]),.cin(w1));
fa u3(.sum(sum[2]),.carry(w3),.a(a[2]),.b(b[2]),.cin(w2));
fa u4(.sum(sum[3]),.carry(w4),.a(a[3]),.b(b[3]),.cin(w3));
fa u5(.sum(sum[4]),.carry(w5),.a(a[4]),.b(b[4]),.cin(w4));
fa u6(.sum(sum[5]),.carry(w6),.a(a[5]),.b(b[5]),.cin(w5));
fa u7(.sum(sum[6]),.carry(w7),.a(a[6]),.b(b[6]),.cin(w6));
fa u8(.sum(sum[7]),.carry(w8),.a(a[7]),.b(b[7]),.cin(w7));
fa u9(.sum(sum[8]),.carry(w9),.a(a[8]),.b(b[8]),.cin(w8));
fa
u10(.sum(sum[9]),.carry(w10),.a(a[9]),.b(b[9]),.cin(w9));
fa
u11(.sum(sum[10]),.carry(w11),.a(a[10]),.b(b[10]),.cin(w1
0));
fa
u12(.sum(sum[11]),.carry(w12),.a(a[11]),.b(b[11]),.cin(w1
1));
fa
u13(.sum(sum[12]),.carry(w13),.a(a[12]),.b(b[12]),.cin(w1
2));

fa
u14(.sum(sum[13]),.carry(carry),.a(a[13]),.b(b[13]),.cin(w
13));
endmodule

//rca15bit
module rca15bit(sum,carry,a,b,cin);
input[14:0] a,b;
input cin;
output [14:0] sum;
output carry;
wire
w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14;
fa u1(.sum(sum[0]),.carry(w1),.a(a[0]),.b(b[0]),.cin(cin));
fa u2(.sum(sum[1]),.carry(w2),.a(a[1]),.b(b[1]),.cin(w1));
fa u3(.sum(sum[2]),.carry(w3),.a(a[2]),.b(b[2]),.cin(w2));
fa u4(.sum(sum[3]),.carry(w4),.a(a[3]),.b(b[3]),.cin(w3));
fa u5(.sum(sum[4]),.carry(w5),.a(a[4]),.b(b[4]),.cin(w4));
fa u6(.sum(sum[5]),.carry(w6),.a(a[5]),.b(b[5]),.cin(w5));
fa u7(.sum(sum[6]),.carry(w7),.a(a[6]),.b(b[6]),.cin(w6));
fa u8(.sum(sum[7]),.carry(w8),.a(a[7]),.b(b[7]),.cin(w7));

fa u9(.sum(sum[8]),.carry(w9),.a(a[8]),.b(b[8]),.cin(w8));
fa
u10(.sum(sum[9]),.carry(w10),.a(a[9]),.b(b[9]),.cin(w9));
fa
u11(.sum(sum[10]),.carry(w11),.a(a[10]),.b(b[10]),.cin(w1
0));
fa
u12(.sum(sum[11]),.carry(w12),.a(a[11]),.b(b[11]),.cin(w1
1));
fa
u13(.sum(sum[12]),.carry(w13),.a(a[12]),.b(b[12]),.cin(w1
2));
fa
u14(.sum(sum[13]),.carry(w14),.a(a[13]),.b(b[13]),.cin(w1
3));
fa
u15(.sum(sum[14]),.carry(carry),.a(a[14]),.b(b[14]),.cin(w
14));
endmodule

//rca16bit
module rca16bit(sum,carry,a,b,cin);
input[15:0] a,b;
input cin;

output [15:0] sum;

output carry;
wire
w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w
15;
fa u1(.sum(sum[0]),.carry(w1),.a(a[0]),.b(b[0]),.cin(cin));
fa u2(.sum(sum[1]),.carry(w2),.a(a[1]),.b(b[1]),.cin(w1));
fa u3(.sum(sum[2]),.carry(w3),.a(a[2]),.b(b[2]),.cin(w2));
fa u4(.sum(sum[3]),.carry(w4),.a(a[3]),.b(b[3]),.cin(w3));
fa u5(.sum(sum[4]),.carry(w5),.a(a[4]),.b(b[4]),.cin(w4));
fa u6(.sum(sum[5]),.carry(w6),.a(a[5]),.b(b[5]),.cin(w5));
fa u7(.sum(sum[6]),.carry(w7),.a(a[6]),.b(b[6]),.cin(w6));
fa u8(.sum(sum[7]),.carry(w8),.a(a[7]),.b(b[7]),.cin(w7));
fa u9(.sum(sum[8]),.carry(w9),.a(a[8]),.b(b[8]),.cin(w8));
fa
u10(.sum(sum[9]),.carry(w10),.a(a[9]),.b(b[9]),.cin(w9));
fa
u11(.sum(sum[10]),.carry(w11),.a(a[10]),.b(b[10]),.cin(w1
0));
fa
u12(.sum(sum[11]),.carry(w12),.a(a[11]),.b(b[11]),.cin(w1
1));

fa
u13(.sum(sum[12]),.carry(w13),.a(a[12]),.b(b[12]),.cin(w1
2));
fa
u14(.sum(sum[13]),.carry(w14),.a(a[13]),.b(b[13]),.cin(w1
3));
fa
u15(.sum(sum[14]),.carry(w15),.a(a[14]),.b(b[14]),.cin(w1
4));
fa
u16(.sum(sum[15]),.carry(carry),.a(a[15]),.b(b[15]),.cin(w
15));
endmodule

//3 bit BEC

module bec3bit(x,b);
input [2:0] b;
output [2:0] x;
assign x[0] = ~(b[0]);
assign x[1] = (b[0] ^ b[1]);

assign x[2] = ((b[0]&&b[1])^b[2]);

endmodule

//4 bit BEC

module bec4bit(x,b);
input [3:0] b;
output [3:0] x;
assign x[0] = ~(b[0]);
assign x[1] = (b[0] ^ b[1]);
assign x[2] = ((b[0]&&b[1])^b[2]);
assign x[3] = ((b[0]&&b[1]&&b[2])^b[3]);
endmodule

//5 bit BEC

module bec5bit(x,b);
input [4:0] b;
output [4:0] x;
assign x[0] = ~(b[0]);
assign x[1] = (b[0] ^ b[1]);
assign x[2] = ((b[0]&&b[1])^b[2]);
assign x[3] = ((b[0]&&b[1]&&b[2])^b[3]);

assign x[4] = ((b[0]&&b[1]&&b[2]&&b[3])^b[4]);

endmodule

//6 bit BEC

module bec6bit(x,b);
input [5:0] b;
output [5:0] x;
assign x[0] = ~(b[0]);
assign x[1] = (b[0] ^ b[1]);
assign x[2] = ((b[0]&&b[1])^b[2]);
assign x[3] = ((b[0]&&b[1]&&b[2])^b[3]);
assign x[4] = ((b[0]&&b[1]&&b[2]&&b[3])^b[4]);
assign x[5] = ((b[0]&&b[1]&&b[2]&&b[3]&&b[4])^b[5]);
endmodule

//7 bit BEC

module bec7bit(x,b);
input [6:0] b;
output [6:0] x;
assign x[0] = ~b[0];
assign x[1] = (b[0] ^ b[1]);

assign x[2] = ((b[0]&&b[1])^b[2]);

assign x[3] = ((b[0]&&b[1]&&b[2])^b[3]);
assign x[4] = ((b[0]&&b[1]&&b[2]&&b[3])^b[4]);
assign x[5] = ((b[0]&&b[1]&&b[2]&&b[3]&&b[4])^b[5]);
assign x[6] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5])^b[6]);
endmodule

//9 bit BEC

module bec9bit(x,b);
input [8:0] b;
output [8:0] x;
assign x[0] = ~b[0];
assign x[1] = (b[0] ^ b[1]);
assign x[2] = ((b[0]&&b[1])^b[2]);
assign x[3] = ((b[0]&&b[1]&&b[2])^b[3]);
assign x[4] = ((b[0]&&b[1]&&b[2]&&b[3])^b[4]);
assign x[5] = ((b[0]&&b[1]&&b[2]&&b[3]&&b[4])^b[5]);

assign x[6] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5])^b[6]);
assign x[7] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6])^b[7]);
assign x[8] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7])
^b[8]);
endmodule

//10 bit BEC

module bec10bit(x,b);
input [9:0] b;
output [9:0] x;
assign x[0] = ~b[0];
assign x[1] = (b[0] ^ b[1]);
assign x[2] = ((b[0]&&b[1])^b[2]);
assign x[3] = ((b[0]&&b[1]&&b[2])^b[3]);
assign x[4] = ((b[0]&&b[1]&&b[2]&&b[3])^b[4]);
assign x[5] = ((b[0]&&b[1]&&b[2]&&b[3]&&b[4])^b[5]);
assign x[6] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5])^b[6]);

assign x[7] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6])^b[7]);
assign x[8] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7])
^b[8]);
assign x[9] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8])^b[9]);
endmodule

//11 bit BEC

module bec11bit(x,b);
input [10:0] b;
output [10:0] x;
assign x[0] = ~b[0];
assign x[1] = (b[0] ^ b[1]);
assign x[2] = ((b[0]&&b[1])^b[2]);
assign x[3] = ((b[0]&&b[1]&&b[2])^b[3]);
assign x[4] = ((b[0]&&b[1]&&b[2]&&b[3])^b[4]);
assign x[5] = ((b[0]&&b[1]&&b[2]&&b[3]&&b[4])^b[5]);

assign x[6] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5])^b[6]);
assign x[7] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6])^b[7]);
assign x[8] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7])
^b[8]);
assign x[9] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8])^b[9]);
assign x[10] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8]&&b[9])^b[10]);
endmodule

//12 bit BEC

module bec12bit(x,b);
input [11:0] b;
output [11:0] x;
assign x[0] = ~b[0];
assign x[1] = (b[0] ^ b[1]);
assign x[2] = ((b[0]&&b[1])^b[2]);

assign x[3] = ((b[0]&&b[1]&&b[2])^b[3]);

assign x[4] = ((b[0]&&b[1]&&b[2]&&b[3])^b[4]);
assign x[5] = ((b[0]&&b[1]&&b[2]&&b[3]&&b[4])^b[5]);
assign x[6] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5])^b[6]);
assign x[7] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6])^b[7]);
assign x[8] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7])
^b[8]);
assign x[9] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8])^b[9]);
assign x[10] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8]&&b[9])^b[10]);
assign x[11] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8]&&b[9]&&b[10])^b[11]);
endmodule

//13 bit BEC

module bec13bit(x,b);

input [12:0] b;
output [12:0] x;
assign x[0] = ~b[0];
assign x[1] = (b[0] ^ b[1]);
assign x[2] = ((b[0]&&b[1])^b[2]);
assign x[3] = ((b[0]&&b[1]&&b[2])^b[3]);
assign x[4] = ((b[0]&&b[1]&&b[2]&&b[3])^b[4]);
assign x[5] = ((b[0]&&b[1]&&b[2]&&b[3]&&b[4])^b[5]);
assign x[6] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5])^b[6]);
assign x[7] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6])^b[7]);
assign x[8] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7])
^b[8]);
assign x[9] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8])^b[9]);
assign x[10] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8]&&b[9])^b[10]);
assign x[11] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8]&&b[9]&&b[10])^b[11]);

assign x[12] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8]&&b[9]&&b[10]&&b[11])^b[12]);
endmodule

//14 bit BEC

module bec14bit(x,b);
input [13:0] b;
output [13:0] x;
assign x[0] = ~b[0];
assign x[1] = (b[0] ^ b[1]);
assign x[2] = ((b[0]&&b[1])^b[2]);
assign x[3] = ((b[0]&&b[1]&&b[2])^b[3]);
assign x[4] = ((b[0]&&b[1]&&b[2]&&b[3])^b[4]);
assign x[5] = ((b[0]&&b[1]&&b[2]&&b[3]&&b[4])^b[5]);
assign x[6] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5])^b[6]);
assign x[7] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6])^b[7]);

assign x[8] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7])
^b[8]);
assign x[9] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8])^b[9]);
assign x[10] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8]&&b[9])^b[10]);
assign x[11] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8]&&b[9]&&b[10])^b[11]);
assign x[12] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8]&&b[9]&&b[10]&&b[11])^b[12]);
assign x[13] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8]&&b[9]&&b[10]&&b[11]&&b[12])^b[13]);
endmodule

//15 bit BEC

module bec15bit(x,b);
input [14:0] b;

output [14:0] x;
assign x[0] = ~b[0];
assign x[1] = (b[0] ^ b[1]);
assign x[2] = ((b[0]&&b[1])^b[2]);
assign x[3] = ((b[0]&&b[1]&&b[2])^b[3]);
assign x[4] = ((b[0]&&b[1]&&b[2]&&b[3])^b[4]);
assign x[5] = ((b[0]&&b[1]&&b[2]&&b[3]&&b[4])^b[5]);
assign x[6] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5])^b[6]);
assign x[7] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6])^b[7]);
assign x[8] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7])
^b[8]);
assign x[9] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8])^b[9]);
assign x[10] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8]&&b[9])^b[10]);
assign x[11] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8]&&b[9]&&b[10])^b[11]);

assign x[12] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8]&&b[9]&&b[10]&&b[11])^b[12]);
assign x[13] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8]&&b[9]&&b[10]&&b[11]&&b[12])^b[13]);
assign x[14] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8]&&b[9]&&b[10]&&b[11]&&b[12]&&b[13])^b[14]);
endmodule

//16 bit BEC

module bec16bit(x,b);
input [15:0] b;
output [15:0] x;
assign x[0] = ~b[0];
assign x[1] = (b[0] ^ b[1]);
assign x[2] = ((b[0]&&b[1])^b[2]);
assign x[3] = ((b[0]&&b[1]&&b[2])^b[3]);
assign x[4] = ((b[0]&&b[1]&&b[2]&&b[3])^b[4]);
assign x[5] = ((b[0]&&b[1]&&b[2]&&b[3]&&b[4])^b[5]);

assign x[6] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5])^b[6]);
assign x[7] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6])^b[7]);
assign x[8] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7])
^b[8]);
assign x[9] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8])^b[9]);
assign x[10] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8]&&b[9])^b[10]);
assign x[11] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8]&&b[9]&&b[10])^b[11]);
assign x[12] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8]&&b[9]&&b[10]&&b[11])^b[12]);
assign x[13] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8]&&b[9]&&b[10]&&b[11]&&b[12])^b[13]);
assign x[14] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8]&&b[9]&&b[10]&&b[11]&&b[12]&&b[13])^b[14]);

assign x[15] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8]&&b[9]&&b[10]&&b[11]&&b[12]&&b[13]&&b[14])^
b[15]);
endmodule

//17 bit BEC

module bec17bit(x,b);
input [16:0] b;
output [16:0] x;
assign x[0] = ~b[0];
assign x[1] = (b[0] ^ b[1]);
assign x[2] = ((b[0]&&b[1])^b[2]);
assign x[3] = ((b[0]&&b[1]&&b[2])^b[3]);
assign x[4] = ((b[0]&&b[1]&&b[2]&&b[3])^b[4]);
assign x[5] = ((b[0]&&b[1]&&b[2]&&b[3]&&b[4])^b[5]);
assign x[6] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5])^b[6]);
assign x[7] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6])^b[7]);

assign x[8] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7])
^b[8]);
assign x[9] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8])^b[9]);
assign x[10] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8]&&b[9])^b[10]);
assign x[11] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8]&&b[9]&&b[10])^b[11]);
assign x[12] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8]&&b[9]&&b[10]&&b[11])^b[12]);
assign x[13] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8]&&b[9]&&b[10]&&b[11]&&b[12])^b[13]);
assign x[14] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8]&&b[9]&&b[10]&&b[11]&&b[12]&&b[13])^b[14]);
assign x[15] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8]&&b[9]&&b[10]&&b[11]&&b[12]&&b[13]&&b[14])^
b[15]);

assign x[16] =
((b[0]&&b[1]&&b[2]&&b[3]&&b[4]&&b[5]&&b[6]&&b[7]&
&b[8]&&b[9]&&b[10]&&b[11]&&b[12]&&b[13]&&b[14]&&
b[15])^b[16]);
endmodule

//

//

//

//

//

//

//
//
//
//
//
//
//

//6by3mux
module mux6_3(out,cout,cin,s0,s1,c0,c1);
input [1:0]s0,s1;

input c0,c1,cin;
output [1:0] out;
output cout;
mux212bit u1(.out(out),.i0(s0),.i1(s1),.s1(cin));
mux21 u2(.out(cout),.i0(c0),.i1(c1),.s1(cin));
endmodule

//8by4mux
module mux8_4(out,cout,cin,s0,s1,c0,c1);
input [2:0]s0,s1;
input c0,c1,cin;
output [2:0] out;
output cout;
mux213bit u1(.out(out),.i0(s0),.i1(s1),.s1(cin));
mux21 u2(.out(cout),.i0(c0),.i1(c1),.s1(cin));
endmodule

//10by5mux
module mux10_5(out,cout,cin,s0,s1,c0,c1);
input [3:0]s0,s1;

input c0,c1,cin;
output [3:0] out;
output cout;
mux214bit u1(.out(out),.i0(s0),.i1(s1),.s1(cin));
mux21 u2(.out(cout),.i0(c0),.i1(c1),.s1(cin));
endmodule

//12by6mux
module mux12_6(out,cout,cin,s0,s1,c0,c1);
input [4:0]s0,s1;
input c0,c1,cin;
output [4:0] out;
output cout;
mux215bit u1(.out(out),.i0(s0),.i1(s1),.s1(cin));
mux21 u2(.out(cout),.i0(c0),.i1(c1),.s1(cin));
endmodule

//14by7mux
module mux14_7(out,cout,cin,s0,s1,c0,c1);
input [5:0]s0,s1;
input c0,c1,cin;

output [5:0] out;

output cout;
mux216bit u1(.out(out),.i0(s0),.i1(s1),.s1(cin));
mux21 u2(.out(cout),.i0(c0),.i1(c1),.s1(cin));
endmodule

//18by9mux
module mux18_9(out,cout,cin,s0,s1,c0,c1);
input [7:0]s0,s1;
input c0,c1,cin;
output [7:0] out;
output cout;
mux218bit u1(.out(out),.i0(s0),.i1(s1),.s1(cin));
mux21 u2(.out(cout),.i0(c0),.i1(c1),.s1(cin));
endmodule

//20by10mux
module mux20_10(out,cout,cin,s0,s1,c0,c1);
input [8:0]s0,s1;
input c0,c1,cin;

output [8:0] out;

output cout;
mux219bit u1(.out(out),.i0(s0),.i1(s1),.s1(cin));
mux21 u2(.out(cout),.i0(c0),.i1(c1),.s1(cin));
endmodule

//22by11mux
module mux22_11(out,cout,cin,s0,s1,c0,c1);
input [9:0]s0,s1;
input c0,c1,cin;
output [9:0] out;
output cout;
mux2110bit u1(.out(out),.i0(s0),.i1(s1),.s1(cin));
mux21 u2(.out(cout),.i0(c0),.i1(c1),.s1(cin));
endmodule

//24by12mux
module mux24_12(out,cout,cin,s0,s1,c0,c1);
input [10:0]s0,s1;
input c0,c1,cin;
output [10:0] out;

output cout;
mux2111bit u1(.out(out),.i0(s0),.i1(s1),.s1(cin));
mux21 u2(.out(cout),.i0(c0),.i1(c1),.s1(cin));
endmodule

//26by13mux
module mux26_13(out,cout,cin,s0,s1,c0,c1);
input [11:0]s0,s1;
input c0,c1,cin;
output [11:0] out;
output cout;
mux2112bit u1(.out(out),.i0(s0),.i1(s1),.s1(cin));
mux21 u2(.out(cout),.i0(c0),.i1(c1),.s1(cin));
endmodule

//28by14mux
module mux28_14(out,cout,cin,s0,s1,c0,c1);
input [12:0]s0,s1;
input c0,c1,cin;
output [12:0] out;
output cout;

mux2113bit u1(.out(out),.i0(s0),.i1(s1),.s1(cin));
mux21 u2(.out(cout),.i0(c0),.i1(c1),.s1(cin));
endmodule

//30by15mux
module mux30_15(out,cout,cin,s0,s1,c0,c1);
input [13:0]s0,s1;
input c0,c1,cin;
output [13:0] out;
output cout;
mux2114bit u1(.out(out),.i0(s0),.i1(s1),.s1(cin));
mux21 u2(.out(cout),.i0(c0),.i1(c1),.s1(cin));
endmodule

//32by16mux
module mux32_16(out,cout,cin,s0,s1,c0,c1);
input [14:0]s0,s1;
input c0,c1,cin;
output [14:0] out;
output cout;
mux2115bit u1(.out(out),.i0(s0),.i1(s1),.s1(cin));

mux21 u2(.out(cout),.i0(c0),.i1(c1),.s1(cin));
endmodule

//34by17mux
module mux34_17(out,cout,cin,s0,s1,c0,c1);
input [15:0]s0,s1;
input c0,c1,cin;
output [15:0] out;
output cout;
mux2116bit u1(.out(out),.i0(s0),.i1(s1),.s1(cin));
mux21 u2(.out(cout),.i0(c0),.i1(c1),.s1(cin));
endmodule

//

//

//

//

//
//

//
MUX Designs

//
///
///

///

////

//2bit2by1mux
module mux212bit(out,i0,i1,s1);
input[1:0] i0,i1;
input s1;
output[1:0] out;
assign out = (s1?i1:i0);
endmodule

//3bit2by1mux
module mux213bit(out,i0,i1,s1);
input[2:0] i0,i1;
input s1;
output[2:0] out;
assign out = (s1?i1:i0);
endmodule

//4bit2by1mux
module mux214bit(out,i0,i1,s1);

input[3:0] i0,i1;
input s1;
output[3:0] out;
assign out = (s1?i1:i0);
endmodule

//5bit2by1mux
module mux215bit(out,i0,i1,s1);
input[4:0] i0,i1;
input s1;
output[4:0] out;
assign out = (s1?i1:i0);
endmodule

//6bit2by1mux

module mux216bit(out,i0,i1,s1);
input[5:0] i0,i1;
input s1;
output[5:0] out;
assign out = (s1?i1:i0);

endmodule

//7bit2by1mux
module mux217bit(out,i0,i1,s1);
input[6:0] i0,i1;
input s1;
output[6:0] out;
assign out = (s1?i1:i0);
endmodule

//8bit2by1mux
module mux218bit(out,i0,i1,s1);
input[7:0] i0,i1;
input s1;
output[7:0] out;
assign out = (s1?i1:i0);
endmodule

//9bit2by1mux
module mux219bit(out,i0,i1,s1);
input[8:0] i0,i1;

input s1;
output[8:0] out;
assign out = (s1?i1:i0);
endmodule

//10bit2by1mux
module mux2110bit(out,i0,i1,s1);
input[9:0] i0,i1;
input s1;
output[9:0] out;
assign out = (s1?i1:i0);
endmodule

//11bit2by1mux
module mux2111bit(out,i0,i1,s1);
input[10:0] i0,i1;
input s1;
output[10:0] out;
assign out = (s1?i1:i0);
endmodule

//12bit2by1mux
module mux2112bit(out,i0,i1,s1);
input[11:0] i0,i1;
input s1;
output[11:0] out;
assign out = (s1?i1:i0);
endmodule

//13bit2by1mux
module mux2113bit(out,i0,i1,s1);
input[12:0] i0,i1;
input s1;
output[12:0] out;
assign out = (s1?i1:i0);
endmodule

//14bit2by1mux
module mux2114bit(out,i0,i1,s1);
input[13:0] i0,i1;
input s1;

output[13:0] out;
assign out = (s1?i1:i0);
endmodule

//15bit2by1mux
module mux2115bit(out,i0,i1,s1);
input[14:0] i0,i1;
input s1;
output[14:0] out;
assign out = (s1?i1:i0);
endmodule

//16bit2by1mux
module mux2116bit(out,i0,i1,s1);
input[15:0] i0,i1;
input s1;
output[15:0] out;
assign out = (s1?i1:i0);
endmodule

//2by1 Mux
module mux21(out,i0,i1,s1);
input i0,i1,s1;
output out;
assign out = (s1?i1:i0);
endmodule

//Full adeer Design

module fa(sum,carry,a,b,cin);
input a,b;
input cin;
output sum,carry;
assign sum = a^b^cin;
assign carry = ((a&&b)||(b&&cin)||(a&&cin));
endmodule