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Experiment No.-01: Objective Practical Significance

This document describes an experiment to implement a half adder using VHDL. It defines the objective as writing a VHDL program for a half adder using logic gates. It provides background on HDL design and lists the required resources. It then explains the principal of a half adder, provides the truth table, and shows the circuit diagram and VHDL code. It also includes the results waveform and concludes by describing the half adder's functionality of adding two binary inputs to produce a sum and carry output.

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35 views3 pages

Experiment No.-01: Objective Practical Significance

This document describes an experiment to implement a half adder using VHDL. It defines the objective as writing a VHDL program for a half adder using logic gates. It provides background on HDL design and lists the required resources. It then explains the principal of a half adder, provides the truth table, and shows the circuit diagram and VHDL code. It also includes the results waveform and concludes by describing the half adder's functionality of adding two binary inputs to produce a sum and carry output.

Uploaded by

RajBhan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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EXPERIMENT No.

-01

OBJECTIVE Write a VHDL program to implement a


half adder using logic gates.

PRACTICAL SIGNIFICANCE HDL (Hardware


Description Language) based design has established itself
as the modern approach to design of digital systems, with
VHDL (VHSIC Hardware Description Language) and Verilog
HDL being the two dominant HDLs.

RESOURCE REQUIRED Computer System,


Software : Xilinx ise 9.2i,
Book: Digital Logic and Computer Design by M. Morris
Mano.

PRINCIPAL OF EXPERIMENT Half adder is


combinational arithmetic circuit that adds two numbers
and produces a sum bit (S) and carry bit (C) as the output.
If A and B are the input bits, then sum bit (S) is the X-OR
of A and B and the carry bit (C) will be the AND of A and
B. From this it is clear that a half adder circuit can be
easily constructed using one X-OR gate and one AND gate.
Half adder is the simplest of all adder circuit, but it has a
major disadvantage. The half adder can add only two
input bits (A and B) and has nothing to do with the carry if
there is any in the input. So if the input to a half adder
have a carry, then it will be neglected it and adds only the
A and B bits. That means the binary addition process is not
complete and thats why it is called a half adder.
TRUTH TABLE FOR HALF ADDER
inputs

A
0

B
0

outputs
C
S
0
0

0
1
1

1
0
1

S=AB
S=AB+AB

0
0
1

1
1
0
C=A.B

CIRCUIT DIAGRAM
a) Half Adder --

b) XOR Gate

VHDL CODE FOR HALF ADDER


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity vivek is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
S : out STD_LOGIC;
C : out STD_LOGIC);
end vivek;
architecture Behavioral of vivek is
begin
S <= A xor B;
C <= A and B;
end Behavioral;

RESULTS/Waveform

CONCLUSION The HALF ADDER adds two binary


number (one bit) A & B. The HALF ADDER produces two
bit output ,one bit as the sum (S) of inputs and other one
as the carry (C).

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