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Omair Akhtar 120526 Bemts (6A) Assignment 5

The document contains Verilog code for several shift register designs including 16-bit and 8-bit shift left registers with serial in serial out, an 8-bit shift left/right register with serial in serial out, an 8-bit shift left register with serial in parallel out, a universal 8-bit shift register, and code to generate a 100 millisecond derived clock. It also includes test fixture code to simulate and test the designs. The summary notes that the shift register codes contain no errors but the test fixtures have problems, and one test fixture code is noted to contain errors.

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68 views6 pages

Omair Akhtar 120526 Bemts (6A) Assignment 5

The document contains Verilog code for several shift register designs including 16-bit and 8-bit shift left registers with serial in serial out, an 8-bit shift left/right register with serial in serial out, an 8-bit shift left register with serial in parallel out, a universal 8-bit shift register, and code to generate a 100 millisecond derived clock. It also includes test fixture code to simulate and test the designs. The summary notes that the shift register codes contain no errors but the test fixtures have problems, and one test fixture code is noted to contain errors.

Uploaded by

HammadMehmood
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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OMAIR AKHTAR

120526
BEMTS (6A)
Assignment 5

16 bits Shift left Register serial in serial out code:


module Regsiter16bitsSiSO(clk,si,so);
input clk,si;
output so;
reg [15:0] temp;
initial temp=16'b0101100100001111;
always @(posedge clk)

begin
temp <= {temp[14:0],si};
end
assign so = temp[15];
endmodule

Test Fixture Code:


initial begin
// Initialize Inputs
clk = 0;
si = 1;
// Wait 100 ns for global reset to finish
#10;
clk = 1;
si = 1;
// Wait 100 ns for global reset to finish
#10;

clk = 0;
si = 1;
// Wait 100 ns for global reset to finish
#10;
clk = 1;
si = 1;
//**Follow and give values according to requirements
end
endmodule

8bit Shift left/right Regsiter serial in serial out code:


module RegiterLRSiSo(si,so,clk,s);
input si,clk,s;
output so;
reg so;
reg [7:0] temp;
initial temp = 8'b01010011;
always @(posedge clk)
begin
if (s==1)
begin

temp <= {si,temp[7:1]};


so <= temp[0];
end
else
begin
temp <= {temp[6:0],si};
so <= temp[7];
end
end
endmodule

initial begin
Test Fixture
code:

s = 0;
// Wait 10 ns for global reset to finish
#10;

// Initialize Inputs
si = 1;
clk = 0;
s = 0;
// Wait 10 ns for global reset to finish
#10;

si = 1;
clk = 0;
s = 0;
//**Follow and give values according to requirements
end
endmodule

si = 1;
clk = 1;

8bit Shift left serial in parallel out:


module Register8BitSiPo(clk,si,po);
input clk,si;
output [7:0] po;
reg [7:0] temp;
initial temp=8'b11001010;
always @(posedge clk)

begin
temp <= {temp[6:0],si};
end
assign po = temp;
endmodule

Test Fixture code:


initial begin
// Initialize Inputs
clk = 0;
si = 0;
// Wait 100 ns for global reset to finish
#10;
clk = 1;
si = 1;
// Wait 100 ns for global reset to finish
#10;

clk = 0;
si = 0;
// Wait 100 ns for global reset to finish
#10;
clk = 1;
si = 1;
//**Follow and give values according to requirements
end
endmodule

Universal 8 bit shift regsiter:


module Uni8bitReg(clk,clr,s,si,so,pi,po);
input si,clk,clr;
input [1:0] s;
input [7:0] pi;
output so;
output [7:0] po;
reg so;
reg [7:0] temp,po;
initial temp=8'b01010011;

else if (s==1)
begin
temp <= {si,temp[7:1]};
so <= temp[0];
end
//parallel in serial out
else if (s==2)
begin
temp <= pi;
so <= temp[0];
end
//serial in parallel out
else
begin
temp <= {si,temp[7:1]};
po <= temp;
end

always @(posedge clk)


begin
if (~clr)
temp <= 8'b00000000;
else
begin
//parallel in parallel outt
if (s==0)
begin
temp <= pi;
po <= temp;
end
//serial in serial out

end
end
endmodule

Test Fixture code:


initial begin

clk = 1;
clr = 0;
s = 2'b00;
si = 1;
pi = 8'b11001011;
// Wait 100 ns for global reset to finish
//**Follow and give values according to requirements
end
endmodule

// Initialize Inputs
clk = 0;
clr = 0;
s = 2'b00;
si = 1;
pi = 8'b11001011;
// Wait 100 ns for global reset to finish
#10;

Note: No Errors in code But problem in Waveform.

Derived Clock Code:


module Der100MilliClock(clk,reset,clkout);
input clk,reset;
output clkout;
reg clkout;
parameter period=10000000;
parameter N=23;
parameter halfperiod=period/2;
reg [N:0] countvalue;
always @ (posedge clk)
begin
if (reset)
begin
countvalue = 0;
clkout <= 0;
end

else
begin
if(countvalue == period -1)
begin
countvalue =0;
clkout <= 0;
end
else
countvalue = countvalue +1;
if (countvalue == halfperiod)
clkout <= 1;
end
end
endmodule

Test Fixture Code:


clk = 0;
reset = 0;
always @(posedge clk)
begin
//clk=1;
//#10
//clk=0;
//#10
// Add stimulus here

initial begin
// Initialize Inputs
clk = 0;
reset = 1;
// Wait 100 ns for global reset to finish
#10;
clk = 1;
reset = 1;
// Wait 100 ns for global reset to finish
#10;

end
endmodule

Note: Problem (Errors) in test Fixture code , No errors in other code.

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