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College of Engineering & Management: Department of Electronics & Communication

This document contains information about two tests conducted for the Fundamentals of HDL course. Test 1 contains three questions related to different HDL description styles in VHDL, writing programs for combinational logic circuits, and performing logic operations. Test 2 contains three questions about synthesis of VHDL code, mapping assignment statements to gates, and writing code for a JK flip-flop. Both tests were administered to 4th year section A and B students and were evaluated by two faculty members.

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saralabitm
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37 views

College of Engineering & Management: Department of Electronics & Communication

This document contains information about two tests conducted for the Fundamentals of HDL course. Test 1 contains three questions related to different HDL description styles in VHDL, writing programs for combinational logic circuits, and performing logic operations. Test 2 contains three questions about synthesis of VHDL code, mapping assignment statements to gates, and writing code for a JK flip-flop. Both tests were administered to 4th year section A and B students and were evaluated by two faculty members.

Uploaded by

saralabitm
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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SAHYADRI

COLLEGE OF ENGINEERING &


MANAGEMENT
DEPARTMENT OF ELECTRONICS & COMMUNICATION
FUNDAMENTALS OF HDL -10EC45
Test II

Date: 02-03-2013

Sem/Section: 4th A,B


Question
No.
a
1

Duration: 1.15 Hour

Max.Marks: 25

Faculty: Ms. Supreetha Rao , Ms. Deeksha Rai


NOTE: Answer any TWO full questions
Question

Describe synthesis information from entity and module with examples.

4 marks

Explain Booth algorithm with flow chart, code by taking necessary examples.

6 marks

Explain mapping the case, casex statements using synthesis.

6marks

a
2
b

Marks
Awarded

Explain the difference between signal and variable assignment statements


using D-latch with necessary waveforms and also write the code for both.
Explain mapping the signal and variable assignment statements to gate level
with suitable examples.

6.5marks
6.5
marks

3
b

Write the VHDL code for positive edge triggered JK flip flop using case
statement.

6 marks

SAHYADRI
COLLEGE OF ENGINEERING &
MANAGEMENT
DEPARTMENT OF ELECTRONICS & COMMUNICATION
FUNDAMENTALS OF HDL -10EC45
Date: 14-03-2013

Test I

Sem/Section: 4th A,B

Question

No.

Mention the types of HDL description. Explain dataflow and behavioral description
in VHDL.
Explain with programs structural description in VHDL.

b
c
a

Max.Marks: 25

Faculty: Ms. Supreetha Rao , Ms. Deeksha Rai


NOTE: Answer any TWO full questions

Question

Duration: 1.15 Hour

b
c

Explain with programs switch level description in VHDL.

Write a program for 2x2 unsigned combinational array multiplier.

4 marks
4.5
marks
4marks
4.5marks

Describe the different data types in VHDL.

3marks

Compare VHDL and Verilog.

5marks

Write a dataflow description of a full adder with enable. If enable is low


sum and carry are zero otherwise sum and carry are the usual output. Use a
5ns delay for any gate including XOR. Draw the truth table of this adder.
Given A=1000 and B=0011, perform the following operation,

Marks
Awarded

i)
ii)
iii)

5 marks

3 marks

shift B two position left logical


AXNORB
Reduction NAND

Describe the different data operators in verilog.

4.5
marks

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