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Desain Sistem Digital: Data Tipe Dan Operator Aritmatika Eko Setiawan

This document discusses digital system design and arithmetic operators in VHDL. It covers data types, arithmetic libraries, type casting, concatenation, tri-state conditions, processes, if-else statements, comparison operators, case statements, constants, generics, and provides an example design task to create a logic circuit with 4 gates, 4 inputs and 4 outputs along with truth table and VHDL simulation.

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Heri J Situmorang
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© © All Rights Reserved
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Download as PPTX, PDF, TXT or read online on Scribd
12 views

Desain Sistem Digital: Data Tipe Dan Operator Aritmatika Eko Setiawan

This document discusses digital system design and arithmetic operators in VHDL. It covers data types, arithmetic libraries, type casting, concatenation, tri-state conditions, processes, if-else statements, comparison operators, case statements, constants, generics, and provides an example design task to create a logic circuit with 4 gates, 4 inputs and 4 outputs along with truth table and VHDL simulation.

Uploaded by

Heri J Situmorang
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Desain Sistem Digital

Data Tipe dan Operator Aritmatika


Eko Setiawan

Operator

Tipe Data

Sebelum melakukan operasi aritmatika harus dilakukan


pemanggilan library numerik
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
...
signal sl, s2, s3, s4, s5, s6: std_logic_vector(3 downto 0 );
signal ul, u2, u3, u4, u5, u6, u7: unsigned(3 downto 0);
...

Library Aritmatika

Casting atau konversi antar tipe data perlu dilakukan saat


menghubungkan sinyal dengan data berbeda
ul <= unsigned( s1 ); -- type casting
u2 <= to_unsigned( 5,4 ) ; -- conversion function
s2 <= std_logic_vector( u3 ); -- type casting
s3 <= std_logic_vector( to_unsigned ( 5,4 ));
s5 <= std_logic_vector( unsigned(s2) + unsigned(s1));
s6 <= std_logic_vector( unsigned(s2) + 1) ;

Casting

Concenation menggabungkan dua buah array 1-D menjadi


satu array 1-D

signal a1: std_logic ;


signal a4: std_logic_vector (3 downto 0);
signal b8, c8, d8: std_logic_vector (7 downto 0) ;
...
b8 <= a4 & a4;
c8 <= a1 & a1 & a4 & 00;
d8 <= b8(3 downto 0) & c8(3 downto 0);

Concenation

VHDL merepresentasikan kondisi logika menjadi 1, 0 dan Z yang mewakili


kondisi high-impedance

entity bi-demo is
port ( bi : inout std_logic ;

)
begin
sig_out <= output_expression;

bi <= sig_out when dir=l else Z;


sig_in <= bi;

Tri-state condition

process (a,b)
begin
c <= a and b;
c <= a or b;
end process;
sama dengan kode:
process (a,b)
begin
c <= a or b;
end process;

Process

Proses digunakan jika


kode ingin dieksekusi
secara urut
Proses digunakan untuk
meminimalkan kesalahan
Apabila terdapat dua
koneksi, sinyal yang
dihubungkan adalah
ekspresi yang paling akhir

architecture if_arch of decoder_2_4 is begin


process (en,a)
begin
if (en=0) then
y <= 0000;
elsif (a=00) then
y <= "0001;
elsif (a="01) then
y <= "0010";
elsif (a="10") then
y <= "0100";
else
y <= "1000";
end if ;
end process;
end if-arch;

If-else

large <= a when a > b else b;


small <= b when a > b else a;
Sama seperti:
process (a,b) begin
if a>b then
large <= a;
small <= b;
else
large <= b;
small <= a;
end if;
end ;

Comparison

process (a,b,c,sel)
begin
case sel is
when 00 =>
r <= a + b + c;
when 10 =>
r <= a - b;
when others =>
r <= c + 1;
end case;
end process;
Sama dengan kode:
with sel select
r <= a + b + c when 00 ,
ab
when 10 ,
c+1
when others ;

Case

Constant digunakan untuk merepresentasikan konstanta dan dideklarasikan dalam architecture


constant const_name : data_type : = value_expression;
Generic juga digunakan untuk merepresentasikan konstanta. Generic dideklarasikan pada entity
sehingga dapat diakses dari luar blok
entity entity_name is
generic (
generic_name : data_type : = default_values ;
)
port (
port_name : mode data_type ;
);
end entity_name;

Constant and Generics

Rancanglah rangkaian logika dengan yang minimal terdiri


dari :
4 gerbang,
4 masukan dan
4 keluaran

Sertakan tabel kebenaran (25%) dan gambar rangkaian


(25%)
Simulasikan kode VHDL pada ISE (50%)
Kumpulkan dalam softcopy (boleh scan, foto, atau screen
capture)

Tugas-2

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