Run Options
Run Options
Synopsys, Inc.
Version I-2014.03LC
Project file D:\isplever_classic1_8\trabajos\5em5\pruebas\run_options.txt
Written on Mon Jan 26 22:21:03 2015
#project files
add_file -verilog
og/mach.v"
add_file -verilog
add_file -verilog
add_file -verilog
add_file -verilog
"d:/ispLEVER_Classic1_8/ispcpld/../cae_library/synthesis/veril
"./prueba01.h"
"./siete.v"
"./cuenta4.v"
"./cuena4bcd.v"
#implementation: "pruebas"
impl -add pruebas -type fpga
#
#implementation attributes
set_option -vlog_std v2001
set_option -num_critical_paths 3
set_option -num_startend_points 0
#device options
set_option -technology ispmach4000b
set_option -part LC4064B
set_option -package T44C
set_option -speed_grade -2.5
set_option -part_companion ""
#compilation/mapping options
set_option -top_module "cuenta4bcd"
# mapper_options
set_option -frequency 200
set_option -auto_constrain_io 1
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -srs_instrumentation 1
# Lattice ispMACH4000
set_option -maxfanin 20
set_option -RWCheckOnRam 1
set_option -maxterms 16
set_option -areadelay 0
set_option -disable_io_insertion 0
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 1
set_option -resource_sharing 1
# Compiler Options
set_option -auto_infer_blackbox 0