MOS/LSI DATABOOK NAO] NN SEMICONDUCTOREdge Index by Product Family Clocks Counters/Timers Electronic Organ Circuits TV Circuits Analog to Digital (A/D) Converters Communications/CB Radio Circuits Watches Calculators | Controller Oriented Processor Systems (COPS) Keyboard Encoder Circuits Interface Drivers Displays Clock Modules Custom MOS/LSI RRR ABARORONROOEOWh4 Edge Index by Product Family, Alpha Numerical Index CLOCKS ~ SECTION 1 M5309 Digital Clock MMB311 Digital Clock MMB312 Digital Clock MM5313 Digital Clock M5314 Digital Clock MM5315 Digital Clock MWMI5316 Digital Alarm Clock MMB318 TV Digital Clock M5370 Digital Alarm Clock MMB371 Digital Alarm Clock MMB5375XX Series Clocks. MM5376XX Series Clocks MMS377 Auto Clock MMS378 Auto Clock MM5379 Auto Clock M5322 Digital Calendar Clock Radio Circuit MM5383 Digital Calendar Clock Radio Circuit MM5384 LED Display Digital Clock Radio Circuit, MM5385 Digital Alarm Clock MMS386 Digital Alarm Clock M5387 AA Digital Alarm Clock MMI5396 Digital Alarm Clock 'MMB5397 Digital Alarm Clock MMS402 Digital Alarm Clock MMS5406 Digital Alarm Clock MM53108 Digital Alarm Clock. AN-143 Using National Clock Integrated Circuits in Timer Applications COUNTERS/TIMERS — SECTION 2 MMS307 Baud Rate Generator/Programmable Divider M5369 17-Stage Programmable Oscillator/Divider M5865 Universal Timer MM53107 17-Stage Oscillator/Divider AN-168 MMS5G65 Universal Timer Applications. AN-169 A 4-Digit, 7-Function Stopwatch/Timer ELECTRONIC ORGAN CIRCUITS — SECTION 3 MMB5554 Frequency Divider MMB5555 Chromatic Frequency Generator MMB556 Chromatic Frequency Generator MMS559 Serial-to Parallel Converter MM5828 Frequency Divider MM5824 Frequency Divider Table of Contents 12 12 12 12 12 12 19 42 1g 4g 421 127 1.33 4:38 1.38 1.43 1.43 1-50 156 1.86 1-62 156 186 1-68, 1-68 1-62 174 22 27 2410 2-20 2.23 2:33 32 34 34 36 38 38ELECTRONIC ORGAN CIRCUITS — SECTION 3 (Continued! MM5832 Chromatic Frequency Generator ant MM5833 Chromatic Frecuency Generator 341 MM5837 Digital Noise Source 344 MM5871 Rhythm Pattern Generator. 346 MMS891 MOS Top Octane Frequency Generator 3.19 TV CIRCUITS ~ SECTION 4 LM 1889" TV Video Modulator 448 MMS318 TV Digital Clock 42 MM8320 TV Camera Sync Generator 46 MM5321 TV Camera Sync Generator 412 MMS322 Color Bar Generator Chip 418 MM5840 TV Channel Number (16 Channels) and Time Display Circuit 4-23 MM5841 TV Channel Number and Time Readout Circuit 4.28 MM5878 Remote Control Potentiometer 457 MM53100 Programmable TV Timer/Alarm Clock 4:32 MM53104* TV Game Clock Generator (NTSC) with reference to MM53114 TV Game Clock Generator (PAL) 4-60 MMS3105 Programmable TV Timer/Alarm Clock 4-32 MM57100° TV Game Circuit (NTSC) with reference to MMS7105 TV Game Circuit (PAL) 4-37 MM58106 Digital Clock and TV Display Circuit 4-53 ANALOG TO DIGITAL (A/D) CONVERTERS — SECTION 5 LF13300 Integrating A/D Analog Building Block 52 M5330 4 1/2-Digit Pane! Meter Logic Block 5.23 MMB5863 12-Bit Binary A/D Building Block 530 AN-165 Digital Voltmeters and the MM5330 5:38 AN-156 Specifying A/D and D/A Converters 548 COMMUNICATIONS/C.B. RADIO CIRCUITS — SECTION 6 M303 Universal Fully Asynchronous Receiver/Transmitter 62 M5393 Push Button Telephone Dialer 68 MM5395 TOUCH: TONE® Generator en MMS5104 PLL Frequency Synthesizer 6-16 MMS5106 PLL Frequency Synthesizer 616 MM55108 PLL Frequency Synthesizer with Receive/Transmit Mode, 6-20 MM55110 PLL Frequency Synthesizer with Receive/Transmit Mode. 6-20 MM55114 PLL Frequency Synthesizer 6.16 MM55116 PLL Frequency Synthesizer 6-16 WATCHES — SECTION 7 MM5829 LED Watch Circuit 72 MMB5860 LED Watch Circuit 76 M5879 RC Circuit 72 M5880 LED Waten Circuit 76 M5885 Direct Drive LED Watch 713 MMB5886 Direct Drive LED Watch 7413 MMB5889 RC Circuit. 712 MM5890 LCD Chronograph Circuit 7-20 M5899 RC Circuit 792 MMS58104 Direct Drive LED Watch, rar MMS58115 Digitally Tuned, Direct Drive, 6-Function LED Watch 7:32 MMB58117 LCD Watch Girevit 7.40 MM58118 LCD Watch Circuit 7-40 1MM58119 LCD Watch Circuit ceeeee ee sees 740 “TV Game Kit #SK1115 includes tht circuit ‘TOUCH-TONE® is 2 Registered Trademark of Bell TelephoneWATCHES ~ SECTION 7 (Continued) |MM58120 LCD Watch Circuit (MIM58127 LCD Watch Circuit MM58128 LCD Watch Circuit MM§8129 LCD Wateh Circuit MM58130 LCD Watch Circuit MM58601 Two Time Zone LED Watch Circuit MM58801 Two Time Zone LED Watch Circuit CALCULATORS — SECTION 8 1MM5734 8-Function, Accumulating Memory Calculator MM5737 8 Digit, 4-Function, Floating Decimat Point Calculator M5758 Scientific Caloulator M5760 Slide Rule Calculator. MM5762 Financial Calculator MMB5763 Statistical Calculator MM5764 Conversion Calculator MMB765 Calculator Programmer MMB5766 Calculator Programmer M5767 Slide Rule Calculator MMS777 6-Digit, 4:Function, Floating Decimal Point Calculator M5780 Educational Toy Calculator MMS5791 7-Funetion, Accumulating Memory Calculator MM5794 7-Function, Accumulating Memory, Vacuum Fluorescent Display Catoulator M5795 7-Function, Accumulating Memory, Vacuum Fluorescent Display Calculator. MM57103 Scientific Calculator Circuit MMB7104 Scientific Calculator Circuit MMS7123 Financial Calculator MMB57135 Scientific Calculator ROM MMB57136 RPN Scientific Calculator Control ROM AN-112 Calculator Chip Makes a Counter, AN-119 Calculator Learns to Keep Time AN-149 Handheld Calculator Battery Systems [AN-176 Using Standard Notional Calculators in Industrial and Microprocessor Applications CONTROLLER ORIENTED PROCESSOR SYSTEMS (COPS) — SECTION 9 Nationat’s Controller Oriented Processor Systems MM5781 Controller Oriented Processor System. MM5782 Controller Oriented Processor System. MMS785 RAM Interface Chip M5788 Printer Interface Chip MM5799 Controller Oriented Processor MM57109 Number Processing Unit MM57126 COPS Memory MM57140 Controller Oriented Processor KEYBOARD ENCODER CIRCUITS — SECTION 10 MM5740 90-Key Keyboard Encoder MMB745 78-Key Keyboard Encoder MM5746 78-Key Keyboard Encoder MMS4C922/MIM74C922 16-Key Encoder. MM54C923/MM74C923 20-Key Encoder. AN-128 Microprocessor Mates with MOS/LSI Keyboard Encoder AN-139 MOS Encoder Plus PROM Yield Quick Turnaround Keyboard Systems 7.40 747 747 747 2.47 76 76 82 88 ata 8.26 835 8.46 858 8.65 8-76 8.80 B84 8.90 8-96 8.105 B114 8.123 8.132 B14 8-163 8.157 8-163 8.169 8177 8.181 92 93 93 945 921 927 9-39 9-40 9-46 102 10-10 10-10 10-16 10-16 10.21 10.27INTERFACE DRIVERS — SECTION 11 Display Driver Selection Guide. (CD45118M/CD45118C BCD-t0-7-Segment Latch/Decoder/ Driver 10S7664/0S8664 14-Dicit Decoder/Driver with Low Battery Indicator DS8665 14-Digit Decoder Driver (Hi-Drive) DS8666 14-Digit Decoder ‘Driver [P.0.8.) 1038692 Printing Calculator Interface Set 058693 Printing Calculator Interface Set 1938694 Printing Calculator Interface Set (058867 8 Segment Driver DS886B 12-Dig't Decoder/Driver 1D$8871 Saturating LED Cathode Driver 1038872 Saturating LED Cathode Driver 038873 Saturating LED Cathode Driver . . 038874 9-Digit Shift input LED Driver. 038877 6-Digit LED Driver. 1038892 Programmabie Hex LED Digit Driver 1DS8977 Saturating LED Cathode Driver . 875491 MOS-t0 LED Quad Segment Driver 1DS75492 MOS:to LED Hex Digit Driver DS75493 Quad LED Segment Oriver. MN54C48/MM74C48 BCD-10-7-Segment Decoder, ‘MM'S4C9 15/MIM74C915 7-Segmentte-BCD Converter DISPLAYS — SECTION 12 NSA 1100 Series 0.100 Inch 9-Digit LED Display NSA 1298 0.110 Inch 9-Digit LED Display NSA 5120 1/8 Inch 12-Digit LED Disalay NSA 8140 1/8 Inch 14-Digit LED Display NSB 5917 0.5 Inch 5-Digit Numeric Display NSB 5921 0.5 Inch 5-Digit Numeric Display NSB 5922 0.5 Inch 5-Digit Numeric Display Multi-Digit LED Numeric Series AN-170 Mounting Techriques for Multidigit LED Numeri¢ Display CLOCK MODULES -- SECTION 13 MA1002 LED Display Digital Electronic Clock Module MA1003 12 Voc Automotive/Instrument Clack Module NA1010 LED Display Digital Electronic Clock Module NVAI012 LED Display Digital Electronic Clock Module NA1013 LED Display Digita! Electronic Clack Module CUSTOM MOS/LSt -- SECTION 14 Custom MOS at National ORDERING INFORMATION/PHYSICAL DIMENSIONS ‘Ordering Information Physical Dimensions. Definition of Terms 112 144 119 11.412 1145, wg nae 118 11.25, 11.27 = 11-29, 11.29 11:29, 11.31 11.33 11-35, 11.29 11:37 1137 11-40 11.42 11.46 122 126 128 1210 1212 12.12 1212 1214 12.22 132 138 13.11 13.17 13-23 142 At AQ Ag Ral SWE AN — " Anant te 9a sen ony sty fr 2 eat ee, it He ene Ie aN HN te AN in ate te RE ty 5Alpha-Numerical ta CD4511BC BCD-to-7-Segment Lateh/Decoder/Driver CD4511BM BCD-to-7-Segment Latch/Decoder/Driver $7664 14.0 igit Decoder/Driver with Low Battery Indicator $8664 14.D git Decoder/Driver with Low Battery Indicator DSB6ES 14-Digit Decoder/Driver (Hi-Drive) DSBESE 14-0 igit Decoder Driver [P.0.S.) 1D$8692 Printing Calculator Interface Set $8693 Printing Calculator Interface Set. $8694 Printing Calculator Interface Set DS8867 8-Segment Driver $8868 12 Digit Decoder/Driver DS8871 Saturating LED Cathode Driver $8872 Saturating LED Cathode Driver $8873 Saturating LED Cathode Driver $8974 9-Digit Shift Input LED Driver DS8877 6 Digit LED Driver $8892 Programmable Hex LED Digit Driver $8977 Saturating LED Cathode Driver D$75491 MOS-to-LED Quad Segment Driver 0875492 MOS:t0-LED Hex Digit Driver 10$75493 Quad LED Segment Driver. LF13300 Integrating A/D Analog Building Block LIM1889 TV Video Modulator MA1002 LED Display Digital Electronic Clock Module MA1003 12 Voc Automotive/Instrument Clock Module MA1010 LED Display Digital Electronic Clock Module MA1012 LED Display Digital Electronic Clock Module MA1013 LED Display Digital Electronic Clock Module MM5303 Universal Fully Asynchronous Receiver/Transmitter M5307 Baud Rate Generator/Programmable Divider 'MM5309 Digital Clock ‘MNM5311 Digital Clock MM5312 Digital Clock MIM5313 Digital Clock MM5314 Digital Clock MM5315 Digital Clock MM5316 Digital Alarm Clock MM5318 TV Digital Clock MMS320 TV Camera Sync Generator M5321 TV Camera Syne Generator M5322 Color Bar Generator Chip, M5330 4 1/2-Digit Pane! Meter Logic Block. MM5369 17-Stage Programmable Oscillator/Divider: MMS370 Digital Alarm Clock MMB371 Digital Alarm Clock MMB375XX Series Clocks MM5376XX Series Clocks M5377 Auto Clock MMB378 Auto Clock MMB379 Auto Clock : : M6382 Digital Calendar Clock Radio Circuit Index 14 14 19 119 42 48 11-18 14.18 11.18 11:25 1127 11:29 11.29 11:29 at 11.33 11.35 11.29 11.37 a7 11.40 62 4.48 13.2 138 13.411 13.17 13.23, 62 22 12 12 12 12 12 12 19 42 46 412 418 5:23 27 14 114 421 1.27 133 1:38 1-38 1-43MM5383 Digital Calendar Clock Radio Circuit MME384 LED Display Digital Clock Radio Circuit MMIS3B5 Digital Alarm Clock IMME386 Digital Alarm Clock MMB387 AA Digital Alarm Clock MRI5993 Push Button Telephone Disler. MNM5395 TOUCH-TONE” Generator MM5396 Digital Alarm Clock MMB397 Digital Alarm Clock MNI5402 Digital Alarm Clock IMM5405 Digital Alarm Clock MMBS54 Frequency Divider M5585 Chromatic Frequency Generator MMIB55E Chromatic Frequency Generator IMM55S9 Serial-xo Parallel Converter M5734 8 Function, Accumulating Memory Calculator MMS737 8.Digit, Function, Floating Decimal Point Caleulator MM5740 90-Key Keyboard Encoder MMB745 78-Key Keybosrd Encoder MN5746 78-Key Keyboard Encoder MM5758 Scientific Calculator M5760 Slide Rule Calculator MMB 762 Financial Calcviator MMB763 Statistical Caleulator MMB764 Conversion Calculator M5765 Calculator Programmer MMB766 Calculator Programmer MMB5767 Slide Rule Calculator. M5777 6:Digit, 4-Function, Floating Decimal Point Calculator MM780 Educational Toy Calculator MM5781 Controller Oriented Processor System. MM5782 Controller Oriented Processor System MM5785 RAM Interface Chip MMB788 Printer Interface Chip MN5791 7-Function, Accumulating Memory Calculator MMS794 7-Function, Accumulating Memory, Vacuum Fluorescent Display Calculator MMB796 7-Function, Accumulating Memory, Vacuum Fluorescent Display Calculator Circuit MM5799 Controller Oriented Processor MMB823 Frequency Divider MWM§824 Frequency Divider MM5828 LED Watch Circuit MM5B32 Chromatic Frequency Generator MMB5833 Chromatic Frequency Generator MIM5837 Digital Noise Source MNM5B40 TV Channel Number (16 Channels) and Time Display Circuit MMSB41 TV Channel Number and Time Readout Circuit MMIBB60 LED Watch Circuit MMB863 12-Bit Binary A/D Building Block [MMBB6B Universal Timer MMB871 Rhythm Pattern Generator MMB878 Remote Control Potentiometer MM5B79 RC Circuit MIM5880 LED Watch Circuit MIMB8B5 Direct Drive LED Watch M5886 Direct Drive LED Watch MMBBB9 RC Circuit MNI5B90 L.CD Chronograph Circuit MMB891 MOS Top Octane Frequency Generator M5899 RC Circuit MMS3100 Programmable TV Timer/Alarm Clock TOUCH-TONE" is Registered Trademark of Bll Telephone 143 1.50 186 158 1-62 68 en 156 156 1.68 1-68 32 34 34 36 82 88 102 1010 10-10 B14 826 8:35 8.46 856 8-66 876 8-80 a84 8.90 93 93 918 921 8.96 8-105 ara 927 38 38 72 341 ant 344 423 428 76 5-30 210 3.16 457 742 76 713 7413 712 7:20 349 712 4-32MM53104* TV Game Clock Generator (NTSC) with reference to MM531 14 TV Game Clock Generator (PAL) MM53105 Programmable TV Timer/Alarm Clock MM53107 17-Stage Oscillator/Divider MMB3108 Digital Alarm Clock. MMB4C48 BCD-to-7-Segment Decoder MMS55104 PLL Frequency Synthesizer MMB5106 PLL Frequency Synthesizer MMB5108 PLL Frequency Synthesizer with Receive/Transmit Mode. MMS5110 PLL Frequency Synthesizer with Receive/Transmit Mode. MM55114 PLL Frequency Synthesizer MMS5116 PLL Freauency Synthesizer MM57100* TV Game Circuit (NTSC) with reference to MMS57105 TV Game Circuit (PAL) MMS7 103 Scientific Calculator Circuit M57 104 Scientific Calculator Circuit MM57109 Number Processing Unit MMB7123 Financial Calculator MMB57126 COPS Memory MM57135 Scientific Calculator ROM MMS7136 RPN Scientific Calculator Control ROM. MM57140 Controller Oriented Processor MMBB106 Direct Drive LED Watch, MMBB106 Digital Clock and TV Display Circuit MMS8115 Digitally Tuned, Ditect Drive, 6-Function LED Watch MM58117 LCD Wateh Circuit MM58118 LCD Watch Circuit MM58119 LCD Watch Circuit MMB8120 LCD Watch Circuit MMBB127 LCD Watch Circuit ‘MMI58128 LCD Watch Circuit M8129 LCD Watch Circuit MM5B130 LCD Watch Circuit MM58601 Two Time Zone LED Watch Circuit MMB58801 Two Time Zone LED Watch Circuit MM74C48 BCD-to-7-Segment Decoder MMB4C915 7-Segment-to-BCD Converter MM54C922 16-Key Encoder MM54C923 20-Key Encoder MM74C915 7-Segment-to. BCD Converter MM74C922 16-Key Encoder MM74C923 20-Key Encoder NSA 1100 Series 0,100 Inch 9-Digit LED Display NSA 1298 0.110 Inch 9.Digit LED Display NSA 5120 1/8 Inch 12-Digit LED Display NSA 6140 1/8 Inch 14-Digit LED Display NSB 5917 0.5 Inch 5-Digit Numeric Display NSB 5921 0.5 Inch 5-Digit Numeric Display NSB 6922 0.6 Inch 5-Digit Numeric Display. NSN Series Multi:Digit LED Numeric Series 4-50 4-32 2:20 1-62 11.42 616 6-16 6-20 6.20 616 616 4:37 8.123 8.132 9-39 Brat 9.40 8.153 8.157 9.46 727 453 732 7-40 7.40 7-40 7.40 747 747 7.47 7.47 76 76 11.42 11-46, 10:16 1016 11-46 10-16 10-16 122 126 128 12-10 12.12 12.412 12.12 fataMM5309, MM5311, MM5312, MM5313, MM5314, MM5315 A MM5309, MM5311, MM5312, MM5313, MM5314, MM5315 digital clocks general description These digital clocks are monolithic MOS integrated circuits utilizing P-channel jow-threshold, enhancement mode and ion implanted. depletion mode devices. The eviews provide alt the logic required to build several types of clocks. Two display modes (4 or 6-digits) facilitate end-product designs of varied sophistication. ‘The circuits interface to LED and gas discharge displays with minimal additional components, and require only a single power supply. The timekeeping function ‘operates from either a 50 or 60 Hz input, and the dis: play format may be either 12 hours (with leading-zer0 blanking) or 24 hours. Outputs consist of multiplexed display drives (BCD and 7-sogment} and digit enables. The devices operate over a power supply range of 11V to 19V and do not require a regulated supply. These clocks are packaged in dual-in-ine packages, features © 50 oF 60 Hz operation = 120r 24-hour display format Clocks For editions application information, see AN-143 2 the end of this section, © Leading-zer0 blanking {12-hour format) © Psogment outputs © Single power supply ‘© Fast and slow set controls = Internal multiplex oscillator © For features of individual clocks, see Table | applications © Desk clocks = Automobile ctocks = Industrial clocks Interval Timers rast reatanes | wsses” [omen nao [oar [ aie | ane BB one x x x x r oe q x x x Te Oo x x Pt x 7 connection diagrams (Dval-n-Line Pckooes) a [ [en (Order Number MNIE30ON ‘See Package 23 (Order Nuenbar MIMSSTIN, ‘See Package 23absolute maximum ratings Voltage at Any Pin Operating Temperature Storage Temperature Lead Temperature (Soldaring, 10 seconds) electrical characteristics ta within operating range, Vs: Vsg + 0.3 10 Vgg-20V =28°C 10 #70°C 65°C to +150°C 300°C 1V to 19V, Vp = OV, unless otherwise specified, PARAMETER CONDITIONS min [vp | max units Power Supely Voltage Vss (Vp = Ov) 1" 13 v Power Supply Current gs = 14V, (No Output Loads) 10 ma 50/60 He Input Frequency de | so0r60 | 60K He 50/60 He Input Voltage Logical High Level vss-1 | vss Vss v Logical Low Leve! von | von | vss-10 v Multiplex Frequency Determined by External R&C o100 | 10 60 kuz A Logie Inputs Driven by External Timebase a 60 kite Logica! High Level Interoal Depletion Device to Veg vss-1 | vss | ss v Logica! Low Level voo | voo } vss-10 v BED and 7-Segment Outputs Logical High Level Loaded 2k®2 0 Vpo 20 20, | mA source Logical Low Level 0.01 | ma source Digital Enable Outputs Logical High Love 03 |mAsource Losicat Low Level Loaded 1009 to Vsg 50 25 | mAsink Connection diagrams (Continued) Duat-in-Line Packages (Top Views) = [sor ne SER [se Cndee Norte MON Cvder Number MEN ‘te Package 22 ‘soe Pachoge 23, swcaie matien (Order Namibar MASTS ‘Sea Package 22 ‘See Packago 23 SLESWW ‘PLESIW ‘cLESW B “ZLESIAIN ‘LES ‘60ESWWMM5309, MM5311, MM5312, MM5313, MM5314, MM5315 functional description A block diagram of the MM5309 digital clock is shown in Figure 1. NMS311, MM5312, MMS313, MM5314 and MIM§315 clocks are bonding options of MM5309 clock. Table | shows the pin-outs for these clocks, 50 or 60 Hz Input: This input is applied to a Schmitt Trigger shaping circuit which provides approximately BV of hysteresis and allows using a filtered sinewave input. A simple RC filter such as shown in Figure 10 should be used to remove possible line voltage transients that could either cause the clock to gain time or damage ‘the device. The shaper output drives a counter chain which performs the timekeeping function, 50 or 60 Hz Select Input: This input programs the prescale counter to divide by either 50 or 60 to obtain a 1 Hz timebase. The counter is programmed for 60 Hz operation by connecting this input to Vp. An internal depletion device is common to this pin; simply leaving this input unconnected programs the clock for 50 Hz operation. As shown in Figure 7, the prescale counter provides both 1 Hz and 10 Hz signals, which can be brought out as bonding options ‘Time Setting Inputs: Both fast and slow setting inputs, a well as hold input, are provided. internal depletion devices provide the normal timekeeping function ‘Switching any of these inputs (one at a time} to VDD results in the desired time setting function. The three gates in the counter chain (Figure 1) are used for setting time, During normal operation, gate A connects the shaper output to @ prescale counter {-50 or #60); gates B and C cascade the remaining counters Gate A is used to inhibit the input to the counters for the duration of slow, fast or hold time-setting input activity. Gate B is used to connect the shaper output directly to a seconds counter (:60}, the condition for slow advance. Likewise, gate C connects the shaper output directly to a minutes counter (60) for fast advance, Fast set then, advances hours information at one hour per second and slow set advances minutes information at one minute per second. 12 or 24-Hour Select Input: This input is used to pro gram the hours counter to divide by either 12 or 24, thereby providing the desired display format. The WZhour display format is setected by connecting this, input te Vp: leaving the input unconnected {internal depletion device} selects the 24-hour format. Output Multiplexer Operation: The seconds, minutes, and hours counters continuously reflect the time of day. ‘Outputs from each counter {indicative of both units and tens of seconds, minutes, and hours) are. time division multiplexed to provide digitsequential access to the time data, Thus, instead of requiring 42 leads to interconnect 9 G-digit clock and its display (7 segments per digit), only 13 output leads are required. The multi- plexer is. addressed by a multiplex divider decoder, which is driven by a multiplex oscillator, The oscitlator and external timing components set the frequency of the multiplexing function and, as controlled by the 4 or G-ligit select input, the divider determines whether data will be output for 4 or 6 digits, A zero-blanking circuit suppresses the zero that would otherwise sometimes appear in the tens-of-hours display; blanking is effective ‘only in the 12hour format. The multiplexer addresses also become the display digit-enable outputs. The multi plexer outputs are applied to a decoder which is used to address a programmable (code converting) ROM. This ROM generates the final ourput codes, i., BCO and 7-segment, The sequential output order is from digit 6 (unit seconds) through digit 1 {tens of hours}. Multiplex Timing Input: The multiplex oscillator is, shown in Figure 2. Adding an external resistor and capacitor to this circuit via the multiplex timing input {as shown in Figure 4a) produces a relaxation oscillator The waveform at this input is 2 quas-sawtooth that is squared by the shaping action of the Schmitt Trigger in Figure 2. Figure 3 provides guidelines for selecting the external components relative to desired multiplex. frequency Figure 4 also illustrates two methods of synchronizing the multiplex oscillator 10 an external timebase. The external RC timing components may be omitted and this input may be driven by an extemal timebase; the required logic levels are the same as 50 or 60 He input, Reset: Applying VOD to this input resets the counters, to 0:00:00,00 in 12:hour format and 00:00:00.0 in 24-hour formats leaving the input unconnected (internal depletion pull-up) selects normal operation. 4 oF 6-Digit Select Input: Like the other control inputs, this input is provided with an internal depletion pull-up device. With no input connection the clock outputs data for a 4-digit display. Applying Vpp to this input pro: vides a 6-digit display. Output Enable Input: With this pin unconnected the BCD and 7-segment outputs are enabled (via an internal depletion pull-up). Switching Vpp 10 this input inhibits these outputs. (Not applicable to MM6312, MM6313, and MM5315 clocks.) Output Circuits: Figure 5a illustrates the circuit used for the BCD and 7-seament outputs. Figure 5b shows the digit enable output circuit. Figure 6 illustrates interfacing these outputs to standard and low power TTL, Figures 7 and & illustrate methods of interfacing these outputs to common anode and common cathode LED displays, respectively. A method of interfacing these clocks to gas discharge display tubes is shown in Figure 9. When driving gas discharge displays which enclose more than one digit in a common gas envelope, it is macessary to inhibit the seqment drive voltage(s) during inter-digit transitions, Figure 9 also illustrates a method of generating a voltage for application to the output enable input to accomplish the required inter digit blanking,functional description (continued) ———= “eo teens Ld ve (oS La EH HEHE ye een en ooreurs Paocaaw. ‘outers FIGURE 1. MM5309 Digital Clock Biock Diagram soi rs cuitoron so a com vant i 6 cerranes ust anth 226 Iw 4, A FIGURE 3. Multiplex Timing Component Selection Guide ih-—-——0< F-- 4 NI ri I Dotted components added to shaping is Gireuit to form multiplex oxelror FIGURE 2. 50/60 He Shaping Ciruit/Multiplex Oscillator SLES ‘PLESWIW ‘ELESWW B@ ‘ZLEGININ 'LLESININ ‘6OESWIMM5309, MM5311. MM5312, MM5313, MM5314, MM5315 functional description (Continvea) au roan. | Yoo FIGURE 4a, Relaxation Oxcillator cL i || rane TY eae “LY Ei oy ei | sn > FIGURE 4b, External Time Base L— Note, Free running frequency should be set to run slightly lower than system frequency lover temperature, Externa} time base may be input oF output, + R=100k, Dscowent RCD 08 tyes iorewonan FIGURE Sa FIGURE 5. Output Circuits FIGURE 4e, External Clack. art exaave FIGURE 5bel functional description (continued) MOS to Low Power TTL Interface For Vss=5, Vop = 12, R = 10k For Vgg = 10:0 17V, Vpp = Gnd, R ~ 3k evagt| ~L- ct Breau. A) Vs5~Voo Ve 06v feel Wiig) Where Ry a in ket Ana Ve * tonmerd drop of LEO O8V = voltage drop of tansatore N= numero gt in dalay Ip ~ required average LED current MOS to TTL Interface For Vss = 8, Vor Note, Digit select wil drive TTL avaetiy when 5, ~12 supplies ae used ing TTL Jf sun as uswan aS ie ee iss Voo)/2 Ve 1.5 Aue Nile) Where Ry isin kf And Vp = forward drop of LED 0.8 = vaitage drop of transistors N= number of digits i disolay Ip = required average LEO current “Transistors may be replaced by OM7S491, OM75492, MEST, DMEBES or equivalent segmentiigit drovers FIGURE 7. Interfacing Common Anode LED Displays FIGURE 8, Interfacing Common Cathode LED Displays 7 SLESWW ‘PLES ‘ELESWW Bm ‘CLES ‘LESWW ‘6OESWIWMM5309, MM5311, MM5312, MM5313, MM5314, MM5315 functional description (continued) dee |[ 2 ™ _ FIGURE 9. Interface Panaplox I1* Neon Display Tubs “TM of Burroughs Corp. wea] ees FIGURE 10, M5309 Driving Gas Discharge Display, Typical ApplicationsMM5316 digital alarm clock general description Clocks ess doves, Tepovies all he oie required to bu severat_T_2toUr alarm eting Power supply. The timekeeping function operates @ Elimination of illegal time display at turn on ing and AM/PM indication) or 24 hours. Outputs ‘© Qminute snooze alarm consist of display drives, sleep (e.g., timed radio turn © Presettable $9-minute sleep timer provided to inform the user that incorrect time is applications The MM5316 is packaged in a 40-lead dual-in-line Goce (idle 1 ‘Stopwatches features © Portable clocks © 50 or 60 Hz operation = Photography timers © Low power dissipation (36 mW at 9V) Appliance timers block and connection diagrams soma F He m| ros - “oo | i eee Ficune 1, (Onder Number MMS316N ‘See Package 24 FicurE 2. 13 SLESWINMM5316 absolute maximum ratings Voltage at Any Pin Operating Ternperature Storage Temperature Lead Temperature (Soldering, 10 seconds) electrical characteristics Ta within operating range, Vg3 21V to #29V, Yop Vsg + 0.3 to Vgg ~ 30V 28°C to +70°C 65°C to +150°C 300°C NV, unless otherwise specified PARAMETER CONDITIONS min | tye | Max | UNITS Power Supply Voltage Vgs (Vop = OV) a 28 v Power Supply Current No Output Loads Vgg = 8V 4 mA Vgs = 29V 5 mA Counter Operation Voltage 8 29 v 50/60 Hz Input Frequency Voltage de | sooreo| 10k He LLosieal High Level vss-1 | vss. Vss v Losieal Low Level vopn | Yoo | VYoo*1 v Blanking Input Voltage Lovical High Level Vss-1.5 | Ves Vss v Logical Low Level voo | Yoo | Vss-4 y All Other input Voltages Losical High Levet vss-1 | Vss Vss v Losical Low Level Interoal Depletion Device to Vp, voo | voo | vootz v Power Failure Detect Voltage (gg Voltage! 10 20 Output Currents, 1 Hz Display Vgg = 21 10 20V, Output Common = Vsg Logical High Levet 1500 uA Logical Love Level, Leakage 1 BA 10's of Hours {b & €), 10° of Minutes (ead Logical High Levet Vou = Vss - 2V 1000 HA Losical Low Level, Leakage Vou=Vop 1 yA All Other Display, Alarm and Steep Outputs Logical High Level Vou 500 uA LLosical Low Level, Leakage Vou= Yoo 1 uA 110functional description A block diagram of the MM5316 digital alarm clock is shown in Figure 7. The various display modes provided by this clock are listed in Table |, The functions of the setting controls are listed in Table Hl. Figure 2 is a connection diagram, The following discussions are based on Figure 1 50 or 60 Hz Input (pin 35): A shaping circuit (Figure 3) is provided to square the 50 or 60 Hz input, This circuit allows use of a filtered sinewave input. The circuit is a Schmitt Trigger that is designed to provide about 6V of hysteresis. A simple RC filter, such as shown in Figure 6, should be used to remove possible line-voltage transients that could either cause the clock to gain time or damage the device. The shaper output drives @ counter chain which performs the timekeeping function 50 or 60 Hz Select Input (pin 36): A programmable prescale counter divides the input line frequency by either 50 oF 60 to obtain a 1 Hz time base. This counter is programmed to divide by 60 simply by leaving pin 36 unconnected; pull-down to Vig is provided by an internal depletion device, Operation at 50 H2 is pro: grammed by connecting pin 36 to Vsg, Display Mode Select Inputs (pins 30-32): Inthe absence of any of these three inputs, the display drivers Present time-of-day information to the appropriate display digits. Lnternal pull-down depletion devices allow use of simple SPST switches to select the display mode, If more than one mode is selected, the priorities are as oted in Table I. Alternate disolay modes are selected by applying Vgg to the appropriate pin. As shown in Figure 1 the code converters receive time, seconds, alatm and sleep information from appropriate points in the clock circuitry. The display mode select inputs control the gating of the desired data to the code converter inputs and ultimately (via outout drivers) to the display digits, ‘Time Setting Inputs (pins 33 and 34): Both fast and slow setting inputs are provided. These inputs are applied either singly oF in combination to obtain the control functions listed in Table It. Again, internal pull-down depletion devices are provided; application of Vgg to these pins effects the control functions, Note that the control functions proper are dependent on the Selected display mode, For example, a hold:-time control function is obtained by selecting seconds display and actuating the slow set input. As another example, the Clock time may be reset to 12:00:00 AM, in the 12-hour format (00:00:00 in the 24-hour format, by selecting seconds display anc actuating both slow and fast set inputs Blanking Contro! Input (pin 37): Connecting this Schmitt Trigger input to VoD places all display drivers non-conducting, high-impedance state, thereby inhibiting the display, (see Figures 3 and 4), Conversely, \Vsg applied to this input enables the display. Output Common Source Connection (pin 23): All display output drivers are opendrain devices with all sources common to pin 23 (Figure 4), When using fluorescent tube displays, Vgs or a display brightness contro! voltage is permanently connected to this pin, Since the brightness of a fluorescent tube display is dependent on the anode (segment) voltage, applying @ variable voltage to pin 23 results in a display brightness control. This control is shown in Figure 6. 12 oF 24-Hour Select Input (pin 38): By leaving this pin unconnected, the outputs for the most-significant display digit (10's of hours) are programmed to provide ‘2 12hour display format. An internal depletion pull down device is again provided. Connecting this pin to Vsg programs the 24-hour display format. Seg- ‘ment connections for 10°s of hours in 2&hour mode are shown in Figure 5b. Power Fail Indication: If the power to the integrated Circuit drops indicating a momentary ac power failure and possible loss of clock, the power fail latch is set The power failure indication consists of a flashing of the AM or PM indicator at a 1 Hz rate. A fast or slow set input resets an internal power failure latch and returns the display 10 normal, In the 24-hour format, the power failure indication consists of flashing segments “e"" and "#" for times less than 10 hours, and of a flashing segment “c"’ for times equal to or greater than 10 hours but less than 20 hours; and a flashing segment “g” for times equal to or greater than 20 hours Alarm Operation and Output (pin 25): The alarm comparator (Figure 1) senses coincidence between the alarm counters (the alarm setting) and the time counters (real time). The comparator output is used to set a latch in the alarm and sleep circuits. The latch output enables the alarm output driver (Figure 4), the MM5316 output that is used to control the external alarm sound gener ator. The alarm latch remains set for 89 minutes, during which the slarm will therefore sound if the latch output is not temporarily inhibited by another latch set by the snooze alarm input (pia 24) ar reset by the alarm “OFF” input (gin 26}. If power fail occurs and power comes back up, the alarm output will be in high impedance state Snooze Alarm Input (pin 24): Momentarily connecting Pin 24 to Vsg inhibits the alarm output for between 8 and 9 minutes, after which the alarm will again be sounded. This ‘input is pulled-down to Vop by an internal depletion device. The snooze alarm feature may be repeatedly used during the 59 minutes in which the alarm iatch remains set. Alarm “OFF” Input (pin 26): Momentarily connecting pin 26 to Vsg resets the alarm latch and thereby silences the alarm. This input is also returned to Vop by an internal depletion device. The momentary alarm “OFF” input also readies the alarm latch for the next compara tor output, and the alarm will automatically sound again in 24 hours (or at a new alarm setting). If it is desired to silence the alarm for a day or more, the alarm “OF F”* input should remain at Vs. Sleep Timer and Output (pin 27): The sleep output at pin 27 can be used to turn off a radio after a SLESMM5316 functional description (continued) desired time interval of up t0 69 minutes. The time interval is chosen by selecting the sleep display mode (Table 1) and setting the desired time interval (Table 11), ‘This automatically results in a currentsource output via pin 27, which can be used to turn on a radio (or other appliance). When the sleep counter, which counts downwards, reaches 00 minutes, a latch is reset Yoo land the sleep output current drive is removed, thereby turning off the radio. The turn off may also be manually controlled (at any time in the countdown) by 2 momentary Vss connection to the snooze input (pin 24), The output circuitry is the same as the other ‘outputs (Figure 4) sao wz INPUT OR BLANKING save He Neu OurPuT on BLANKING SIGWAL “Ettectively HIGH Ve Mss FIGURE 3, 50/60 He or Blanking Input Shaping Circuit ‘OUTPUT COMMON SOURCE BUS (PIN 23) aioaray BLANKING (FROM oureut SHAPER) (OPEN ORAIN} Vs * Alarm and sleep output sources are connected to Vsg blanking is not applied 10 these outputs FIGURE 4. Output Circuit pina Pint Piao iN? THe Att PM be pina pn pin2 Pu AM NC bac oa (a) 12.Hour Display Format 1b) 26-Hour Display Format FIGURE 5. Wiring Ten’s-of-Hours Digit 12functional description (continues) ‘TABLE 1, MMS316 Display Modes “SELECTED DSstAy ObE DIGIT NO. 1 DIGIT NO. 2 DIGIT NO. 3 DIGIT NO. 4 Time Display 10's of Hours & AM/PM Hours 10's of Minutes Minutes Seconds Display Blanked Minutes 10's of Seconds Seconds Alarm Display 10's of Hours & AMYPM Hours 10's of Minutes Minutes Sleep Display Blanked Blanked 10's of Minutes Minutes “MF more than ane display made input is applied, the display priorities ae in the order of Sleep (overrides all others) Alarm, Seconds, Time {na other mode slected) TABLE II, MMS316 Setting Control Functions SELECTED ‘CONTROL, 7 DISPLAY MODE INPUT a “Time Slow Minutes Advance at 2 Hz Rate Fast Minutes Advance at 60 Hz Rate Born Minutes Advance at 60 Hz Rate Alarm Stow Alarm Minutes Advance at 2 Ho Rate i Fast Alarm Minutes Advance at 60 Hz Rate Both Alarm Resets to 12:00 AM (12:hour format) Both Alaimn Resets t0 00 00 (24-hour formatl Seconds Slow Input to Entire Time Counter is inhibited (Hold! Fast Seconds and 10's of Seconds Reset to Zero Without a Canty to Minut Both Time Resets to 1200-00 AM (12-hour format) Both Time Resets to 00:00:00 (24-hour format) Sleep Slow Substracts Count at 2. He Fast Substracts Count at 60 Hz Born Substracts Count at 60 Hz “When setting time sleep minutes will decrement at rate of time counter, until the slep counter reaches OD minutes (sleep countor wil not recycle). typical application Figure 6 is a schernatic diagram of a general purpose alarm clock using the MMS5316 and a fluorescent tube display. | ee ea ea eae Abs eee i ra ce. FIGURE 6. Schematic 13 SLESWINMM5370. MM5371 MM5370, MM5371 digital alarm clocks general description The MM5370 and MM5371° digital alarm clocks are monolithic MOS integrated circuits utilizing P-channel low-threshold, enhancement mode and ion-implanted depletion mode devices, They provide all the logic required to build several types of clocks and timers, Three display modes (time, alarm and steep) are pro vided to optimize circuit utility. The circuits interface simply with 7-segment gas discharge displays. The ‘timekeeping function operates from either a 60 Hz (MMS370} or 80 Hz (MM5371) input, and the display format may be either 12 hours (with leading-zero blanking and AM/PM indication) or 24 hours. Outputs consist of display drives, alarm enable and sleep (c.0., timed radio turn off). Power failure indication is provided to inform the user that incorrect time is being displayed, Setting the time cancels this indication, ‘These clocks are packaged in 28-pin dual-in-ine packages, features Single power supply Low power dissipation 12 or 24-hour display format Colon drive output connection diagram applications Dusl-tn-Line Package Clocks AM/PM drive output in 12-hour format Leading-zero blanking in 12-hour format 24-hour alarm setting All counters are resettable Fast and slow set controls Power fail indication Blinking colon—12-hour or 24-hour mode Blinking AM/PM indicators—12-hour only Brightness control capability Simple interface to gas discharge display Presettable 59-minute sleep timer S:minute snooze timer Alarm clocks Desk clocks Clock/radios Automobile clocks Industrial clocks Appliance timers savozt ‘nna van ke, ane on0uRS | reir | vue iE ede ane a sunutes au" SLEEP. ES minutes oureut A he vss ‘ , ss vp : sucer | 2, der Number MMS37ON oscar —] mse mmucrncexeo orm N Mw suse _ a an, }isconent See Package 23 wae Fee [Sai neser | a sow 1} fue a rast fe te une | coun rocavencv mrt 4] ound reaeyoun are sect ovine wocrmex 1 ts eniuruess rane west JF conraoc nour ‘ro view aabsolute maximum ratings Vottage at Any Pin Voltage at Any Display Output Pin Operating Temperature Storage Temperature Lead Temperature (Soldering, 10 seconds) Vss + 0.3V to Vg - 29V \Vgs + 0.3V to Vsg ~ 88V 25°C t0 +70°C 65°C 10 +150°C 300°C electrical characteristics 1, within operating range, Vgg ~ OV. VoD = -29V unless otherwise specified. PARAMETER CONDITIONS min [tye | max | _ units Power Supply Voltage Functioning Clock No Output Loads -8.0 25 ~29 v Outputs Driving Display -21 29 v Power Supply Current No Output Loads, (See “Power 50 mA Supply” Section) 60 Hz (or 50 Hz) Input Frequency MMs370 oc 30k He wnsa7t dc 30k He 60 Hz (or 50 Hz) Input Voltage Logical High Level vss-10 | vsg | Vgg v Logical Low Level voo | voo | voo+ v Brightness Control Voltage Logical High Level ves-20 | vss | Veg v Logical Low Level voo | Yoo | Yss-40 v All Other Input Voitages Logical High Level vss-10 | vss | Vss v Logical Low Level Internal Depletion Load to Vop voo | voo | Voo+2.0} v Multiptex Frequency Determined by Ext, RC 500 60% He Driven by Ext, Time Base ec 60k he Power Failure Detect Voltage (pp Voltage) 3.0 “80 v Output Currents Vp =~21V t0 -29V, Vgg * 0V Digit Anode Outputs Logica High Level, ("ON") VoH = Vss - 8V 80 mA Logical Low Level, ("OFF") | VoL = Vgg — 45 40 HA ‘Segment Cathode Ourauts Logical High Level, ("OFF") | Vou = Vgg ~ SV 20 mA Logical Low Level, ("ON") Vou = Vgs ~ 48V 10 uA ‘Alarm and Sleep Outputs Logical Migh Level, ("ON") Vou = Vss - 2V 16 mA Logical Low Level, (“OFF”) | You = Von +2V 10 HA functional description A block diagram of the MM5370 and MM5371 clocks is. shown in Figure 1. Tne various display modes provided by these clocks are listed in Table |. The functions of the controls are listed in Table I, A connection diagram for these devices is shown on page 1. Unless indicated other wise, the following ciscussions ar2 based on Figure 1, Power Supply: Even though these clocks da not require @ regulated supply, and operate over a wide voltage range, certain factors should be remembered, Power supply voltages between -BV and —21V will provide all functions of the clocks (proper counting, ete.) except output drive capabilities. In order to ensure proper ‘ourput levels and breakdown voltages it is necessary to provide supply voltages between —21V and ~28V. At some point between —7V and —3V, the power fail latch becomes “set”. All counters will then hold their count at least 0.5V below this point, This ensures power failure indication before any count is lost. For oroper power failure indication, power supply rise time should not exceed 10 Vims, since faster rise times may be faster than propagation delays within the latch circuitry. LLESINW ‘OLESWWMM5370, MM5371 functional description (continued) Line Frequency Input (pin 12): A shaping circuit is provided to square the 60 Hz (MMS370) or 50 Hz (MM5371) input. This circuit allows use of a sinewave input. The Schmitt Trigger shaper (Figure 2) is designed to provide approximately BV of hysteresis. A simple RC. filter, such 3s shown in Figure 8, should be used to remove possible line-voltage transients that could cause the clock to gain time or damage the device. The shaper output drives a counter chain which performs the time- keeping function. A prescale counter divides the tine input frequency to obtain a 1 pps timebase. Display Mode Select Inputs (pins 7 and 8): In the absence of either of these inputs, the display drivers ‘urput time-of.day information to the display. Internal pull-down (to Vp) depletion loads allow use of simple SPST switches for connecting these inputs to Vss, thereby selecting alternate display modes, If more than fone mode is simultaneously selected, the priorities are are noted in Table |. As shown in Figure 1 the multi plexed code converter receives time, alarm and sleep information from appropriate points in the clock circuitry. The display mode select inputs control the gating of the desired data to the multiplexed code converter inputs and ultimately (via output drivers) 10 the display. Time Setting Inputs (pins 10 and 11): Both fast and slow setting inputs are provided. These inputs are applied either singly or in combination to obtain the control functions listed in Table Hl. Again, internal pulldown depletion loads are provided; application of Vgg to these pins effects the control functions. Note that the control functions proper are determined by the selected display mode, An optional hole-time control funetion can be obtained as shown in Figure 8. Reset Input (pin 9): Applying Vgg to this input results in resetting the timekeeping function of the clock; a pulltown depletion load is provided at this input Time is reset t0 12:00 AM in the 12-hour format ‘oF 00:00 in the 24-hour format. See Table II 12 or 24-Hour Select Input {pin 13}: By leaving this pin unconnected, the clock is programmed to provide 2 12-hour display format. This format provides for zero:blanking the most significant display digit (ten’s of hours}. Aa internal pull-down depletion load is again provided; connecting this pin to Vsg programs the 24-hour display formar. (See Figure 8) Output Multiplexer Operation: Depending upon the selected display mode (see Table 1), outputs from the appropriate internal counter are time division multi plexed to provide digitsequential access to the data Thus, instead of requiring 28 leads to interconnect a 4edigit clock and its display (7-segments per digit), only 11 output leads are required. Note that the MM5370 and MMS371 actually provide 13 outputs (4-aigit anode drive outputs plus 9 “segment” cathode drive outputs). The two additional “segment” drives are provided to accommodate displays which feature a colon and/or AM/PM indication. (See sections on pin 16 and pin 17). The multiplexed code converter and output drivers are controlled by @ multiplex oscillator The oscillator and external timing components set the frequency of the multiplexing function. Each digit anode is sequentially enabled for a time equal to the period of one cycle of the multiplex oscillator frequency. When driving gas discharge displays which enclose more than one digit in a common gas envelope, itis necessary to either (1) inhibit the segment drive voltagels) for @ short time during inter-digit transitions, or (2) avoid physically adjacent inter-digit transitions. The MMS370 and MMB371 clocks utilize an imerlaced output sequence 10 eliminate the need for inter-digit blanking circuitry and to prevent display arcing problems, The digit sequence is: (1) digit no, 1 (ton’s of hourst, (2) digit no. 3 (ten's of minutes), (3) blank for one digit time, (4) digit no, 2 {unit hours), (5) digit no. 4 {unit min utes), (6) blank for one digit time, etc, The two blanking intervals are provided to recharge level-translating capacitors located in the display segment drive lines (soe Figure 8). Both segment data and digit enables are blanked. Figure 3 is a timing diagram which illustrates output timing, Multiplex Timing Input (pin 14): The multiplex oscil lator is shown in Figure 4, Adding an external resistor and capacitor to this circuit via the multiplex timing input produces a relaxation oscillator. The waveform at this input is a quasi-sawtooth that is squared by the shaping action of the Schmitt Trigger in Figure 4. Figure 5 provides guidelines for selecting the external com ponents relative to the desired multiplex frequency. Figure 6 illustrates a method of synchronizing o driving the multiplex oscillator with an external timebase. The external RC timing components may be omitted and this input driven by an external timebase; the required logic levels are the same as the 60 Hz or 50 Hz input. Output Circuits: All display output drivers are open drain devices with sources common to Vsg {pin 5), see Figure 7. Figure 8 illustrates interfacing the clock outputs and a gas discharge display. Brightness Control Input (pin 15): Since display bright: ness is a function of cathode segment current, a capa: bility of interrupting this current for a variable per- centage of the digit interval results in a_ brightness control. Connecting this Schmitt Trigger input (see Figure 2) to Vpp places all cathode segment drive voltages at the high level, thereby inhibiting the display. Conversely, Vsg applied to this input enables the cathode segment drives, The Schmitt Trigger shaper provides approximately 1V of hysteresis, which facili tates using a waveform such as asawtooth with a variable slope or variable de companent) to effect the shaper output duty cycle and, therefore, the display brightness. The control waveform should be derived from the multi plex frequency; a circuit is included in Figure 8. ‘Alarm Operation and Output (pin 2): An alarm com- parator (see Figure 1) senses coincidence between the alarm counters (the alarm setting) and the time counters, (real time]. The comparator output is used to set a latch in the alarm and sleep circuits. This latch enables the alarm output driver (see Figure 7), the output of which is used to control the external alarm sound generator. The alarm latch remains set for 69 minutes, during which the alarm will sound if the latch output is notfunctional description (continued) temporarily inhibited by another latch set by the snooze input (pin 1) oF reset by the alarm “OFF” input (pin 3) ‘Alarm time setting and resetting are outlined in Table Il. When initially powered, alarm is in “OFF” state. Alarm “OFF” Input (pin 3): Momentarily connecting this pin to Vsg resets the alarm latch and thereby silences the alarm, This input is also returned to Vp. by an internal depletion load. The momentary alarm "OFF" input also readies the alarm latch for the next alarm comparator output; the alarm will sound again in 24 hours lor at a new alarm setting), If it is desired to silence the alarm for @ day or more, the alarm input should remain at Vs. Snooze Timer Input (pin 1): Momentarily connecting this pin to Vsg inhibits the alarm output for between 8 and 9 minutes, after which the alarm will again be sounded. This input is pulled to Vpp by an internal depletion load. The snooze feature may be repeatedly used during the 59 minutes in which the alarm latch remains set. Sleep Timer and Output (pin 4): The sleep output at pin 4 can be used to tum off a radio (or other appliance) after a cesired time interval of up to 59 minutes. The time interval is chosen by selecting the vs ome "ine O_o} ene sleep display mode (see Table I) and setting the desired time interval (see Table II), This automatically results in 2 current-source output via pin 4 which can be used to turn on a radio. When the sleep counter, which ‘counts downwards, reaches 00 minutes a latch is reset and the sleep output drive current is removed, thereby turning off the radio. This turn off also may be manually controlled (at any time in the countdown} by a momen tary Vgg connection to the snooze input (pin 1). This input is also returned to Vp by a depletion load. The output circuitry is the st Figure 7), ne as the alarm output (see AM/PM Cathode Output (pin 16): Current with this writing, gas-discharge clock displays are available with two types of AM/PN indications, (1) AM and PM. indicators common to digits 3 and 4 respectively; and (2) @ PM only indication common to digit 1. Figure 3 illustrates an AM/PM cathode drive output that is com: patible with both display types. Note that this same ‘output also provides a non-blinking (steady) colon drive common to digit two. Power failure is shown by turning off this output at a 1 H2 rate, Colon Cathode Output (pin 17): As an optional indica tion of clock operation, some users may prefer to display a1 Hz activity. As shown in Figure 3, a cathode drive output is provided to facilitate a blinking colon water FT =—1/T J = [en FIGURE 1. MMS370 and MM5371 Digital Alarm Clock, Block Diagram v7 LLESINW ‘OLESWWWMM5370, MM5371 functional description (continues) ‘TABLE |, MM5370 and MMS371 Display Modes “SELECTED DepEAV NORE DIGIT NO.1 DIGIT NO. 2 DIGIT NO. 3 DIGIT NO. 4 Time 10's of Hours Unit Hours 10's of Minutes | Unit Minutes Alarm 10's of Hours Unit Hours 10's of Minutes | Unit Minutes Sleep Blanked** Blanked 10's of Minutes | Unit Minutes “1f move than one displey mod input is applied, the display priorities are inthe order of Sleep (overrides all others), Alarm, Seconds, Time ino other mode selected) =F segment is it in V2shour cisplay mode. This may be eliminated by using circuit shown in Figure 9 Table 11, M5370 and MMS371 Setting Control Functions, SELECTED CONTROL DISPLAY MODE INPUT eee Time Siow ‘Minutes Advance at 2 Hz Rate Fast Minutes Advance at 60 Hz Rate Both Minutes Advance at 60 Hz Rate Reset Time Resets to 12:00 AM (12-hour format} Reset Time Resets to 00:00 (24-hour format) Alarm Slow Alacm Minutes Advance at 2 Hz Rate Fast ‘Alarm Minutes Advance at 60 Hz Rate Both ‘Alarm Resets to 12:00 AM (12shour format) Both Alarm Resets £0 00:00 (24-hour format) Sleep Slow Subtracts Count at 2 Hz Rate Fast Subtracts Count at 60 Hz Rate Both Subtracts Count at 60 Hz Rate When setting time sleep minutes will leerement at rate of time counter, until the sleep counter reaches {00 minut (leep counter wil not recycle. me run OR saeco ine uontnsss O—P—] Heaven RirrowT FIGURE 2. 60 Hz (or 50 H2) Input (or Brightness Control Input) Shaping Cireuit 18functional description (continues) wea [7] r ood 7] aot | [To L 1 ir ett ™ oof egeaee” Ls eal telly FIGURE 3. Output Timing Diagram E owe “once 3 se 18 189F WOpF NWoD9 onF ae FIGURE 5. Multiptex Tir Selection Guide (Typical Only) Note 1: For syneheonizing, free canning period should be set to run alghily tonger than exter fal timobase over temperature Note 2: For driving, timing capocitor should be delete FIGURE 6. Synchronizing oF Driving Multiplex Oscillator 19 LLESWIW ‘OLESWWMM5370, MM5371 functional description (Continued) FIGURE 7. Output Circuits al ba \sam oF stoner a | rod rst ser | ro san eran - sa “Hh FIGURE 8. Recommended Application cc| - MM5375XxX series clocks general description MIMB375XX series clock is a monolithic MOS integrated circuit utilizing P-channel low threshold enhancement mode and ion-implanted depletion-mode devices. It Provides all the logic required to give a 4 or 6-digit 12-hour oF 24-hovr display from a 80 or 6O Hz input ‘An auxiliary counter allows various options, Available options have been listed under features. Power failure indication is provided to inform the user that incorrect time is being displayed. Setting time cancels this indica tion. MMS375XX is available in a 24-lead dual-in-ine epoxy package features Single power supply Low power dissipation Fast and slow set controls & All counters resettable "= Power failure indication Clocks Brightness control capability No illegal time display at turn-on Simple interface to gas discharge displays and LED's Internal digit multiplex oscillator Leading zero blanking Activity indicator 4 to 6digit operation Available options? application Alarm ctocks Desk clocks Auromobile clocks Industrial clocks Date clocks Minute timer clocks Seconds timer clocks connection diagram Dual In-Line Package available options tablet (Order Nursber MMS375XXN ‘See Package 22 F swuxase som ne “|. . : we [Be “Tone is 1/6 multiplex frequency 12 'S XXSLESWN seueMMS5375XX Series absolute maximum ratings Voltage at Any Pin Voltage at Any Display Output Pin Operating Temperature Storage Temperature Lead Temperature (Soldering, 10 seconds) electrical characteristics TA within operating range, Vss = OV. VDD Vgs + 0.3V to Vg ~ 30V \Vgg + 0.3V to Vgg ~ 55V 28°C 10 +70°C 65°C 10 +150°C. 300°C ~21V to -29V unless otherwise specified. PARAMETER CONDITIONS MIN tye | max UNITS Power Supply Voltage (Vp) Excluding Outputs 80 28 v Outputs Driving Displays 21 -29 v Power Supply Current Excluding Outputs 80 mA 60 Hz Input Frequency oc 50/60 | 30k He Logical High vss-1.0| Vs. Vss v Logical Low Voo | Yoo | Voptl.o v Brightness Control Range Determined by External R and C, 0 95, % % of Digit Time (Figure 2) Multiplex Oscillator Frequency Input | Determined by External R and C, oc 30 kHz (Figure 2) All Other Input Voltages Logical High Leve! vgs-1.0| sg Vss v Logical Low Level von | Voo | voo+20 v Power Failure Detect Voltage (Vp Voltage “10 80 v Output Current Vop = -21V to-29V Digit Select Outputs Vss = 0V Logical High, Source Von = Vss-5V 80 mA Logical Low, Leakage Vou = Vss~45V 40. vA ‘Segment Outputs Logical High, Source Vou = Vss~ 5V 20 ma, Logical Low, Leakage Vou = Vss~ 45V 10 uA Alarm Output Logical High, Source Vou = Vss~ 2V 18 mA Logical Low, Sink Vou=Voo + 2V 1 BA functional description A block diagram of the MMS375XX series of clocks is shown in Figure 1. The display modes are listed in Table |, The functions of the setting controls are listed in Table I, The following discussions are based on Figure 1 60 Hz Input (Pin 11): A shaping circuit is provided to square the 60 Hz input (60 Hz optional}. This circuit allows use of a filtered sinewave input. The circuit is @ ‘Schmitt trigger that is designed to provide about 3V of hysteresis. The shaper output drives @ counter chain which performs the timekeeping function, Time Setting Inputs (Pins 9 and 10}: The time setting control functions are affected by the application of Vsg to these 2 pins, which are internally pulled to the power 122, supply. Activating Fast Set (pin 10) causes the minutes counter to advance at a 60 He rate, thus clocking the hours counter at a rate of 1 hour per second. Slow Set {pin 8} advances the minutes counter at a rate of 2 min: Utes per second. Activating either Fast Set or Slow Set resets the seconds counter to zero, When Fast Set and Slow Set are activated simultaneously, all counters are reset to 12:00 p.m. and remain in that count until Slow Set is deactivated. The 2 time setting inputs affect only the counters that are displayed (either the timekeeping counters or the alarm counters} BSegment Test (Pin 24): For testing purposes, all B-segment output lines may be activated by connecting pin 24 (S10 digit output) to Vss.functional description (continued) Brightness Control {Pin 21): In LED applications, brightness of the cisplay may be varied by use of an external time constant, This time constant is used in the integrated circuit 10 control the pulse width or duty cycle of the G-digit enable outputs, (Figure 2), In gas discharge applications, connect as shown in Figure 3 Activity Indication (Pin 23}: When all 6 digits are being Used, it Is not necessary t0 blink the colon to indicate operation of the clock, because the seconds digits pro- vide this information. When only 4 digits are in use, the 81 digit (pin 23) may be connected to Vgg, In this case, the colon flashes at 1 Hz rate Multiplex Frequency (Pin 20): Applying an external time constant to this pin allows the multiplex frequency 10 be adjusted, (Figure 2) Power Failure Indication: If the power to the integrated circuit drops, indicating a momentary ac power failure and possible loss of clock, the AM or PM and colon indi cator will flash at a 2H2 rate. If power drops completely, the clock will reset itself (on resumption of power) ta a legal state, and the AM or PM and colon indicators will flash at a2 Hz rate, In addition to the flashing AM or PM and colon indicator, if a power failure occurs when alarm “OFF” (pin 7; is at Vp (logical 0”), the alarm output will be activated (non-activated optionall. A logical “1” (Vg) on pin 7 will deactivate the alarm signal B8-Segment Outputs (Pins 13-19 and 22): These outputs contain multiplexed information for the display of ‘Tsegment numerical readouts, The 8th segment is for the activation of AM/PM and colon(s) as included in the 988 dischatge displays for which these ouxputs are designed, 4-Digit Operation: Connect pin 23 10 Vgg. Digit Enable Outputs (Pin 1-4, 23 and 24): These outouts are used to select the 6 digits and are syn: ehronized with the segment outputs. If pin 23 is grounded, segment cutputs will be blanked during the scanning of the seconds digits Auxiliary Counter: Alarm Counter Option: In this option, the auxiliary counter is programmed and used as an alarm counter. Pin 6 serves as both alarm display and snooze input pin. Ala-m counter is displayed when pin 6 is held at Vgg. Alarm setting (Table 11) is done using alarm display, Fast Set {pin 10) and Slow Set (pin 9) If the alarm “OFF” input {pin 7) is open and whenever the real time matches with the alarm time, the alarm ‘comparator sets the alarm latch. This latch activates the alarm output {pin 8). The alarm will remain activated until the alarm "OFF" input is connected to Veg temporarily. This readies the alarm latch for next com. parison. To deactivate the alarm output for more than 24 hours, the alarm “OFF” input is held at Vgg for that long. When the alarm output is active, connecting pin 6 to Vgg will interrupt the alarm signal for 6 to 8 ‘minutes (snooze funetion) Auxiliary Counter: Date Counter Option: In this option, the auxiliary counter is programmed and used as 2 month and day counter. The day counter counts up to 31 days and increments the month counter, The day ‘counter rolls over from 31 to 1. The month counter counts up to 12 and rolls over to 1. The date counter can be displayed by connecting date display (pin 6) to Vg. The effects of Fast and Slow Set controls are shown in Table 11. In this option, do not use the alarm output (pin 8) Auxiliary Counter: Timer Option: In this option, the auxiliary counter is programmed and used as a timer counter. When the display pin 6 is connected to Vgg, the elapsed time from the previous setting is displayed The following sequence describes the use of the product as a minute (or seconds) timer. 1. Hold display pin 6 at Vss, 2. Hold both Fast and Siow Set controls at Vsg. Note: This will reset the timer counter to 12:00 in 12:hour mode and 00:00 in 24 hour mode. 3. Release both the Fast and Slow Set controls simul taneously, Note: The timer counter starts counting minutes {or seconds). 4, If itis requited to monitor elapsed time continuously, retain the display pin 6 at Vg. Otherwise, release pin 6. 5. Elapsed time can be displayed any time by holding pin 6 at Vg In this option, the clock can be used for up to 12 hours (12 minutes in seconds timer) of elapsed time in 12-hour mode and 24 hours (24 minutes in seconds timer) of elapsed time in 24-hour mode, The effect of Fast and Slow Set controls are listed in Table HI, In these options, do not use the alarm output (pin 8) Accuracy of Elapsed Time: Elapsed time ~ displayed time + 1 minute (or second} TABLE 1. Display Modes Second Tee iin | teat Mines | Unetts | 10% of Scone | UnteSeeonee | ‘ S8u2S XXSLESWINMM5375XX Series functional description (Continues) TABLE II, Setting Contro! Functions SELECTED DISPLAY | CONTROL Leto ae CONTROL FUNCTION Time Display Slow | Minutes advance at 2.0 He rate and seconds are held a a reset (00) condition Fast Minutes advance at 60 He rate and seconds are held ata reset (00) condition Both | Time resets to 12:00:00 prm. (12 hour mode) «r 00:00:00 (24-hour mode Alarm Display Siow | Alarm minutes advance at @ 2.0 He rate Fast Alarm minutes advance at a 60 H2 rate Both | Alarm resets to 12:00 p.m, (12+hour mode) 67 00:00 (24-hour mode) Date Display Slow | Date advances at 02.0 He rate Fast Date advances at 2 60 He rate Both | Date counter resets to 12:00 Minute Timer Display | Slow — | Minutes (auxiliary counter) advance at « 2.0 He cate Fast Minutes (auxiliary counter) advance ata 60 He rate Both | Timer counter resets to 12:00 {12-Hour mode! or 00:00 (24hour mode} Second Timor Display | Siow | Seconds {auxiliary counter) advance at @ 2.0 M2 rate Fast Seconds {auxiliary counter) advance at @ 60 He rate Both | Timer counter resets t0 12:00 (12-hour mode] 0 09:00 (24 hour mode) ~~ T oat fo ogo, LePage Pte Le as a a J J oe er a oe ; 4 i +] onion FIGURE 1. Block Diagram 124functional description (Continues) vo FIGURE 2 a ee ors =. sawsmana + Ye 00, + | Vgs = ov Vpp > -21V to-20v, = ‘Note. LED interface — common cathode LED's (NSN74R) can be interfaced with MMS375A8 by using two DM78491 segment drivers, one OM75492 digit driver, eight 16052, 1.0W resistors arse snd 10V power appv, vso—| FIGURE 3, Typical Application FIGURE 4. 50 oF 60 He Shaping Circuit 125 SeuesS XXSLESNWMM5375XX Series functional description (Continued mucrcex un INPUT oust no 6 vc wa. 6 ‘nt iar no 2 von OURS oucirna ww3aF sees var 40.3 is scout ae ef on oF uf eowonf Jenuonf Law [Lae FIGURE S. Output Timing Diagram 126ta MM5376XxX series clocks general description MMBE376XX series clock is a monolithic MOS integrated Circuit utilizing P channel, low threshold, enkancement- mode and ionimplanted depletionmode devices. It provides all the logic required to give a 4 or G-digit i2-hour or 24-hour display from a 50 or 6O He input. ‘An auxiliary counter allows various options, Available options have been listed under features. Power failure indication is provided to inform the user that incorrect time is being displayed. Setting time cancels this indica tion. MMB376XX is available in a 24-lead dual in-line epoxy package. features © 50 or 60 Hz operation Single power supply Low power dissipation All counters resettable Fast and slow set controls Power failure indication Leading zero blanking Activity indicator 4 10 B.digit operation ‘Available options! application Alarm clocks Desk clocks Automobile clocks Industrial clocks Two time zone clocks Date clocks Minute timer clocks Seconds timer clacks Brightness contro! capability No illegal time display at turn-on. Internal digit multiplex oscillator Clocks Simple interface to gas discharge displays and LED's connection diagram Dustin Line Package Ea ‘Note 1: 50 He inpet st nin 12 connect pin 13%0 Vp. Note 2: 60 Hz nput at pin 12 connect pin 13 10 Vs, (Order Number MMISSTXXN ‘See Package 23 available options table + ‘unitary Counter arm Co oi . Date Cav : em Oust mosamser2ne | «| {val wal « |e 5 Sag ln ves wal wal | wa “Tone is "16 multipiex frequency 127 Seu2S XX9LESWINMM5376XX Series absolute maximum ratings Voltage at Any Pin Voltage at Any Display Output Pin ‘Operating Temperature Storage Temperature Lead Temperature (Soldering, 10 seconds) electrical characteristics Ta within operating range, Vsg = OV. Yoo Vg #0.3V to Vg ~ 30V \Vgg + 0.3V to Vgs ~ 55V =26°C 10 +70°C 68°C to +150°C 300°C BV to ~29V unless otherwise specified. PARAMETER CONDITIONS MIN tye | MAX UNITS Power Supply Current Excluding Outputs 80 mA 50/60 Hz Input Frequency pe 60/60 | 10k Hz ‘Logic High Vgg-1.0 Vss v Logic Low voo | vss-15.0 v Brightness Controt Range % of Determined by External R and C o 95, % Digit Time (Figure 2) Multiplex Oscillator Frequency Input} Determined by External R and C oc 10 kHz (Figure 2) All Other Input Voltages Logic High Level vss-1.0] Vs Vss v Logic Low Levet vop | Vss-16.0 Power Failure Detect Voltage (vpp Voltage) 1.0 80 Output Current Levels Vpp = ~21V to-29V Digit Select Ourputs Vss* OV Logie High, Source Vou = ¥ss - 5.0V 80 mA Logic Low, Leakage VoL = Vss - 45V 40 uA Segment Outputs Logic High, Source Von = Vss - 5.0V 20 ma, Logic Low, Leakage VoL = Vss ~ 45V 10 BA Alarm Output Logie High, Source Vou = Vss - 2.0V 18 mA, Logic Low, Sink Vo = Vop + 2.0V 10 KA functional description A block diagram of the MMB376XX series of alarm clocks is shown in Figure 1. The two display modes are listed in Table |. The functions of the setting controls are listed in Table I. The following discussions are based on Figure 1 80 or 60 Hz Input (Pin 12): A shaping circuit is pro vided to square the 50 or 60 Hz input. This circuit allows use of a filtered sinewave input, The circuit is a Schmitt trigger that is designed to provide about 3.0V of hysteresis. The shaper output drives a counter chain which performs the timekeeping function, 50 or 60 Hz Select (Pin 13): 50 or 60 He input at pin 12 is selected by pin 13, 60 He operation is selected by connecting pin 13 to Vp (pin 6} and 60 Hz operation is selected by connecting pin 13 to Vgs (pin 14) 128functional description (continued) Time Setting inputs (Pins 10 and 11): The time setting control functions are affected by the application of Vsg to these two pins, which are internally pulled to the power supply. Activating Fast Set (pin 11) causes the minutes counter to advance at 50 or 60 Hz rate, thus clocking the hours counter at a rate of one hour per second. Slow Set (pin 10) advances the minutes counter at a rate of 2 minutes per second. Activating either Fast ‘Set or Siow Set resets the seconds counter to zero. When Fast Sot and Siow Set are activated simultaneously, all counters ate reset to 12:00 p.m. and remain in that count until Slow Set is deactivated. The two time setting inputs affect only the counters that are displayed (either the timekeeping counters or the alarm counters) 8-Segment Test (Pin 28): For tasting purposes, all 8: segment output lines may be ectivated by connecting pin 24 ($10 digit ouxput) to Vgg. Brightness Control (Pin 24): In LED applications, brightness of the display may be varied by use of an external time constant. This time constant is Used in the integrated circuit to control the pulse width or duty cycle of the G-digit enable outputs (Figure 2). In 925 discharge applications, connect as shown in Figure 3, Activity Indication (Pin 27): When all 6 digits are being used, it 1s not necessary to blin the calon to indicate operation of the clock, because the seconds digits provide this information. When only 4 digits are in use the St digit (pin 271 may be connected to Vss. In this cease, the colon flashes at a 1.0 Hz cate, Multiplex Frequency (Pin 23): Applying an external time constant t0 this pin allows the multiplex frequency 10 be adjusted, See Figure 2. Power Failure Indication: If the power to the integrated circuit drops, indicating a momentary ac power failure ‘and possible loss of clock. the AM or PM and colon indicator will flash at a 2.0 Hz rate, If power drops completely, the clock will rset itself (on resumption of ower) to a legal state, and the AM or PM and colon indicators will flash at 2 2.0 Hz rate. lo addition to the flashing AM or PM and colon indicator, if a power failure occurs when alarm “OFE" (pin 8) is at VDD (logic “01, the alarm output will be activated (non activated optional). A logic “1” (Vgg) on pin 8 will eactivate the alarm signal 8-Segment Outputs (Pins 15-17, 19-22 and 26): These ‘outputs contain multiplexed information for the display of 7-segment numerical readouts. The eighth segment is for the activation of AM/PM and colon(s) as included in the gas discharge displays for which these outputs are designed 4-Digit Operation: Connect pin 23 to Vss. Digit Enable Outputs (Pins 1-3, 5, 27 and 28): These outputs are used to select the 6 digits and are synehron ized with the segment outputs. If pin 27 is grounded, segment outputs will be blanked during the scanning of the seconds digits, Auxiliary Counter, Alarm Counter Option: In this option, the auxiliary counter Is programmed and used 2s {an alarm counter. Pin 7 serves as both alarm display ané snooze input pin. Alarm counter is displayed when pin 7 is held at Vgg. Alarm setting {Table 11) is done using Alarm Display, Fast Set (pin 11) and Slow Set {pin 10). If the alarm “OFF” input (pin 8} is open and whenever the real time matches with the alarm time, the alarm comparator sets the alarm latch. This latch activates the alarm output {pin 9}, The alarm will Femain activated until the alarm “OFF” input is con nected to Vgg temporarily. This readies the alarm latch for next comparison, To deactivate the alarm output for more than 24 hours, the alarm “OFF input is held at Vgg for that long, When the alarm output is active, connecting pin 7 to Vsg will interrupt the alarm signal for 6 to 8 minutes (snooze function. TABLE I. Display Modes ‘SELECTED pisrtay mooe | 2'GITNO.1 | oIGiTNo.2 | oIGITNO.3 | DIGITNO.4 | oIGITNO.s | BIGITNO.6 Time Dispay TOs of Hours | UnitsHours | 1058 Minutes | Unite Minutes | 10% a¥ Seconds | Units Seconds Alarm Display Ao'sot tours | UniteHours | to's of Minutes | Units Minotes | ° Date Display Month Month Date Date ° @ Minute Timer Display | 10%0f Hours | Units Hours | 10's of Minutes | Units Minutes | o e Second Timer Display | 10's of Minutes | Units Minutes | 10's af Seconds | Units Seconds | o 2 'S XX9OLESIIA 2 2 &MM5376XX Series functional description (continues) TAGLE 11, Setting Control Functions SELECTED DISPLAY | CONTROL F _ oe CONTROL FUNCTION Time Diplay Siow | Mines advance ot 2.0 He rate and seconds are hee atest (00) conition fest | Minutes aevance at 6D Hz rate and seconds are hae at reset (00) conaltion Both Time resets to 12:00:00 pm, (12-hour mode} oF 00:00:00 (24-hour mee ‘orm Diploy siow | alarm minutes avance a 20 He rte Fax | Alsen minutes advance ato 60 He rate Bots | Alarm resets to 12:00 pm. (12hour mode) 0 00:00 (24hour model One Disp sion | Date avances a a2.0 He rate Fest | Date advances at 260 Hecate oth | Date counter resets to 12:00 Minute Tier Display | Slow — | Mioutes uxtarycounterh advance ata 20 He rate ast — | Minutes (unio counter) advance at a 60 He rate oh | Timer counter resets vo 12:00 (12-Hour mode) or 00:00 (24hour model second Timer Ditslay | Siow | Seconds (auxiary counter advance ata 20 He rate fast | Seconds (auiiary counter) advance a 60 He rate aot | Timer counter ests to 12:00 (12hour model 0F 00:00 (2hour moe) sag Ly st, Lol sans [>] atts FL es FE ane | ee a J J evga Fone +} ein FIGURE 1. Block Diagram 7-30functional description (continues) FIGURE 2 a ne = | Lo | ve Ves = ov y) t4 4 Vop--2ve-ev | | | ie | t Note. LED interface — common cathode LED's (NSN. be interfaced with NIMS376AB by using two DM75491 tives, one OM75402 digit driver, sight 150, 1.04 resistors anda 10V power supply FIGURE 3. Typical Application FIGURE 4. 50 oF 60 He Shaping Circuit Seu98S XX9LESNWMM5376XxX Series functional description (continues) uvnintex | anions Tae ee eae aes m1 ores | i) wterae Lf Slee vosor waves | le al soit TLS scoot TTL J Tene Tene Le FL FIGURE 8, Output Timing DiagramMM5377 auto clock general description ‘The M5377 Auto Clock is a monolithic MOS integrated Circuit utilizing P-channel lowsthreshold, enhancement mode and ion-implanted depletion mode devices. The circuit interfaces directly with liquid crystal 4 digit displays and fluorescent tubes. The display format is 12 hours with leading-zero blanking and colon indication A voltage sensitive output is provided that drives an energy storage network which performs as a voltage doubler/ragulator. The circuit uses a 2 MH2 crystal Oscillator as the reference time base and is packaged in 40 lead dual-in-line package. features = Crystal controlled osciltator (2.097152 MHz) = 12 hour display format ® Colon output Clocks © Lesding zero blanking Hours and minutes set controls Crystal tuner output Voltage doubler contro! output Elimination of illegal time display at turn-on Direct interface to liquid crystal display Direct interface to fluorescent tubes Low standby power dissipation applications © Automobile clocks = Desk clocks = Portable clocks = High accuracy clocks block and connection diagrams se 2 SSE ™ L U Eo Sea Ese ace oe os mural a — =I ~ = LLESWWMM5377 absolute maximum ratings Voltage at Vag Pin Voltage at Any Pin Operating Temperature Storage Temperature Ves + 0.3V to Veg ~30V Vos + 0.3V t0 Veg ~24V 40°C to #85°C 65°C to +150°C Lead Temperature (Soldering, 10 seconds) 300°C electrical characteristics Ta within operating range, Vsg ~ #9V to #20V, Voo = OV, Veo. = ~10V, unless otherwise specitied PARAMETER CONDITIONS MIN TP MAX units Power Supply Voltage (Vss) Outputs and OSC Operational 8 18 20 v Power Supply Voltage (Vga) | Outputs and OSC Operational | 6 8 10 v Power Supply Voltage (Vss) No Loss of Time Memory 8 18 20 v Power Supply Voltage (Vss} lgnition Open 7 9 20 v Power Supply Voltage (Ve) | Ignition Open ° v Power Supply Current (Is) Ignition Open 1 3 5 mA. Input Frequency osc oc 2.097152 24 Me Frequeney of Outputs Liquid Crystal Display 32 He fiy = 2.097182 MHz OUTPUT CURRENTS Display Segments Vas = 18V Source Current Vour * Vss ~ 1V 200 BA Sink Current Vour = Ves ~17¥ 200 BA Display Colon and 10's Hours | Vs = #18V Source Current Vour = Vss ~ 1V 400 uA Sink Current Vour = Vss - 17 400 BA Display Backplane Vos = *18V Source Current Vour = Vss ~ 1.2 4 mA Sink Current Vour = Ves ~ 18.8 4 ma, Convertor Drive Output Source Current Vour > Vas ~ 6V 500 uA Sink Current Vour = Vss ~ 8V 100 HA FOSC/2 Source Current Vos = *18V Vour > Ves ~ 2V 200 HA Voltage Monitor Zener = 16V Source Current 100 BA Trip Point v7 18 19 vfunctional description ‘A block diagram of the MIM5377 auto clock is shown in Figure 1. & connection diagram is shown in Figure 2, Unless otherwise indicated, the following discussions are based on Figure 1. Oscillator 1 (Pin 34) and Oscillator 2 (Pin 33) A. quartz crystal, resonant at 2.019752 MHz, two capacitors and one resistor, together with the internal MOS circuits form a crystal controlled oscillator as shown in Figure 3. Varying one of the capacitors allows precise frequency setting, For test purposes, OSC 1'is the input and OSC 2 is the autput of an inverting amplifier FOSC/2 (Pin 32) FOSC/2 is the output of the first divide-by-two stage This output allows frequency tuning of the crystal oscillator without adding any additional capacitance to the oscillator circuit Set Hours (Pin 39) and Set Minutes (Pin 37), Set Hours will advance the hours at a 1 Hz rate when the input isheld at Vo. While setting hours, the minute's counter may also advance the hours count. Set Minutes will advance the minutas at a 1 Hz rate, hold the internal seconds counter reset and cause the colon to blink at 1 -Hz rate when the input is held at Voo. Depressing both switches at the same time shall cause the clock to initiate a hold and not advance until the switches are released. ‘Mode Select (Pin 36) Mode Select determines the shape of the output wave form as shown in Figure 4. With the input oper or at Voo. the output wave form is a 32 Hz square wave, Segments to be energized have the 32 Hz squere wave 180° out of phase with respect to the backplane 32 Hz square wave. Segments not to be energized have their ‘outputs in phase with the backolane output. With the mode select input at Vss, the outputs are at a constant level. Segments to be energized are at Vs, and segments not to be energized are at Voo. Time Test Input (Pin 35) Time Test Input causes the circuit to cycle through a 12 hour period using an internal clock af 65536 Hz instead of 1 Hz to increment the seconds counter when the input is at Ves. The input also causes the mode of the outputs to change from 32 Hz square wave to constant levels, Ignition Input (Pin 40) ‘The Ignition Input enables setting of the clock using the set hour or set minute inputs, and enables the drive to the display and the voltage doubler. When the input is at a voltage greater then 50 percent of the Vsg supply the time set, display and voltage doubler are enabled, ‘When the input is open circuited or at Voo. the time set, display and voltage doubler are disabled. The display ‘outputs and backplane drive are held to Vo when the display is disabled, This input does not affect the accu: racy of the time keeping logic in any manner. Voltage Converter Control (Pin 31) The Voltage Converter Contral input enables the voltage doubler to operate regardless of the state of the ignition Input when it is at Voo. When the input is open circuited or at Vsg, the voltage doubler is controlled by the ignition input. Output Circuits The Converter Drive output and all display outputs are push-pull stages with sources common to Vss {Pin 27) and drains common to Vop (Pin 38) as shown in Figure 5. FOSC/2 output is a open-drain stage with the source common to Vsg as shown in Figure 6. Figure & illustrates the interfacing between the clock and a liquid crystal display and the clock and fluorescent tubes, When driving fluorescent tubes, Veg can be connected te Vop. Converter Drive (Pin 29) and Voltage Monitor (Pin 26), The Converter Drive output oscillates at 65.636 kHz ‘The duty cycle of the wave depends on the state of the Voltage Monitor input pin as shown in Figure 7, With Vss_on the inpet pin, the duty cycle of the output wave is 50%, which enables the voltage doubler. Once the input pin is a few volts above the zener breakdown voltage of its’ zener diode (Figure 8), the duty cycle of the output is 0% or held at Vpp, which disables the voltage doubler. Therefore, the duty cycle of the output wave form varies from 50% to 0% as the voltage at the voltage monitor input pin varies. Therefore, the voltage to the chip is regulated about 2V abave the zener freak down voltage, Coton Output (Pin 10) ‘The colon output indicates the clock is counting by blinking at a 1/2 Hz rate. When setting minutes, the colon blinks at 1 Hz rate, LLeSWWMM5377 typical applications of FIGURE 3. Crystal Osciletor FIGURE 4. Output Timing Diagram FIGURE 5. Push-Pull Output Circuit FIGURE 6. Open Drain Output Circuittypical applications (con‘t} oe FIGURE 7. Operation of Converter Drive FIGURE 8. Typical Application LLESWWMM5378, MM5379 MM5378, MM5379 auto clocks general description The MMS37B and the MMS379 aute clocks are monolithic MOS integrated circuits utilizing P-channel low-threshold, enhancement mode and iorvimplanted depletion mode devices, The MM5378 circuit interfaces with vacuum fluorescent 4-digit displays. The M5379 circuit. interfaces with gasdischarge A-digit displays. The display format is 12 hours with leading-zero blanking and colon indication. The time keeping function operates from a 2 MHz crystal controlled or externally applied source features © Crystal-controlled oscillator (2.097152 MHz) ® 12-hour display format © Blinking colon output connection diagram Leading-zero blanking Brightness conteo! capability discharge displays Clocks Hours and minutes set controls No illegal time display at turn-on Simple interface to vacuum fluorescent and gas = Low standby power dissipation applications Automobile clocks Desk clocks Portable clocks High accuracy clocks Dual-in-Line Package ma © Ee Order Number MN6378N ornmss7oN Sie Package 20 block diagram > oss Fes it Lo: sey ome ae For Fe: ee ES rod FIGURE 1 138absolute maximum ratings Voltage at Any Pin Voltage at Any Display Output or ‘Switch Input Pin (MM5379 Only) Operating Temperature Storage Temperature Lead Temperature (Soldering, 10 seconds) Vgs + 0.3V to Vsg ~ 28V Vsg + 0.3V t0 Vgg~ 58V ~40°C to +85°C 65°C to +150°C 300°C electrical characteristics 14 within operating range, Vsg~ 9V to 20V, Vop ~ OV. unless othenwise specified [max PARAMETER ‘CONDITIONS MIN TYP UNITS Power Supply Voltege (gs) Outputs and Ose. Operational 9 20 v Power Supply Voltage (Vs! No Loss of Time Memory 5 cy v Power Supply Current (lgs) No Output Loads 1 5 mA Input Frequency (Ose, 1 or Ose. 2} ac | 2097182] 21 Mie Oscillator Inout Voltage (Note 1) Logical High Level Vgg-1.5 Vss v Logical Low Level Vsg-8.5 v Switch In Voltage (04015378) Logical High Level Internat Depletion Devieeto | Vgg-1.8 | Vg Vss v Logical Low Level Vss von | vss-8 v Switch tn Voltage {MM5279) Logical High Level Internal Depletion Device to ves5 | Vss v Logical Low Level Vss Vsg-25 v Output Currents (MM5378} Digit Outputs Logical High Level Vou = Vss~1V 80 mA Logical Low Lovet Vou=Voo 40 aA Segment Outpus Logical High Level Vou = Vss— 1 20 mA Logical Low Level Vou = Yoo 10 Ba Output Currents (M5379) Digit Anode Outputs | Logical High Level | Vou=Vss - sv 80 mA Logical Low Level Vou = Vss ~ 45V 40 HA Segment Cathode Outputs Logical High Level Vou = Vss ~ 8 20 mA Logical Low Level Vou = vss ~ 45 10 bA Note 1 toVss, functional description A block diagram of the MMS378 and the MMS379 auto clocks is shown in Figura 7, Connection diagrams for these devices are shown on the front page. Unless otherwise indicated, the following discussione are based on Figure 1 Crystal Oscillator: A quartz crystal, resonant at 2.097162 MHz, two capacitors and ane resistor, together with the internal MOS circuits form a crystal-controlled oscillator as shown in Figure 2. Varying one of the capacitors allows precise frequency setting, For test purposes, Ose, 1 is the input and Ose. 2 is the output of an inverting amplifier These are the input levels required if an external oscillator ‘aput preferred, using Osc. 2 (in Sh as the input while holing Ose, 1 (pin 6) Time Setting: Time setting is accomplished via the switch input pin, If this input is a logic high during the M1 digit time, the minutes counter will advance at 2 2 Hz rate with no earry to hours counter and will also cause seconds counter to reset, If the switch input is a logic high during the M10 digit time, the hours counter will advance at a 2 Hz rate, minutes and seconds counter will continue in real time. If the switeh input is 2 logic high during H1 digit time, seconds, minutes, and hours counters will reset to 12:00:00. If this input is a logic high during H10 digit time, a test mode will exist in which the minutes counter will advance at a 65.536 kHz rate with carry to hours counter (see Figure 3). An 6LESWIW ‘SESWMM5378, MM5379 functional description (continues) FIGURE 2. Crystal Oscillator internal pull-up resistor to Vgg provides normal time: keeping Output Multiplex Operation: Outputs from the appro- priate internal counter are time division multiplexed at 2 2048 Hz rate. The M5378 and MMS5379 provide 12 outputs (4 digit-anode drive outputs plus 8 segment: cathode drive outputs). The additional “segment” drive is provided to accommodate displays which feature a colon. The colon output is switched at a 1/2 Hz rate to provide a blinking colon as a short-time indication that the clock is operating. When driving vacuum fluorescent displays which enclose more than one digit in a common gas envelope, it is necessary to either (1) inhibit the segment drive ovaries P| var emaace UNIT HOU, “ani a ro waveron smmtoa smcany Yi Mone THAN ONE ‘mca waveronat eae : vaveronie eee ee SETMOURE « + REALTIME «| voltage(s) for a short time during inter-digit transitions, ‘or (2) avoid physical adjacent inter-digit transitions, The MMB379 auto clock utilizes an interlaced output sequence and interdigit blanking circuitry to prevent display arcing problems. The digit sequence is: (1) digit 0, 4 {unit minutes), (2) digit no. 2 {unit hours), (3) digit ‘no. 3 (ten’s of minutes), (4) digit no. 1 (ten’s of hours!, ete, Blanking intervals are provided to recharge level translating capacitors located in the display segment drive lines (Figure 6). Both segment data and digit enables are blanked. Figure 4 is a timing diagram which illustrates output timing for the MMS379. Figure 5 is a timing diagram which illustrates output timing for the MM5378, Brightness Control: Since display brightness is a func: jon of cathode segment current, @ capability of inter rupting this current for a variable percentage of the digit interval results in a brightness control. Depending fon the magnitude of the voltage applied, the digit "ON" time will vary from 0% to 100% of its possible period in 8 1/3% increments, This is illustrated in Figures 4 and 5. Output Circuits: All display output drivers, both digit and segment autputs, are open-drain enhancement devices (Figure 6). Thus, all outputs are capable of sourcing currents while externat pull-downs are required to sink currents. Figure 7 illustrates method of inter facing these outputs to ges discharge displays. sures count AavaNesS AT 2 Me Rate tenures counveh unareecrea COLON SLIMMING ‘MuTes COUNTER ADVeNCSS AT 45.5361 RATE WTH COMPLETE CARRY COLON MELD OWT Ay S950 HH ARTE Eatowweta “on” FIGURE 3, MMS378, MMS379 Setting Control Functionsfunctional description (con:inues) Vs5—+ i ro me Vss— 100% Le fo] ow Pon Pow iit Mss are aK v— anicur ow oN ON [aT e Pom Pos 28, Vss—" 1 | 7 To 228 ea tic ON ON NN FIGURE 4. MM5379 Output Timing Diagram nans378 Mss avoaray TyetcaL o1Gir Voo OR SEGMENT (oven onan) OUTPUT ouctt not vss oe ee ee as oiGrT No.2 | a UNIT HOURS fw 2 rt 366s init No.3 | aa Yss TEN'S MINS mio = 4 Aus ovcir no. i Vs vevsnouns = | | wa a 100% Vss nit o_o Pow Lae fo“ any seéminr a ore ss ‘ON ON ‘ON ON v 100% asicwt covon 3% —— “se ericnr JL J) J] J) 7 xa x FIGURE 5, MM5378 Output Timing Diagram muss79 Vg ayoara) ‘TyPICAL o1GIT op OR SEGMENT (OPEN DRAIN) OUTPUT FIGURE 6. Output Circuits G6LESW ‘SLESMM5378, MM5379 functional description (continues) i FIGURE 7. Typical Application for MME379Clocks MM5382, MM5383 digital calendar clock radio circuits general description ‘The MNM5382 and MM5383 digital calendar clock Circuits provide the timing, control, and interface circuitry for a minimum-cost, solid state, digital clock radio. ‘The timekeeping function operates in either a 12-hour or a 24-hour mode. The MM53B2 is the 12-hour version, and has a month-date format; the MMS383 is the 24-hour version, and has a date-manth format Outputs consist of 2 presettable 59-minute sleen timer (e.g, a timed radio turn off) and an alarm tone, A power failure indication warns the user that the time displayed may be in error: Other features include: alarm display; brightness control; 24-hour alarra set; PM indication; fast and slow set controls; and a 9uninute snooze alarm. (The MM5383 hhas an alarm “ON" indicator.) Both circuits provide ‘open drain outputs for the diceet drive af LEO displays 10 15 mA, features © 60 or 60 Hz operation = 12 hour, month-date (MMS382) or 24 hour, date- month (MM5383) display = PAW indication (MM5382) © Leading zero blanking © 24-hour alarm setting = Power failure indication (the word "OFF" is displayed in MM5382 and all “ON digits blink in M5383 Brightness control Date display (4 year calendar) Presettable 59-minute sleep timer Alarm display ast and slow set sleep and alarm 9 minute snooze alarm Blinking colon Alarm "ON" indication (M5382 only) Alarm tone output No illegal time or date display at turn-on applications = Alarm clock Desk clock Clock radios = Stop watch © Industrial clock ® Portable clock = Timer © Sequential controllers connection diagrams Dual tn-Line Package PE soon, Order Number MMS3B2N ‘See Package 24 (Order Number MMS3E3N ‘See Package 28 FIGURE ESESWW ‘Z8EsSNWMM5382, MM5383 absolute maximum ratings Voltage at Any Pin except Segment, Vgg +0.3V to Vsg ~28V Colon, and PM Voltage at Segment, Coton, and PM Veg #0.3V to Vgs ~10V Operating Temperature 28°C to +70°C ‘Storage Temperature -65'C to +150°C Lead Temperature (Soldering, 10 seconds) 300°C Maximum Power Dissipation 1 Watt Electrical Characteristics ‘Ta within Operating Range «Vg = +18V to +26V, Vp = OV, with specified output drive Unless otherwise specified Functional Clock Voltage Vs = +8V to #26V, Vpp = 0 (No output drive spec) electrical characteristics PARAMETER CONDITIONS MIN ye MAX | UNITS Power Supply Current No output levels Vgs= 8V 4 mA Vg ~ 26V 5 mA 50/60 Hz Input Frequency pc 50 or 60 30k He Voltage Vgg = 18V Logical High Level Vss~1 Vss Vss Logical Low Level oo Yoo Voo*t ‘Switch Input Voltages (Date, Sequence, Alarm Enable, Alarm Display) Logical High Level Vss~1 Vss Vss Logical Low Level (1) Nominal Floating Level Vgs-3 Float Vss-6 v Logical Low Level (2) vo Yop voo!2 v All Other Input Voltages Logical High Level Vss-1 Vss Vss Logical Low Level Internal Depletion Load Vss~18 toVoo Power Failure Detect Voltages (Vgg Voltage] 10 80 v Output Currents: Vgg = 18V to 26V, Vop = OV Al! Segments and Colon Logical High Level, Source Vou = Vss~2V 15 mA Logical Low Level, Leakage VoL * Vss—10V 10 aA PM Indicator and Alarm Indicator Logical High Level, Source Vou = Vss-2V 18 mA, Logical Low Level, Leakage Vou = Vs5—l0v 10 WA Alarm and Sleep Outputs Logical High Level, Source Vol = Vss-2V 2 ma Logical Low Level, Sink Von = Vss-15¥ 500 uA ‘Alarm Output Tone Vgs = 18V to 26V 400 2000 He Frequency Modulated with 2 Hz Total Power Dissipation \Vgs = 26V, Vpp = 0V 830 mW 1QUT (25 Segments) = 15 mA T= 70°C Vour * ¥ss-2¥ 14ablock diagram r 7 omy : rman | [eel (}-—[ | | ae TUG lpiy Mes nd eing Contd Punts ‘ a Cate ony] Tan uniay— |” Seauenee alee? “UNCTION oe ADVANCE. SET/SNOOZE DISPLAY ooo ae alae = = = ae = oo le a won coo te ee See ae eee foe | | ee eee | ome el ae - - eee |e a a : co eee) ee ee ieee ero | 6 leer le 7 functional description Connection diagrams for the MM§382 and the MMS383 Digital Clock Radio Circuits are shown in Figure 1. A block diagram of these devices is shown in Figure 2, Uniess otherwise indicated, the following discussions are based on Figure 2 Figure 3 shows the general purpose alarm clock and procedure to set the time, month, day, alarm and sleep counters. Table | shows the display modes and setting control funetions. 50 or 60 Hz Drive: A shaping circuit is provided to square the 50 or 60 Hz input. This circuit allows use of a filtered sinewave input. The circuit is a Schmitt trigger that is designed to provide about 4V of hysteresis. A simple RC filter should be used to remove possible line: voltage transients that could either cause the clock to gain time or damage the device. The input should swing between Vss and Vpp. The shaper output drives ¢ ‘counter chain which performs the timekeeping function. 50 or 60 Hz Select Input: A programmable prescale Counter divides the input line frequency by either 50 or 60 to obtain a 1 Hz base. This counter is programmed to divide by 60 simply by leaving the pin unconnected: a pull-down to Vpp is provided by an internal resistor, Operation at 50 Hz is programmed by connecting this Input to Vgg. Alarm Operation: The internal alarm comparator senses coincidence between the alarm counters (the alarm, setting) and the time counters (real time). The comparator output is used to set a latch in the alarm and sleep cir cuits. The alarm latch remains set for 69 minutes during Which time the alarm or radio will sound if the latch ‘outputs are not temporarily inhibited by another latch set by the snooze input or reset by the alarm “OFF” input. 145) E8ESWW ‘Z8eSWWMM5382, MM5383 functional description (Continued) Alarm ON/OFF/RADIO Input: Momentarily leaving this input unconnected resets the alarm latch and thereby silences the alarm. This input is also used to determine if the alarm or the sleep output will be enabled when the alarm fateh is set. By connecting the input pin to VoD. both tho alarm output and the steep output (radio) are ‘enabled when the alarm latch is set. If the input pin is connected to Vgg, only the sleep output {radio} is enabled when the alarm latch is set. Momentarily leaving this pin unconnected also readies the alarm latch for the next comparator output, hence, the alarm will auto: ‘matically sound again in 24 hours {or at @ new alarm setting). If it is desired to silence the alarm for a day or more, the Alarm ON/OFF Radio input pin should re: ‘main’ unconnected. Alarm Output: The alarm output signal is a tone of from 400 Hz to 2000 Hz, which is gated on and off at a 2 He rate Alarm Display, Set/Snooze: Momentarity connecting this pin to VD when the alarm and sleep outputs are dis abled displays the alarm setting for 1.5 to 2 seconds. The display shows the hours and minutes of the alarm setting, a constant colon and a PM indication if the clock is in the 12 hour mode. If the input pin is held to Vpp for fonger than 2 seconds, the minutes of the alarm counter start to advance at a 2 Hz rate. To increase the rate that the alarm counter is set at, also connect the Date/ Advance input pin to Vpp. The minutes of the alarm counter will now advance at a 60 Hz rate. By momen: tarily connecting the input pin to Vp when the aiarm ‘or sleep output is enabled, snooze is enabled for 8 ot 9 minutes. Snooze inhibits the alarm output for between 8 and 9 minutes, after which the alarm output is enabled again. Snooze has no effect on the sleep output. The snooze feature may be repeatedly used duringthe 59 minutes in which the alarm latch remains set. Momen- tarily connecting this input pin to Vip when the clock is in the power failure mode stops all power failure indications and displays alarm. If this pin is connected to \Vgg and date advance pin is connected to Vg, the clock, is in a test mode, All outputs are enabled and time and alarm are set to 12:00 AM, the date is set to the 12th month and the 1st day, and the sleep counter is set to 00 minutes. If the Alarm Display, Set/Snooze is at Vss. all outputs and inputs are disabled except 50/60 Hz Select and 50/60 Hz Drive, Sleep Timer and Output: The sleep output can be used to turn off @ radio after a desired interval of up to 59 minutes, The time interval is chosen by selecting the sleep display mode and setting the desired time interval This automatically results in a currentsource output, which can be used to turn on a radio (or other appliance) When the sleep counter, which counts downwards, reaches 00 minutes, a latch is reset and the sleep output current drive is removed, thereby turning off the radio. This turn-off may also be manually controlled (at any time in the countdown) by @ momentary VDD connection to, the Alarm Display, Set/Snooze input. Sequence/Sleep Display and Set: If left open, time or the counter to be set is displayed. Momentarily con: necting this pin to Vsg displays the sleep counter for 1,5 to 2 seconds, If after 2 seconds the pin is still at Vgs, the sleep counter will decrement at a 2 Hz rate, TO increase the rate at which the sleep counter is decre- mented, also connect the Date/Advance pin to VDD. The sleep counter will now decrement at a 60 Hz rate. Mlomentarily connecting the Sequence pin to Vp steps the clock through its set modes. There are 6 states; they are real time, set hours, set minutes, set month (12 hour mode}, set day (12 hour mode), and the holding state. ‘When real time is displayed, a momentary connection to Vpp advances the clack to the set hours state. In this state, hours are displayed, minutes are blanked, the colon is constant, and an A or P is displayed in theunit minutes position if the clock is in the 12 hour mode. To set hours, the Date/Advance pin is connected to Vop. The next time the Sequence pin is connected to Vp, the clock is advanced to the set minutes state. In this state, the minutes are displayed, the hours are blank, the colon is constant and the PM indication is displayed if the clock is in the 12 hour mode and set for PM. The next stata the clock advances to is the set left state. In the 12 hour mode, this is a month set state, For the 24 hour mode, this is a day set state. In this state, the left two digits of the display are shown, the colon and the right, two digits of the display are blank, The next state the clock advances to is the set right state, In this state the day in the 12 hour mode or month in the 24 hour mode is displayed in the right two digits of the display, Fy i ‘j _ ry 0 Ft poll — ‘Time and Date Display Format in ‘Set’ Modo 146functional description (continues) The left two digits and colon are blank. The next transi- tion on the Sequence input displays reat time if the minutes were not set. If the minutes counter was set, the next state the clock advances to is the holding state, In this state the time and the colon are blinking at a 2 Hz rate and held to the set time. To leave the holding state, the Sequence Input is connected to Vipp momen: tarily. If the clock remains in any state except the holding state for more than 10 seconds without being set, the clock will automatically advance to real time or the holding state if minutes were set Note: Time set mode should not he initiated while in alarm or sleep display 2 second time out. Time set mode should be sequenced cnly when the clock displays real time. Date/Advance Input: If left open, this input has no effect on the clock. Momentarily connecting this pin to Vp dispiays the date for 1.5 to 2 seconds if the clock was not in a set state. if after 2 seconds the input pin is, still at Vpp, the date remains displayed until the input pin is released. If the Date/Advance pin is connected to. Vpp when the clock is in a set mode, the counter dis: played will advance at a2 Hz rate until the pin is released. Connecting this input pin to Vp when the sleep counter (or the alarm counter is displayed advances the displayed counter at @ 60 Hz rate. If the Date/Advance pin is con: nected to Vgg, the seconds counter is bypassed and minutes counter advances at a 1 Hz rate, Colon: The colon output blinks at a 1 Hz rate in the run mode, It is constant during set hours and minutes, and alarm display. The colon is blank for date display. The colon blinks at a 2 Hz rate in the holding state, ‘Alarm Indication Output: Whenever the alarm is enabled, the Alarm Indicator output is turned on, It is used t0 indicate to the user that the alarm has been set. PM Output: The PM Qutput is available only in the M5382. This output is enabled only when time or alarm are displayed. Power Failure Indication: If the power to the integrated Circuit drops, indicating @ momentary ac power failure and possible loss of the correct time, in the MM5382 the word ‘OFF’ is displayed blinking at a2 Hz rate, in the M383 all the ‘ON’ segments blink at 2 Hz rate and the colon is blank, Momentarily connecting the Alarm Display Set/Snooze input to VoD displays first the alarm for 1.5 to 2 seconds and then real time. In addition, if the alarm was “ON” the Alarm “ON/OFF” input should also be momentarily connected to VoD. LED CURRENT CONTROL INPUT AND REFERENCE OUTPUT Pin (15) MIM5382, pin (16) MM5383 controls the gate voltage at al the display outputs and the reference device, The output drives can be disabled by connecting pin 15 MM5382, 16 MMS383 to Vsg. This wire-OR capability allows the display to be used for other functions (e.g. temperature). The output current can be controlled two. ways; 1) driving the output in saturated mode: 2} driving the output in linear mode. (Refer to Figures 4 and 5.) 1. The reference device pins (4, 15) MMS382 (5, 16) MM5383 are connected as diodes and an external resistor is used to set the desired current in these diodes (see Figure 4}. The segment drivers of all digits are connected as current mirrors. The drain oS Time and Date Set Flow Chart MMS382, 12-Hour Mode BT face] J farce vegmeg EE gue SE" romana soma LE PL ees ait ‘Time and Date Set Flow Chart 'MM5383, 24-Hour Mode a7 E8ESWI ‘Z8ESNWMM5382. MM5383 functional description (Continued) voltage V1 of the segment drivers is selected such that these devices operate in saturation mode. 1 Since the drain current variation in saturation a mode operation of the MOS device is relatively a constant, the segment drive current does not vary significantly, even though V1 is increased con- siderably. However, as the voltage across the output a bbutfers increases, average power dissipation also 5 increases linearly. This technique of current contro! is recommended to be used only with low current 6 LEDs (1-7 ma). 2. The high current drive requirement of large LED displays can be accomplished by operating the segment drivers in the linear mode. The circuit for high current LED drivers is shown in Figure 5. ‘The reference output device is used in series with a reference LED, diode and current setting resistor A high beta PNP transistor provides the current drive for all the segments. A reference voltage V3 is developed which compensates for variations in MOS process parameters and the variations in the voltage drop across the LED, The rasistor sets the current in the reference LEO which sets the reference voltage V3 which in turn sets the current in the LEDs equal to resistor curront minus the 7 base current of the transistor. Variation in second, supply voltage does not vary the LED currents so. long as the PNP transistor is kept operating in the linear mode, Full wave rectified power supply without any filtering can be used as a second supply voltage V2. The LED brightness can be varied by using a variable resistor. Figure 6 shows a LED drive circuit which uses a single resistor. The resistor controls the total current flowing through all the segments. Brightness shall vary depending, ‘on number of segments that are “ON at that time. Radio Frequency Interference: All display outputs in 9, clude circuitry to slow up the switching transition time to minimize radio frequency interference. Glock Set Up Procedure: (MIM5382) Connect 110V supply. Blinking ‘OFF’ displayed. Momentarily connect alarm display set/snooze pin (13) to Vp which removes “OFF” and displays first the alarm for 1.5 to 2 seconds, then real time. Momentarily connect alarm “ON/OFF” to Vss. Wait till the colon starts blinking. (Approximately 2 seconds.) Time setting a. Momentarily connect sequence pin (14) to Yoo display shows hour and AM or PM. Connect advance pin (11) to Vpp to advance hour. b. Connect pin (14) momentarily to Vop display shows minutes, connect pin (11) to Vop and set minutes, ©. Connect pin (14) momentarily to VoD display shows month, connect pin (11) to Vpp and set month, d. Connect pin (14) momentarily to Vpp display shows date, connect pin (11) to Vp and set date. ‘e. Connect pin (14) momentarily to Vp and the real time is displayed at 2 He rate f. Connect pin (14) momentarily to Vop again and real time is displayed continuously. Alarm setting a. Connect alarm display pin (13) to VoD and hold it for more than 2 seconds. Alarm minutes will advance at slow rate b. Connecting pin (11) and pin (13) to Vop simultaneously will advance the alarm time at a fast rate. . Set the desired alarm time. . Sleep time setting @ Connect, sleep display, pin (14) to Vsg and hhold it for more than 2 seconds. Sleep time will decrement at slow rate. b. Connecting pin (11) and pin (14) to Vop simultaneously will decrement the sleep time at a fast rate. cc. Set the desired sleep time. Connect pin 12 to Vipp to activate alarm. Note: Time and date setting must be done only in the real time display mode. FIGURE 3. Calendar Alarm Clock Usi the MM5382 and # LED Display 148functional description (continued) Yeo ommtnat” geen S37 a i FIGURE ala). Low Current LED Drive Control Circuit (1=7 mA Meg SuLY oko vss, r ss r Vos, FIGURE 6(a). High Current LED Drive Current Circuits (718 mA 0 rae Ys Vis FIGURE 6. Simple LED Drive Cireuit FIGURE 4(b). Segment Current vs Vp (pp at ~18V) (Typical Output Characteristics) Fonte FIGURE 5(b). Row + Vop (Vos #t-1V) (Typical Output Characteristics) FIGURE 7. tin vs Vin ( Input Depletion Load Ch 1-49 ESESINW ‘ZsesWNNMM5384 Clocks MM5384 LED display digital clock radio circuit general description The MM5384 digital clock radio circuit is monolithic MOS integrated circuit utilizing P-channel low-threshold, enhancement mode and ionimplanted depletion mode devices. It provides ali the logic required to build several types of clocks and timers. Four display modes (time, seconds, alarm and sleep} are provided to optimize circuit utility. The circuit interfaces directly with 3 1/2 digit 7-segment LED displays, The timekeeping function operates from either 2 50 or 60 Hz input, and the display format is 12 hours (with leadingzero blanking and AM/PM indication) or 24 hours. Outputs consist of display drivers, sleep {e.g., timed radio turn-off), and alarm enable, Power failure indication is provided to inform the user that incorrect time is being displayed, Setting the time cancels this indication. The device operates over @ power supply range of 8-26V and does not require a regulated supply. The MMS5384 is packaged in a 40 lead dual-inline package. features 50 or 60 He operation Single power supply 1201 24 hour display format AM/PM outputs Leading-2er0 blanking 2a-haur alarm setting All counters are resertable Fast and slow set controls Power failure indication Blanking/brightness control capability Elimination af illegal time display at turn-on Direct interface 0 0.5” LED displays Qminute snodze alarm Prosettable S9.sminute sleep timer applications Alarm clocks Desk clocks Clock radios Automobile clocks Stopwatches Industrial clocks Portable clocks Photography timers Industrial timers Appliance timers Sequential controllers block and connection diagrams Dush:in-Line Package FIGURE 1. Order Number MMS384N ‘See Package 28 FIGURE 2 1 50absolute maximum ratings Voltage at Any Pin Except Segment Outputs Vg + 0.3 to Vgg ~ 30V Vgg + 0.3 to Vgg~ 15V 28°C 10 +70°C “85°C to +150°C Voltage at Segment Outputs Opereting Temperature Storage Temperature Lead Temperature (Soldering, 10 seconds) electrical characteristics Ta within operating range, Vgg = 24V to 26V, Vp = OV, unless otherwise specified PARAMETER CONDITIONS MIN tye | MAX UNITS Power Supply Voltage (Output Driving Display 24 26 v Functional Clack 8 26 v Power Supply Current No Output Loads vss 4 mA Vgs = 28V 5 ma, 50/60 Hz Input Frequency Voltage | Vgg = 8V to 26V de | S00r60 | 10k He Logical High Level vss-1 | Vgg Vss v Logical Low Level Von | von | Voot2 v 50/60 Hz Input Leakage 10 uA Blanking Input Voltage Logical High Level Vgs-1 | Vss Vss v Logical Low Level von | Yoo | Vss-5 v Blanking Input Leakage { 10 BA All Other input Voltages Logical High Level Vss-1 | Vss vss. v Logical Low Level Internal Depletion Device to Vpp, voo | voo | vss-6 v Power Failure Detect Voltage (Wgg Voltage, (Note 2) 1 8 v Count Operating Voltage 8 26 v Hold Count Voltage (Note 2) 26 v Output Current Levels Vs = 24V to 26V, Output Common = Vgg. 10's of Hours (b & c), 10's of Minutes (a & d) Logical High Level, Source VoH = Vs - 7 10 mA Logical Low Level, Leakage VoL = Vss — 14 10 BA 1 Hz Display Logical High Level, Source Vou = Vss —7 15 mA Logical Low Level, Leakage Vou = Yss - 14 10 uA All Other Displays Logical High Level, Source VoH = Vgs ~ 7V 6 mA, Logical Low Level, Leakage VoL = Vss — 14 10 uA Alarm and Sleep Outputs | Vss=24v Logical High, Source Vou = Vgs ~ 2 600 uA Logical Low, Sink | vou= Vpn +2 1 uA, Niles 10.6 mA maximum by User; power dissipation must be limited to 900 mW at 70°C and 1.2W Note 2: Power fel detect voltage is 0.25V oF more above the hold count voltage. The ower fal latch trips into ower fal mode at least 0,25V above the voltage at which data stored in the time latch v lost 151 v8EsMWMM5384 functional description A block diagram of the MMS5384 digital clock radio circuit is shown in Figure 1. The various display modes provided by this clock are listed in Table I. The functions of the setting controls are listed in Table II Figure 2 is @ connection diagram. The following dis- ‘cussions are based on Figure 1 50 or 60 Hz Input: A shaping circuit (Figure 3) is pro. vided to square the 50 or 60 Hz input. This circuit allows use of a filtered sinewave input. The circuit is a ‘Schmitt trigger that is designed to provide about BV of hysteresis, A simple AC filter such as shown in Figure 5, is recommended in order to remove possible line-voltage ‘transients that could either cause the clock to gain time ‘of damage the device. The shaper output drives a counter chain which performs the timekeeping function, 50 or 60 Hz Select Inputs: A programmable prescale counter divides the input line frequency by either 50 or 60 to obtain a 1 Hz time bose, This counter is programmed to divide by 60 simply by leaving 50/60 Hz select unconnected; pull-down to Vp is provided by an internal depletion device. Operation at 50 Hz is pro: ‘grammed by connecting 50/60 Hz select to Vss Display Mode Select Inputs: In the absence of any of these three inouts, the display drivers present time-of- day information to the appropriate display digits. nter nal pulldown depletion devices allow use of simple SPST switches to select the display mode. If more than fone mode is selected, the priorities are as noted in Table |. Alternate display modes are selected by applying Vag to the appropriate pin. As shown in Figure 1 the code converters receive time, seconds, alarm and sleep information from appropriate points in the clock circuitry. The display mode select inputs control the gating of the desired data to the code converter inputs and ultimately (via output drivers} to the display digits Time Setting Inputs: Both fast and slow setting inputs are provided. These inputs are applied either singly or in combination to obtain the control functions listed in Table II. Again, internal pull-down depletion devices are provided; application of Vgg to these pins affects the control functions, Note that the control functions pro per are dependent on the selected display mode. For example, a hold-time control function is obtained by selecting seconds display and actuating the slow set input, As another example, the clock time may be reset to 12:00:00 AM, by selecting seconds display and actua: ting both slow and fast set inputs. Blanking Control Inputs: Connecting this Schmitt Trigger input to Vp places all display drivers in a non conducting, high-impedance state, thereby inhibiting the display. See Figures 3 and 4, Conversely Vsg applied to this input enables the display. This input does not have internal pull-down device. ‘Output Common Source Connection: All display output Grivers are open-drain devices with all sources common (Figure 4). Common source pin should be connected to Vgg. 12 of 24-Hour Select Input: By leaving this pin uncon: ected, the outputs for the most-significant display digit (10's of hours) ate programmed to provide a 12-hour display format. An internal pull-down depletion device is again provided. Connecting this pin to Vsg programs the 24-hour display format, See Figure 6 for 24-hour application. If the power to the integrated circuit drops, indicating a momentary ac power failure and possible toss of clock, the AM or PM indicator will flash at 1 Hz rate. A fast or slow set input resets an inter: nal power failure latch and returns the display to nor mal ‘Alarm Operation and Output: The alarm comparator (Figure 1) senses coincidence between the alarm count- ers (the alarm setting) and the time counters (real time}. The comparator output is used to set a latch in. the alarm and sleep circuits. The latch output enables the alarm output driver (Figure 4), the MMB384 output that is used to control the external alarm sound genera tor, The alarm latch remains set for 69 minutes, during which the alarm will therefore sound if the latch output is not temporarily inhibited by another latch set by the snooze alarm input or reset by the alarm off input. ‘Sno :+e Alarm Input: Momentarily connecting snooze to Vgg inhibits the alarm output for between 8 and 9 minutes, after which the alarm will again be sounded. This input is pulled-down to Vo by an internal deple: tion device, The snooze alarm feature may be repeatedly used during the 89 minutes in which the alarm latch remains set. Alarm Off Input : Momentarily connecting alarm off to Vgg resets the alarm latch and thereby silences the alarm. This input is also returned to Vp by an internal depletion device. The momentary alarm off input also readies the alarm latch for the next comparator output, {and the alarm will automatically sound again in 24 hours (or at a new alarm setting). If it is desired to silence the alarm for a day or more, the alarm off input should remain at Vss, Sleep Timer and Output: The sleep output at pin 14 can be used to turn off @ radio after a desired time interval of up to 59 minutes. The time interval is chosen by selecting the sleep display mode. (Table 1) and setting the desired time interval (Table 11). This automatically results in a current-source output via pin 14, which can bbe used to turn on a radio (or other appliance). When the sleep counter, which counts downwards, reaches 00 minutes, a latch is reset and the sleep output current drive is removed, thereby turning off the radio. This turnoff may also be manually controlled (at any time in the countdown) by amomentary Vg connection to the Snooze input. The output circuitry is the same as the other outputs (Figure 4). 182functional description (Continued) Yoo sana nz wnPUT OR suaacans ine0T Lom va IGM Vy Vs FIGURE 3. 50/60 oF Blanking Input Si + optPur COMMON SOURCE BUS N18) Giotay auanain ‘erom: ouTeur suareal (oven onan Vss FIGURE 4a, Segment Outputs savsa ne ovrPUt on BLANKING SIONAL taping Circuits Vs FROM ALARMISLEEP, ‘Cowpanarans ourrut FIGURE 4b, Alarm and Sleep Outputs ‘TABLE 1. M5384 Display Modes ssevecteo | rey DiGiT No.1 pisitno.2 | oicitwo.2 | o1artNo.4 Time Oipiay| TOsoF Howe awiee | Howe TOsot Minutes | Minutes Seconds Oisolay | alunkes Minwter 10's0t Seconds | Seconds Alarm Oispey W'sof Hous &ameM | Hous Tos ot minutes | minutes Sleep Dispiay Blanked Blanked 10's ot Minutes | Minutes "If more than one display mode input is applied, the display priorities ae inthe order of Sleep (over: ‘ides all others}, Alarm, Second, Time (no other mode selected) 153 psesWWMM5384 functional description (continues) ‘TABLE II, MMS]84 Setting Control Functions SELECTED | CONTROL . : pisptay move | INPUT ee “Time Slow Winuiss Advance at 2 He Rate Fast Minutes Advance at 60 Me Rate Both Minutes Advance at O0 HE Rate Alarm Slow Alacm Minutes Advance at 2 He Rte Fast ‘Alam Minutes Advanoe at 60 He Bate Bah ‘Alarm Resets to 12:00 AM (12 hour formal Both ‘sisim Resets {9 QD:00 (24\nour fest) Seoonde Slow Ingut 0 Entire Tine Counter s inhibited (Hold) Fast Seconds and 10% of Seconds eset to Zero Without a Carry to Minutes Both ‘Time Resets t6 12:00:00 AM (12 hour format) Bor ‘Time Resets t0 00:00:00 (28 hour format) Sleep Siow SSubstacte Gount at 2 He Fast Substecte Count at 60 He 0h Sobstrects Count at 60 He “*vunen setting time sleep minutes wll decrement at rate of time counter, vatil the sleep Courter reaches 00 minutes (sleep counter will aot reeyele). q Fey ry r T ee eee] + +¢ ~ 1 7 154functional description (continued) : | : | omnes Segment | FIGURE 6. 24-Hour Operation: 10's of Hours Disit Connections 155) pSESWNWMM5385, MM5386, MM5396, MM5397 Clocks MM5385, MM5386, MM5396, MM5397 digital alarm clocks general description ‘The MMS385, MMS386, MM5396 and MMS5397 digital alarm clocks are monolithic MOS integrated circuits utilizing P-channel low-threshold, enhancement _mode and ion-implanted depletion mode devices. MM5385 or MMB5396 and MM5386 or MM5397 have display formats of 12 hours and 24 hours respectively, with 24:hour alarm display capability. They provide all the logic required to build several types of clocks and timers Four display modes (time, seconds, alarm and sleep) are provided to optimize circuit utility. The circuit interfaces directly with 7-segment light emitting diodes ‘and requires «wo power supplies. The timekeeping function operates from either a 50 or 60 Hz input. MM5385 or MM5396 displays 12 hours with colon flashing at a one second rate and a PM indication. MM5386 or MMS5397 displays 24 hours with leading zero blanking, Outputs consist af display drives, sleep (eg.. timed radio turn off), and alarm enable. Power failure indicetion is provided to inform the user that incorrect time is being displayed. The power failure indication consists of flashing of all the “ON" digits at a1 -Hez rate, Setting the time cancels this indication. ‘The device operates over a power supply range of 18-26V and LED supply voltage of 4~7V. ‘The MMS396 and MMS397 are reverse lead-bend versions (mirror image) of the MMS385, MMS5386 (respectively) ideally suited to facilitate PC board layouts when designing an “L" shaped clock "module" (vertical features 50 or 60 He operation © Low power dissipation = PM outputs in 12:hour format with a colon flashing fat a one second rate {{MMS5385 and MM5396 only} = Leading zero blanking = 24hour alarm setting # All counters are resettable = Fast and slow set controls, = Power failure indication © Blanking/brightness control capability © Direct interface to light emitting diode (LED) with forward current of 3-15 mA = Individual drivers for each segment of each digit = Bminute snooze alarm = Prosettable 59-minute sleep timer Radio frequency interference eliminating slow up circuitry atthe outputs Avsilable in standard (MM5385, MMS3B6) or reverse Tead:bend version (MM5396, MM5397) applications Alarm clocks Desk clocks Clock radios Stopwatches Industrial clocks Portable clocks display, horizontal component board); the MM5385, MMS386 are better suited for applications where the display and IC are mounted on 9 PC board in the same plane. All four versions are supplied in a 40-lead dual-in fine package. Photography timers industrial timers Appliance timers Sequential controllers block diagram Note. M5396, MM5397 pin connections shown in parenthesis (xx) FIGURE 1 196absolute maximum ratings Voltage at Any Pin Voltage at Any Output Pin Operating Temperature Storage Temperature Power Dissipation Lead Temperature (Soldering, 10 seconds) electrical characteristics Ta within operating range, Vgg = 18V to 26V, Yop. Vgs + 0.3 to Vgg ~ 28V Vsg + 0.3 to Vg ~ 7.5V ~25°C to +70°C “65°C to +150°C Ww 300°C WV, unless otherwise specified PARAMETER, CONDITIONS MIN tye | MAX UNITS Power Supply Voltage (Vgg) ‘Output Driving Display 18 26 v Functional Clock 8 26 v Power Supply Current No Output Loads, Vgg 5 mA 50/60 Hz Input Frequency Voltage dc | 500r60 | 10k He Logical High Level Vgs-1 Vss v Logicat Low Levei Vo vop+1 v All Otner Input Voltages (ote 2) Except Sleep/Seconds Display Logicat High Level Vgs-t Vss v Logical Low Level Internal Depletion Vo vopt7 v Device © Vo Power Failure Detect Voltage (gg Voltage) (Note 1) 1 75 v Output Currents Vgg = 18V to 26V, Vpp = OV. Current Measured in Individual Segment Driver with 0 Current in Remaining Segment Driver, LED Current Controt Connected to Vo All Segment Drivers Logical High Level Von = Vgg - 2 15 ma, Logical Low Level VoL = ss -6 10 WA Alarm and Sleep Outputs Logical High Level Vou = ¥ss - 2 800 uA Logical Low Level Vou= Vo +2 1 HA LED Reference Output LED Current Control Connected to Vp. Vsg = 18V, All Segment Driver 0 Current Logical High Level Von = Vss 2 15 mA, Logical Low Level Vou=Vss = 6 10 BA Note 1: The powerfal detect voltage is O.5V or more above the hold count voltage. The nower-tll latch trips into the power fil mode at feast (0.5V above the voltage at which data stored in the time latch i lost, [Note 2: Sleep/seconds display (sin 11 on MMB3B5 and MM5346, pin 30 on MMS396 and MM5397). Connect pin to Vsg for Sleep display. Connect pin to Vop for Seconds display, Leave pin open for normal time display 187 LGESWIW ‘96ESWIN “OSES ‘SSeSWWMM5385, MM5386, MM5396. MM5397 functional description A block diagram of the MMS385, MM5386, MM5396 ‘and MM§397 digital alarm clock is shown in Figure 1. ‘The various display/setting modes are listed in Table | and Table I shows the setting control functions. The following description is based on Figure 1; for simplifi cation, pin numbers in the text are shown only for the MM5385 and MME386, but pin connections for the MM5396 and MM5397 may be cross-referenced from the diagrams in Figure 2. 50 oF 60 Hz Input (pin 8): A shaping circuit (Figure 3) is provided to square the 50 or 60 Hz input. This circuit allows use of a filtered sinewave input. The circuit is @ ‘Schmitt Trigger that is designed to provide about 6V of hysteresis, A simple RC filter, such as shown in Figure 7, should be used to remove possible line-voltage tran- sients that could either cause the clock to gain time or damage the device. The input should swing between Vgg and Vpp. The shaper output drives a counter chain which performs the timekeeping function, 50 or 60 Hz Select Input (pin 7}: A programmable prescale counter divides the input line frequency by either 50 of 60 to obtain a 1 pps time base, This counter is programmed to divide by 60 simply by leaving pin 7 unconnected; pull-down to Vpp is provided by an Internal depletion toad, Operation at 50 Hz is pro: grammed by connecting pin 7 to Vs. Display Mode Select Inputs (pins 11. and 17): In the absence of any of these two inputs (i.e., pin open}, the display drivers present time-ofday information to the appropriate display digits. Snooze/alarm display input has an internal pull-down depletion load to VoD. Sleep/seconds display input has an internal voltage control which allows this input to assume three input states. The sleep time can be displayed by connecting pin 11 to Vg and seconds can be displayed by con- necting pin 11 to Vpp, and if pin 11 is left open, formal time is displayed. If more than one mode is selected, the priorities are as noted in Table I. As shown sama [= snd Pena ‘Order Number MMIS325N or MMB3B5N ‘See Package 24 in Figure ? the code converters receive time, alarm and sleep information from appropriate points in the clock circuitry. The display mode select inputs contro! the ‘gating of the desired data to the code converter inputs and ultimately (via output drivers) to the display digits. Time Setting Inputs (pins 9 and 10): Both fast and slow setting inputs are provided, These inputs are applied either singly or in combination to obtain the control functions listed in Table II. Again, internal depletion loads to VoD. are provided, application of Vgg to these pins affects the control functions, Note that the control functions proper are dependent on the selected display mode. For example, @ hold:time control function is obtained by selecting seconds display and actuating the slow set input, As another example, the clock time may be reset to 12:00:00 AM (midnight), in the 12-hour format {0:00:00 in the 24hour format), by selecting seconds display and actuating both slow and fast set inputs. Alarm Operation and Output (pin 16); The alarm com: parator (Figure 1) senses coincidence between the alarm counters (the alarm setting) and the time counters {teal time). The comparator output is used to set a latch in the alarm and sleep circuits. The latch output enables ‘the open drain alarm output driver to control the external alarm sound generator, The alarm latch remains set for 59 minutes, during which the alarm will therefore sound if the latch output is not temporarily inhibited by another latch set by the snooze alarm input (pin 17) for reset by the alarm “OFF” input (pin 15). Snooze/Alarm Display (pin 17): Momentarily connecting pin 17 to Vgg inhibits the alarm output for between 8 and 9 minutes after which the alarm will again be sounded and display alarm time. This input is pulled- down to Vpp by an internal depletion load. The snooze alarm feature may be repeatedly used during the 59 minutes in which the alarm latch remains are set; con: necting pin 17 0 Vg displays alarm time enn Order Number MMIS396N or MME3B7N FIGURE 2functional description (continues) Alarm “OFF” Input (pin 15): Momentarily connecting pin 15 to Vg resets the alarm latch and thereby silences the alarm. This input is also returned to Vop by an internal depletion load. The momentary alarm “OFF” input also readies the alarm latch for the next comparator ‘output, and the alarm will automatically sound again in 24 hours (or at a new alarm setting). [fit is desired to silence the alarm for a day or more, the alarm “OFF” input should remain at Vgg. FIGURE 3. 50/60 He Input Shaping Circuits Sleep Timer and Output (pin 14): The sleep output at in 14 can be used to tum off a radio after a desired time interval of up to 59 minutes, The time interval is chosen by selecting the sleep display made (Table 1) and setting the desired time interval (Table Il), This automatically results in a current-source output via pin TABLE | MM3a5, mN5386, 14, which can be used to turn on a radio for other appliance}. When the sleep counter, which counts down: wards, reaches 00 minutes, a latch is reset and the sleep output drive is removed, thereby turning off the radio, This turn off may also be manually controlled (at any time in the countdown) by a momentary Vgg connec: tion to the snooze input (gin 17) Segment Outputs (pins 1—6 and 20-40); All seqment Outputs are open drain devices with all sources con nected to Vgg. Each segment output may source direct current of 18 mA at 2V on the output device, Figure 5(b) shows the output resistence (RON) of segment driver with respect to Vpp. Power Failure Indications: Power failure indication is shown by the flashing of all “ON” digits at 1 He rate, A fast oF slow set input resets an internal power failure latch and returas the display to normal. The power failure latch trips into the power failure mode prior to the loss of data stored in the time latches. When powered up, alarm and sleep outputs will be in the OFF" state. In order to assure guaranteed power {ail indication, power supply rise time should not exceed 10 V/ms. LED CURRENT CONTROL INPUT AND REFERENCE OUTPUT (PINS 19 AND 18) Pin 18 controls the gate voltage at all the display outputs ‘and the reference device. The output drivers can be disabled by connecting pin 18 to Vgs. This wire-OR capability allows the display to be used for other func: tions (eg., temperature, radio frequency wavelength) MM5396, IM5397 Display Modes *SELECTED ' ae DIGIT NO. pisitno.2 | oicitno.a | picitNo, Tine Diapay 10st House AMPH | Hows Teor minster | Minter Seconds Oispey | Blanked Mioutes wosorseconas | seconds ‘Alem Display HO'sot Hous Baw | Hours rosot mines | Minutes Sleen Disoloy Bianked Blanks eof minutes | Minutes “If more than one display mode mput 's applied, the display priorities are inthe order of Sleep (overrides all others), Alarm, Seconds, Time (no other mode selected) ‘TABLE II. MMS385, M5386, MMS396, MIIS397 Setting Control Functions SELECTED | CONTROL pispLav mone | INPUT eee “Time Siow Minutes Advance at 2 He Rate Fast Minster Advance at 60 He Rate Bath Minutes Advance at 60 He Rate Alarm Siow Alarm Minutes Advance at 2 He Rate Fast Alarm Minutes Advance at 6D He Rate oth Alarm Roses to 12°00 AM (Midnight) (MMSI@5, MIMSIB6) Btn ‘Alarm Reyet 0 0:00 (§M535, MME397) Seconds Stow Input to Eacke Time Counter ¢ Inhibited (Hold) Fast Steonds and 10's af Seconds Reset to Zera Without 2 Carry to Minutes Beth ‘Tiese Resets to 12:00:00 AM (Micnight) (MMSBR5, mM5396) anim ‘Time Resets to 0°00:00 (M5385, 11M5307) sleeo Slow ‘uotacts Count at 2 He Fast Subtrecte Count at 6 He Barn ‘Subtracte Count at 60 He ‘When setting time sleep minutes will decrement at rate of time counter, until the sleep counter reaches OD minutes (sleep counter will not recycle 159 L6ESWIW ‘96ESWW “98ESWW ‘SSESWWMM5385, MM5386, MM5396, MM5397 functional description (continues) The output current can be controlled two ways: 1) driving the output in saturated mode; 2) driving the output in linear mode. (Refer to Figures 4 and 5}. 1) The reference device {pins 18 and 19) is connected as a diode, and an external resistor is used to set the desired current in this diode (see Figure 4), The seg: ment drivers of all digits are connected as current mirrors, The drain voltage V1 of the segment drivers is selected such that these devices operate in saturation mode. Since the drain current variation in saturation made operation of the MOS device is relatively constant, the segment drive current does not vary significantly, even though V1 is increased considerably, However, a the voltage across the output butters increases, average power dissipation also increases linearly, ‘This technique of current control is recom mended to be used only with low current LEDs (1-7 mal. FIGURE 4(e). Low c FIGURE 5{o). High Current LED Drive Control Ci it LED Drive Control Cireult (1—7 mA 2) The high current drive requirement of large LED displays can be accomplished by operating the segment drivers in the linear mode, The circuit for high current LED drivers is shown in Figure 5, The reference output device is used in series with a reference LED, diode and ‘current setting resistor. A high beta PNP transistor provides the current drive for all the segments. A refer fence voltage V3 is developed which compensates for variations in MOS process parameter and the variations in the voltage drop across the LED. The resistor sets the current in the reference LED which sets the reference voltage V3. This in turn sets the current in the LEDs equal to resistor current less the base current of the transistor. Variation in second supply voltage does not vary the LED currents so long as the PNP transistor is kept operating in the linear mode. Full wave rectified power supply without any filtering can be used as a second supply voltage V2. The LED brightness can be varied by using a variable resistor. | aa Bet FIGURE 4(b). Segment Cu (vpp +t 16V) (Typical Output Characteristics) ) T Sta pal enn gone 3S ee “ois a0 asa Von (REFERENCED 10 V9) FIGURE 5{b). Row v* Vop (Vos at ~1VP (Typical Output Characteristics)functional description (continues! Figure 6 shows & LEO drive circuit which uses a single resistor. The resistor controls the total current flowing through all the segments. Brightnoss shal vary depending Con number of segments that are on at that time FIGURE 6, Simole LED Drive Circuit Radio Frequency Interference: All display outputs include circuitry to slow up the switching transition time to minimize radio frequency interference. Me FIGURE 7. 11n vs Vin (Typical Input Depletion Load Characteristics) | lesa ! 4 Te Vd | eal a iF J 4 FIGURE 8, General Purpose Alarm Clock Using the MMS3ES or M5396 and LED Display 161 L6ESW ‘96ESWW “O8ESWIW ‘SsesAWMM5387AA, MM53108 Clocks MM5387AA, MM53108 digital alarm clocks general description features The MUSSETAA, MMSSI00 dit) arm docks ne H00r 60H operation Sec eons 1 oe eens required to build several types of clocks and timers aaa with up to four display modes (time, seconds, alarm Leading-zero blanking eee Gi agt) ‘nth eee aking MABR ton and Wnting exon, 30 how eee ee Scie ns aaa cereccamruie erlang pamela 24-hour alarm setting Alll counters are resettable Fast and slow sot controls Power failure indication Elimination of illegal time display at turn “ON” Direct interface to LED displays 9-minute snooze alarm Tho MMS3108 is electrically identical to tre @PPlications MMB387AA, but with mirror-image pin-out to facilitate Alarm clocks PC board layout when designing a “module” where the LED display and MOS chip are mounted on the same side: the MMS5387AA is more suited for “L” shaped module designs (vertical LED display, horizontal com ponent board), Both devices are supplied in a 40lead dual-in-line package © Portable clocks Desk clocks = Photography timers Clock radios = Industrial timers Automobile clocks © Appliance timers Stopwatches . Industrial clocks Sequential controllers block diagram a) a Note. MIM53108 pin connections shown in parenthesis FIGURE 1-62absolute maximum ratings Voltage at Any Pin Except Segment Outputs Voltage at Segment Outputs Operating Temperature Storage Temperature Lead Temperature (Soldering, 10 seconds) electrical characteristics Ta within operating range, Vsi Vgg + 0.3 to Vgg ~ 30V Vgg + 0.3 to Vgg ~ 18V ~25°C to +70°C 65°C to +150°C 300°C 24V-26V, Vp = OV, unless otherwise specified, PARAMETER CONDITIONS MIN typ | Max UNITS Power Supply Voltage Output Driving Display 24 26 v Functional Clock 8 26 v Power Supply Current No Output Loads Vsg= 8V 4 mA Vss= 26V 5 mA 50/60 Hz Input Frequency Voltage Vgg = 8V to 26V ae | 800r60) 10k Hz Logical High Level vss1 | Vss | Vss v Logical Low Level Yoo | Yoo | Yoot2 v Input Leakage 100 uA All Other Input Voltages Logical High Level vss-1_ | Vss Vss. v Logical Low Level Internal Depletion Load to Vop | Yoo | vpp | Vss-6 v Power Failure Detect Voltage [Vgg Voltage}, (Note 2) 1 75 v Count Operating Voltage 8 26 v Hold Count Voltage (Note 2 26 v Output Current Levels Vg = 24V to 26V, Output Comman = Vgg 10's of Hours (b & c), 10's of Minutes (a&d) Logical High Level, Source Vou = Vgs - 4V 16 mA Logical Low Level, Leakage VoL = Vss - 14V 10 WA 1 He Display Logical High Level, Source VoH= Vss- 4 24 mA Logical Low Level, Leakage Vou = vss — 14 10 WA All Other Displays Logical High Level, Source Von = Vss — 4V 8 (Note 1) mA Logical Low Level, Leakage VoL = Vss ~ 14V 10 uA Alarm and Sleep Outputs Vgg = 24V Logical High , Source Vou = Vss - 2 500 uA Logical Low, Sink Vou = vss ~2 1 BA [Note 1: Segment output current mast be limited ta. 11 mA maximum by us an 26°C. Power dissipation must be limited to 900 mW at 70°C end 1,20 Note 2: The power fail detect voltage is 0.6V or more above the hold count voltage, The power-fal latch tris into power fail mode at least 0.6V ‘bove the voltage at which data stored inthe time latch i lost SOLESWW ‘VVL8ESWWMM5387AA, MM53108 functional description A block diagram of the MM5387AA, MMS3108 digital ‘lock radio circuit is shown in Figure 1. The various display setting mades are listed in Table |, and Table It shows the setting control functions. The following description is based on Figure 1 and refers to both devices as they are electrically identical. 50 oF 60 Hz input: A shaping circuit (Figure 3) is pro vided to square the 0 or 60 Hz input. This circuit allows use of a filtered sinewave input. The circuit is a Schmitt trigger that is designed to provide about 6V of hysteresis, A simple RC filter such as shown in Figure 7, should be used to remove possible line-voltage tran sients that could either cause the clock to gain time or damage the device. The shaper output drives a counter chain which performs the timekeeping function, 50 or 60 Hz Select Input: A programmable prescale counter divides the input line frequency by either 50 or 60 to obtain a 1 Hz time base. This counter is programmed to divide by 60 simply by leaving 5O/ 60 Hz select unconnected; pull-down to Vpp is pro: vided by an internal depletion load. Operation at 50 Hz is programmed by connecting 50/60 Hz select to Vss Display Mode Select Inputs: In the absence of any of these three inputs, the display drivers present time-of day information ‘to the appropriate display disits Internal depletion pull-down devices allow use of simple ‘SPST switches to select the display mode. If more than ‘one mode is selected, the priorities are as noted in Table |. Alternate display modes are selected by apply: Vgg to the appropriate pin. As shown in Figure 1 the code converters receive time, seconds, alarm and sleep information from appropriate points in the clock circuitry, The display mode select inputs control the connection diagrams Dun tn tine Package ra was 2a. => couom cm) ‘net [Be tnnennsecr ss fe sernesecer vasa rasraet wnt ws -+ 4 2E sean ogra at sons +2 2 an ona ut OMS. ‘ma a SLEEP DISPLAY INPUT vomins -2 2. scree oureur sauna paar wut sins» [= sxotze ur tans = [2 outa como ssunee was wins wns yO se ‘Order Number MMS387AAN See Package 24 FIGURE 2(a). MM5387AA gating of the desired data to the code converter inputs and ultimately [via output drivers} to the display digits. Time Setting Inputs: Both fast and slow setting inputs are provided, These inputs are applied either singly or in combination to obtain the control functions listed in Table II, Again, internal deptetion pull-down devices are provided; application of Vgg to these pins affects the control functions, Note that the control functions proper aro dependent on the selected display mode. For example, a hold-time control function is obtained by selecting seconds display and actuating the slow set input. As anothar example, the clock time may be reset, to 12:00:00 AM, by selecting seconds display and actu: ating both slow and fast set inputs. Output Common Source Connection: All display out ut drivers are open-drain devices with all sources common (Figure 4a). The common source pin should be connected to Vss, 12 oF 24 Hour Select Input: By leaving this pin uncon: nected, the outputs for the mostsignificant display digit (10's of hours) are programmed to provide a T2hour display format. An internal depletion pull down device is again provided. Connecting this pin to Vss programs the 24hour display format. Segment connections for 10's of Hours in 24-hour mode are shown in Figure 6, Power Fail Indication: If the power to the integrated circuit drops, indicating a momentary ac power failure ‘and possible loss of clock, all “ON” segments will flash at 1 Hz rate. A fest or slow set input resets an internal power failure latch and returns the display to normal. Dusl-In-Line Package uourrur smaurrur avons aa] owns =e raenmsueer ns ot [as © ALAR PLAY UT sews SLEEP SPLAT UT ss saan suesraurrur 2 sows + D oy wins —« 3 EE ns 5 Nurmber MMSSTOBN ‘See Package 24 DurPur conway source Ns or FIGURE 2(b). MMS3108 (Mirror Image Pin-Out) 164functional description (continues) Alarm Operation and Output: The alarm comparator (Figure 1) senses coincidence between the alarm count: {rs (the alarm setting) and the time counters (real time) ‘The comparator output is used to set 2 latch in the alarm and sleep circuits. The latch output enables the alarm output driver (Figure 4b) which is used to contral the external alarm sound generator, The alarm latch remains set for 69 minutes, during which the alarm will therefore sound if the latch output is not tempor arily inhibited by another latch set by the snooze alarm input or reset by the alarm “OFF” input. Snooze Alarm Input: Momentarily connecting snooze to Vgg inhibits the alarm output for between 8 and 9 minutes, after which the alarm will again be sounded This input is pulled-down to Vp by an internal deple. tion device. The snooze alarm feature may be repeatedly used during the 69 minutes in which the alarm latch ramains set Alarm “OFF” Input: "OFF! Momentarily connecting alarm to Vsg resets the alarm latch and thereby 4 4 silences the alarm, This input is also returned to Vop by ‘an internal depletion device. The momentary alarm “OFF” input also readies the alarm latch for the next comparator output, and the alarm will automatically sound again in 24 hours {or at @ new alarm setting) If it is desired to silence the alarm for a day or more, the alarm “OFF” input should remain at Vg. Sleep Timer and Output: The sleep output can be used to turn "OFF" radio after a desired time interval of up to 59 minutes. The time interval is chosen by selecting the sleep display mode, (Table 1) and setting the desired time interval (Table II}, This automatically results in a ‘current-source output which can be used to turn "ON" a radio (or other appliance). When the sleep counter, Which counts downwards, reaches 00 minutes, a latch {s reset and the sleep output current drive is removed, thereby turning "OFF" the radio, This turn “OFF” ‘may also be manually controlled {at any time in the countdown) by a momentary Vgg connection to the Snooze input. The output circuitry is the same as the other outputs (Figure 40). sorsome *ettectively FIGURE 3. 50/60 H2 Input Shaping Circuit a {ore onan FIGURE 4{a). Seoment Outputs vs. nou. FIGURE 4(b). Alarm and Sleep Outputs 65 SOLESWN ‘VVZ8ESWNMM5387AA, MM53108 functional description (continued) TABLE I, MMSS87AA, MM53108 Display Modes SELECTED aye o1GIT No.1 oisitno.2 | oiitno.a | v1ciTNo.4 Tire Display TOsol wows wawiPR | Howe TWsof Minwes | Minutes Seconds Ospiay | lankes Minutes 1Wsot Seconds | Seconds ‘Alarm Display rosot Hours wamien | Hous rect Minter | minvtes ‘Sleep Display Blankes Blanked torsot minutes | stinutes *1f more then one display mode input i applied, the display priorities are in the order of Sleep (overcides allothers, Alarm, Secengs, Time Ino other mode selected) ‘TABLE I MMS387AA, NNMG2108 Setting Control Funetions SELECTED | CONTROL INTROL FUNCTION pispLay move | INPUT eee “Time Slow ‘Minutes Advance at 2 Hi Rate Fast Minutes Advance at 6D He Rate fot Minutes Advance at 6D H7 Rate Alarm Siow Alarm Minutes Advance at 2 Hr Rate Fast Alarm Minutes Adkoncs at 60 Hz Rate Bott ‘arn eset to 12.09 AN (Midnight) (12 Hour Format Boh Alm Reset 1 00:00 (24 Hour Forenat) Seconds Siow Input to Entire Time Counter Inhibited (Hold) Feat Steonds and 10's of Seconds Reset to Zero Without 2 Canty to Minutes Bomm Tioe Reset to 12:00:00 AM [Midright (12 Hour Forman Both ‘Time Resets te 00:00:00 (28-Hour Fosmat) Step Siow Suntracte Count at 2 He Fast Subtrcts Count st 6D He Both Suutracts Count st 69 Me ‘Winen setting time sleep minutes will decrement st te of time counter, until the sleep counter reaches 00 minutes Isleep counter will not recycle) OUTPUT ORAIMH VOLTAGE BELOM sg FIGURE 5. Typical Output Current CCharacteristies of MMS387AA, MM53108 Switch A must be ganged with Sleep display as shown, FIGURE 6. 24-Hour Operation 10's of Hours Digit Connsetionstypical applications Figure 7 is a schematic diagram of 8 general purpose alarm clock circuit (12-hour mode) using the MMS3B7AA or MME3108 and a 3 1/2-digit LED display. epee Ph ee SOLES ‘VVL8ESWW a SoS otra SSC cane “ur MOE . Seq FIGURE?MM5402, MM5405 Clocks MM5402, MM5405 digital alarm clocks general description The MM5402, MMS405 digital alarm clocks are mono: lithic MOS integrated circuits utilizing N-channel low-threshold, enhancement mode and ion-implanted depletion mocle devices. They provide all the logic required t0 build several types of clocks end timers with up to four display modes (time, seconds, alarm and sleep) to maximize circuit utility, but are speciti= cally intended for clock-radio applications. Both devices will diectly-drive 7-segment LED displays in either a T2hour format (3 1/2 digits) with lead-zero blanking, AMI/PM indication and flashing colon, or 24-hour format (4 digits) through hard.wire pin selection; the timekeoping function operates from either a 50 or 60 Hz input, also through pin selection. Outputs consist, of display drivers, sleep (e.g, timed radio turn-off), and alarm enable. A power-fail indication mode is provided 10 inform the user of incorrect time display by flashing all "ON" digits at a 1 Hz rate, and is cancelled by simply resetting time, The device operates over a supply range of 7V—11V which does not require regulation. ‘The MMS405 is electrically identical to the MMS402, features 50 oF 60 Hz operation Single power supply 12 oF 24 hour display format AM/PM outputs Leading-zero blanking 24-hour alarm setting All counters are resettable Fast and slow set controls Power failure indication Elimination of illegal time display at turn Direct interface to LED displays Gminute snooze alarm ON Presettable 59-minute sleep timer Available in standard (MM5402} or mirror-image (M5408) pin-out applications but with mitrorimage pinout to fecitate PC board ® Alarm clocks Portable clocks layout when designing a “module” where the LED mw Desk clocks = Photography timers Giplay and MOS chip ave mourited on the same sid&; ey fonts dustrial timers the MM5402 is more suited for ‘'L" shaped module : pee te _ designs (vertical LED display, horizontal component Automobile clocks | Appliance timers boord). Both devices are supplied in a 4Olead duatin- Stopwatches Sequential controllers line package Industria clocks block diagram ce) nopeim atin F+[ttia | [alia] BBD) eae” sone 2 AEE Cam iets > a cane i Note. MM540S pin connections shown in parenthesis, FIGURE 1 168absolute maximum ratings (wore 1) Voltage at Any Pio Vs 19 V5 +12¥ Lend Temperature (Soldering, 10 seconds) 300°¢ Operating Temperatura 25 C10 s70.C Segment Output Current Note + Storage Temparature 85 C10 H150°C electrical characteristics Ta within operating range, Vop = 7V to 11V, Vs. V, unless otherwise specified, PARAMETER ‘CONDITIONS MIN TP MAX UNITS Power Supply Veltage ‘Output Driving Display Q 7 v Functional Clock 7 n v Power Supply Current No Output Loads vop-7v 4 mA voo= nv 5 mA 50/60 Hz Input Frequency Yoo = Vw tv ae 50 0 60 10% He Logica! Low Level vss vss Vss+05 v Logical High Lovet Voo-3 Yoo Voo v Input Leakage 100 HA Al Other Input Voltages Logica! Low Love Vss vss Vss*05 v Logical High Levet Inexnal Depletion Load to Vo voo-3 vop Voo v Power Failure Detect Voltage (Wop Votagel, Note 2) , 5 v Count Operating Voitage 7 " v Hole Count Voltage (Nowe 2) u v Ales and Siaep Outputs Voo= nv Lovie High, Source Vou ss +? 1 uA Logical Love, Sink Vou =Vss +2 5 ma ‘Ourput Currant Levels Yoo = 9v1011V, Output Comman = Vsg Common Anode (Figure 50) 10's of Hours th & e}, 10's of Minutes aa) Logical High Level, Lekaoe Vou = Yoo 10 BA Logical Low Level, Sink Vou = vgs 2v 24 mA 1 He Display Losi! High Level, Leakage Vou=Voo 0 BA Lopica! Low Level, Sink Vou ~ vss + 2V 36 mA [All Other Segment Displays Logical High Level, Leakane Vou=Voo 10 A Logical Low Lovo, Sink Vou = Vss +2 2 ma ‘Output Current Levels (Note 1) Output Common = Vgs + 4 Common Cathode (Figure 50) 10's of Hours (o & cl, 10° of Minutes aa) Logical High Level, Source Vou = Vss + 1.5V 20 ma Lopical Low Level, Leskage Vou * vss 10 HA 1 He Display Logis! High Level, Source Vou * ss + 1.5 30 ma Logical Low Level, Leakage Vou * Vss 10 ua All Other Segment Dieplays Logica High Level, Source Vou = Vsg + 1.5 10 mA Logical Low Level, Leakage Vou. = vss 10 uA ‘Note 1: Segment ourput current must be limited to 18 mA maximum By User; Rowe? Gisipation must be Umnted Yo O00 mW a TOC end TaN atZ5°C, Note 2: The power-fal detect voltage is 0.25V or moro above the hold count voltage. The powwer-fail latch tsps into power-feil mode at least (0.25V above the voltage at which data stored inthe time latch i lost Note 3: Power supply voltage should not exceed @ maximum voltage of 12V under any circumstances, such as during plugin, power up, splay "ON"/"OFF™. oF power supply ripple. Doing to runs the rick of permanently damaging the device, 169 SOVSINW ‘ZOvSWIWMM5402, MM5405 functional description A block diagram of the MM5402, MMS405 digital clock radio circuit is shown in Figure 7. The various display setting modes are listed in Table I, and Table II shows the setting control functions. The following description is based on Figure 1 and reters to both devices as they are electrically identical 50 of 60 Hz Input: A shaping circuit (Figure 3) is pro: vided to square the 50 or 60 Hz input. This circuit allows use of a filtered sinewave input. The circuit is a Schmitt trigger that is designed to provide about O.8V hysteresis. A simple RC filter such as shown in Figure 7, should be used to remove possible line-voltage transients that could either cause the clock to gain time or damage the device, The shaper output drives a counter chain which performs the timekeeping function. 50 or 60 Hz Select Input: A programmable prescale counter divides the input line frequency by either 50 or 60 to obtain a 1 Hz time base. This counter is programmed to divide by 60 simply by leaving 50/ 60 He select unconnected; pull-up to VOD is pro: vided by an internal depletion load. Operation at 50 Hz is programmed by connecting 50/60 Hz select to Vss. Display Mode Select Inputs: In the absence of any of these three inputs, the display drivers present time-ot day information ‘to the appropriste display digits, Internal depletion pull-up devices allow use of simple ‘SPST switches to select the display mode. If more than ‘one mode is selected, the priorities are as noted in Table |, Alternate display modes are selected by apply ing Vsg to the appropriate pin, As shown in Figure 1 the code converters receive time, seconds, alarm and sleep information from appropriate points in the clock circuitry. The display mode select inputs control the gating of the desired data to the code converter inputs and ultimately (via output drivers) to the display digits. connection diagrams (Top Views) Dua Anine Package vas -1 = Bane nnsecr a anon wns = s0160 as neu HRS —« = sow ser nPuT vOMINS ~ 9 aoe SLEEP DISPLAY INPUT ‘ens os samns - Lan -oFF° NPoT ns 1 aanwaureur ‘Number MM54O2N ‘Seo Package 24 FIGURE 2(a), MMS402 Time Setting Inputs: Both fast and slow setting inputs are provided. These inputs are applied either singly of in combination to obtain the control functions listed in Table Il, Again, internal depletion pull-up devices ‘are provided; application of Vgg to these pins affects the control functions. Note that the control functions proper are dependent on the selected display mode. For example, a hold-time control function is obtained by selecting seconds display and actuating the slow set input. As another example, the clack time may be reset to 12:00:00 AM, by selecting seconds display and actu- ating both slow and fast set inputs Output Common: All display output drivers are open drain devices with all the sources connected to output ‘common pin. This pin can be used as a common source ‘or 8 common drain. When used as @ common source, this pin is connected to Vg and when used as a com mon drain, this pin is connected to Vp: This allows the use of either common anode or common cathode LED's for displays. Figure § shows these connections, 12 or 24 Hour Select Input: By leaving this pin uncon ected, the outputs for the most-significant display digit (10's of nours} are programmed to provide a 12hour display format. An internal depletion pull up device is again provided, Connecting this pin to Vgs programs the 24-hour display format. Segment connections for 10's of hours in 24-hour mode are shown in Figure 6. Power Fail Indication: If the power to the integrated Circuit drops, indicating a momentary ac power failure ‘and possible Joss of clock, all "ON" segments will flash at 1 Hz rate, A fast or slow set input resets an internal power failure latch and returns the display to normal. Dusl-in-Line Package sae nnsecect ane cenni—ey sesoneneur | | secon oisrtay iru SLEEF useLay iT asia oFF* nPuT toms -« tanw auteur ns 1 snooze wut 2 ins 4 ‘ourrut common. = ans ns 3 PE sans + Order Number MMB4O5N ‘See Package 24 FIGURE 2(b). MMS405 (Mirror Image Pin-Outfunctional description (continues) Alarm Operation and Output: The alarm comparator (Figure 1) senses coincidence between the alarm count ers (the alarm setting) and the time counters {real time). The comparator output is used to set a latch in the alarm and steep circuits, The latch output enables the alarm output driver (Figure 4b) which is used to control the external alarm sound generator, The alarm latch remains set for 59 minutas, during which the alarm will therefore sound if the latch output is not tempor: arily inhibited by another latch set by the snooze alarm input of reset by the alarm "OFF" input Snooze Alarm Input: Momentarily connecting snooze to Vig inhibits the alarm output for between 8 and 9 minutes, after which the alarm will again be sounded This input is pulled-up to Vp by an internal deple tion device. The snooze alarm feature may be repeatedly used during the 59 minutes in which the alarm latch Alarm “OFF” Input: "OF: Momentarily connecting alarm to Vgg resets the alarm latch and thereby - Ms a silences the alarm, This input is also returned to Vpp by ‘an internal depletion device, The momentary alarm "OFF" input also readies the alarm latch for the next comparator output, and the alarm will automatically sound again in 24 hours (or at @ new alarm setting) If it is desired to silence the alarm for 2 day or more, the alarm “OFF” input should remain at Vgs. Sleep Timer and Output: The sleep output can be used to turn “OFF” a radio after a desited time interval of up to 59 minutes. The time interval is chosen by selecting the sleep display mode, (Table 1) and setting the desired time interval (Table Il). This automatically results in a current sink output which can be used to turn “ON” 3 radio {or other appliance). When the sleep counter, which counts downwards, reaches 00 minutes, a latch is reset and the sieep output current drive is removed, thereby turning “OFF” the radio. This turn “OFF” may also be manually controlled (at any time in the countdown) by a momentary Vss connection to the Snooze input. The output circuitry is the same as the other outputs (Figure 4b), FIGURE 3. 50/60 Hz Input Shaping Circuit > oureur Toren onan FIGURE 4(a). Segment Ourputs wud FIGURE 4b). Alarm and Steep Outputs n SODSWIN ‘ZOrsSWWMM5402, MM5405 functional description (Continued) ‘TABLE 1. M5402, MIM4OS Display Modes eseecr 1 GIT NO. GIT NO. 2 f eae Ici No. picitwo.2 | o1ciT No. DIGIT No.4 Tie Ousplay TWsot Hous &awipm | Hows Wee! Minutes | Minutes Seconds Display | Slankes mates weet Seconas | Second Alarm Disolay 10sot Hows &amiem | Hous wot Ainutes | atinutes Steep Display Blanked Biankes wot atinutes | tinutes +11 more than one display made input i applied, the display priorities are in the order of Sleep (overidies allothers, Alarm, Seconds, Time (no other made selected) ‘TABLE Il, MM402, MM5405 Setting Control Functions SELECTED] CONTROL ee oisptay mooe | INPUT : coe ine Sow Winutes Advance at 2 He Fast Winotes Advance at GO He Rate orn unutes Advance 9 6D He Rate Alam Slow Alarm Nhnutes Advance at 2 He Rate Fast utes Advance at 60 He Rte fen Alaun Resets 0 12-00 ANN (Mideugt £12 Hour Format) form ‘Alarm Resets 10.00:00 (24 Hour Foren Secon Siow Input to Entre Time Counter Inbibtad (Ho Fast Stucnds and 10% of Seconds Reset to Zero Yuthout a Carry to Mines fotn “Time Reset to 12:00:00 AM (Midnight (12 Hour Format) Born ‘Time Resets © DO.00-09 (24:Hour Format Shep Sow Subtrats Gount at 2 Hz a Subtracts Count at 60 He Bor Suttacts Count at 60 He “When setting time sleap minutes wil decrement at rate of time counter, until the sleep counter seaches 00 minutes Is FIGURE Sta). Common ‘Anode Application own avove | p counter will pot recycle. aun ronAy 2ene) FIGURE 5{b). Common FIGURE 6. 24-Hour Operation: Cathode Application 10's of Hours Digit Connectionstypical applications Figure 7 is a schematic diagram of 2 general purpose alarm clock circuit {12-hour mode) using the MM5402 or MMS405 .¥ t thy I he t ir FIGURE 7 aL SOVSINW ‘ZOvSWIAN-143, Clocks USING NATIONAL CLOCK INTEGRATED CIRCUITS IN TIMER APPLICATIONS INTRODUCTION The following is @ description of a technique which allows the use of the National MMS309, MM5311, MM5312. and MM5315 clock integrated circuits as timers in industrial and consumer applications. What will be presented is the basic technique along with some simple circuitry and applications. BASIC TECHNIQUE When first approaching the problem of using clock chips for timers, the most obvious technique is to attempt to compare the display data with preset BCD numbers, Because of the multiplexing and number of data bits this technique, while possible, is unwieldy and requires a large number of components. ‘An easier method is to use one or more demultiplexed BCD lines as contro! waveforms whose edges determine timer data. In Figure 1 we examine the 1-bit of the BCD data of the units second time From this waveform we observe @ one second wide pulse every two seconds. If we look at the 4-bit of the 10 minutes digit we find a pulse which is 20 minutes wide and occurs once each hour Figure 3 is 2 chart showing the various pulses and their widths for all digits and the useful 8CD lines. FIGURE 1. 1 Second Pulse Every 2 Seconds ft sewmce ee | FIGURE 2.20 Minute Pulse Every HourBCD PULSERATE PULSE WIDTH BCD PULSERATE PULSE WIDTH 1 Sec Digit 10 Sec Digit 1 Levary 2 sec 1 sec* 1 every 20 sec 10 sec” 2 2 devery min 20 see 4 Levary 10 sec 4 sec 4 Tevery min 20386 BS evary 10 sec 2sec 8 1 Min Digit 10 Min Digit 1 Yevery 2min 1 min® 1 1 every 20 min 10 min? 2 2 every hr 20 min 4 Tevery 10 min 4 min 4 Vevery hr 20 min BT every 10 min 2min 8 Units Hrs Digit (12 Hr Mode) Units Hrs Digit (24 He Mode) 1 every 2 hrs The? 1 1 every 2 hrs Tht 2 2 4 Tevery 12 hrs 4 hes 4 8 ——Tevery 12 hrs 4hes 8 10 Hrs Digit (12 Hr Mode} 10 Hrs Digit (24 Hr Mode) 1 1 1 every 24 hrs 10 hrs 2 Levery 12 hrs hes 2 1 every 24 hrs hrs 4 every 12hes hes 8 tevery 12 hrs hrs “Square waves FIGURE 3 SIMPLE DEMULTIPLEXING In the simple case where, for example, a four hour wide pulse each day is desired, perhaps to turn on lights in the evening, a simple demultiplexing scheme using one diode is shown in Figure 4. When power is applied, the internal multiplex circuitry will strobe each digit until the digit with the diode connected is accessed. This digit will sink the multiplex charging current and stop the multi plex scanning. Thus, the BCD outputs now present the data from the selected digit. The waveforms as previously discussed are presented at the BCD lines, Note that these pulses are negative true for all BCD outputs. ‘An advantage of this type of timer over mechanical types is the elimination of line power drop outs. The Circuit shown in Figure 5 will maintain timing to within 2 few percent during periods of power (ine failure, but automatically return to the 60 H2 line for timing as soon a8 power is restored. MORE COMPLEX APPLICATIONS Where it is desired to maintain the display, or in more complex timing of the “10 seconds every two hours” variety, external demultiplexing shown in Figure 6 can be used. In this figure the BCD lines are demultiplexed with MM74C74 flip-flops. Examining the waveforms of these circuits we see two edges which allow the 10 second each two hours timing. These are differentiated by the NAND and INVERTERS and the first edge sets and the second resets the $-R flip-flop. The output of the flip-flop is ten seconds wide every two hours. By exam ining the edges of the Figure 3 entries any combination Of timings can be obtained with the circuit of Figure 6, LOW FREQUENCY WAVEFORM GENERATION ‘The asterisked BCD lines in Figure 3 are those wave: forms which are symmetric, By the use of the simple diode demultiplexing scheme previously discussed we 178 evlNvAN-143 FIGURE 4 T = tao FIGURE 5, Fail Sate Automatic Lights Timer. Four Hours Each 24 Hours easily obtain square waves with periods of two seconds, two minutes, twenty minutes and two hours. In other ‘cases, where the waveforms are asymmetric, a simple flip-flop can square, while dividing by two, these wave: forms producing other low frequency square waves 3s long as one per two days. SUMMARY We have shown some simple Jow cost timer and waveform generating examples using National clock integrated circuits, Because of the vast number of timing applica: tions possible, this can in no way be looked at as the limit of clock-timer circuits. Use of the Reset on the MM5309 and MM5315 or the use af clocks in conjunction with programmable counters such as the MM74C161 allows other possibilities to meet specific applications, Also the clock chips themselves can run on frequencies other than 50 or 60 Hz (actually from de to 10 kHz) which can allow scaling of the waveforms presented in Figure 3 to different timing rates,AN-143, UUxMM5307 MM5307 baud rate generator/programmable general description The National Semiconductor MM5307 baud rate generator/programmabie divider is a MOS/LSI P-channet enhancement mode device. A master clock for the device is generated either externally or by an on-chip crystal oscillator (Note 4). An internal ROM controls @ divider Circuit which produces the output frequency. Logic levels on the four control pins select between sixteen output frequencies. The frequencies are chosen from the following possible divisors: 2N, for 3 < N < 2048; 2N +1 and 2N + 0.5 for 4 curr Ms ext cexremuat Dust-n-Line Package exreRnaL FRO nyt sour cava Order Number MMS207N ‘See Packapo 18 22absolute maximum ratings Voltage at Any Pin With Respect to Vgg, +0.2V to Vgg - 20V Power Dissipation 700 mw Storage Temperature Range 65°C 10 +150°C Operating Temperature OC 10 +70°C . Lead Temperature (Soldering, 10 seconds) 300°C de electrical characteristics TA within operating range, Vgg = 8V *5%, Vgg 12V £5%, unless otherwise specified, PARAMETER CONDITIONS MIN TYP. max | UNITS All Inputs (Except Crystal Pins} vin Logical High Level Vs5-15 vgst0.3 v vit Logica! Low Levet Vgg-18 Vss~4.2 v Leakage VIN = ~10V, Ta= 25°C, 05 uA All Other Pins GND Capacitance Vin = OV, f= 1 MHe, 70 pF All Other Pins GND, (Note 1) External Clock Outy Cycle 40% 60% Capacitance Measured Across Mz, (Note 3) 50 pF Crystal Pins Output Levels Vou Logical High Level ISOURCE = -0.5 mA Vss-26 vss v Vou Logical Low Level sink = 1.6 ma, Vss-4.6 v 1G __ Power Supply Current f= 1 Mie 35 mA ac electrical characteristics Ta within operating range Vg = SV *5%, Vgg = —12V 5%, unless otherwise specified PARAMETER, CONDITIONS MIN Ty max | units Master Frequency 0.01 10 ne ta Access Time CL = 50 pF, (Note 2) 16 us tRD Reset Delay Time { + Master Clock Frequency 500 + 4/¢ ns Rew eset Pulse Width 500 + 4/¢ ns top Output Delay From Reset 500 + 4/¢ a Ovtpur Duty Cycle = 0811 | T= Output Period ost ostet f= Master Frequency ‘Note 1: Capacitance is guaranteed by periodic measurement. [Note 2: Access cime is defined 2s the time from a change in control inputs (A, 8, C, 0) to. stable output frequency. Access time iso function of frequency. The following formula may be used to ealeulate maximum sccess time for any master requuncy Ta = 28s 1/1 x43, {isin Mite [Note 3: The MMS207 is designed to operate with 3 1 MHz parallel resonant crystal. When ordering the erystal 8 value of load capacitance (CL) ‘mast be specified, This i the capacitance “seen” by the crystal when it is operating inthe circuit. The value of Cy should match the capecitance measured at the crystal frequency across the erystol input pins on the MMSIO7. Any mismatch will be reflected os very small error ih the ‘operating frequency. To achieve maximum accuracy, it may be necestary to adda small trimmer capacitor acroks the terminals, Note 4: If the crystal oscillator is used Pin 5 (external clock! is connected to Vg. If an external clack is used Pin 7 ¥ connected to Vs 23 LOESIWMM5307 ee Doe control table Input Freq: 921.6 kHz Master Clock NOMINAL BAUD RATES ee (ouTPuT FREQUENCY/16)_|OIVISOR A B c D Aa AB FAG ae Oo to 50 so | 1152 Gof ol 200 75768 0 0 64 tf no t0 | aa o 610-0 | 1345 13451385 | 4285 Of 0 |e co ee | cea o 1 1. 0 | 300 300-300 | 382 o 1 1 1] 600 600-600 | 86 1+ 0 0 0 | 900 900 ©1050 |} 6a 1 0 0 1 | 1200 1200 1200 | 48 1 0c | eo toe | 1 0 + 1 | 2400 2400 2400 | 24 + 1 0 0 | 3600 3600 © 569 | 16 Ce | ce too aaa |e of | oo o67 | 8 1 1 11 | 9600 9600 9600 | 6 foo EXTERNAL FREQ Poste Logi: 1= Vit onve typical applications Internat Oscitator External Clock Ves ourrur 4+ per 21908 > sour 24timing diagram st TTT TTT TTT TTT TTT TTT TTT TTT TTI IT TTT IT ITTT TTT Ascoo oT THE ARPS or connect tn GRuRREN TES = —— tenon fo exer os — a application hints APPLICATION NOTES The external clock is brought in on pin 6 and pin 7 is 3) Reset (pin 13) must be at Vg to operate. It may be tied to Vsg to enable the external clock input. Pin 6 necessary to take this to GND or VGG to reset the can be left open ROM select circuit. An option is to tie 6 out {pin 14) to external Freq In (pin 1}, if not otherwise used, 1) To use the MM5307 with an external clock, hook 4) An interesting application might use two MM5307's it up as follows: in series to generate additional frequencies, i.e, with fone programmed from the 921.6 kHz co 800 He out, vs a second could divide that by 16 to qve «50 He SOHNE crystal controlled signal pL tortare 5) MMMGOTAA divisors ace on the data sheet, AB divisors , are the same a5 the AA except: 1) Code 0010 is Givideo by 288 ~ 32 kHz out, 200 baud: 2) Code 1110 is divided by 768 ~ 1.2 kHz, 75 baud, ‘The MM5307 does not always generate an output when : the power is up, even though the ascillatar seems to be operating properly. In order to eliminate this problem, Tt it is necessary to reset the chip at power “ON”. This can extent cue be done manually, with a teset signal by a host system, or automatically by using R/C timing elements. The 2) To use a crystal directly reset is done internally, when program inputs change When using an R/C combination for auto resetting the time constant must be several times larger than, that of the power supply. For example, most lab power supplies take at least 0.5 sec for the voltage to reach 90% of full level. A 10 KO resistor and 300 uF capacitor combination should be adequate for most applications. rororet -<0193 0 veg 10 eMaaue rat ‘sclera 25 LOESWWMM5307 application hints (continuea) Yoo 6 EXTERNAL 13) CLOCK RESET 5 MANUAL RESET Vss. POWER SUPPLY TIMING AT POWER UP VOLTAGE =2V RESET THRESHOLD =O5SEC TIME FIGURE 1 26Counters/Timers MM5369 17-stage programmable oscillator/divider general description The MM5369 is a CMOS integrated circuit with 17 binary divider stages that can be used to generare a precise 60Hz reference from commonly available high frequency quartz crystals. An internal pulse is generated by mask programming the combinations of stages 1 through 4, 16 and 17 to set or reset the individual stages, The programmable number the circuit will divide by can vary from 10000 to 98000. The MMS369 is advanced fone count on the positive transition of each clock pulse. Two buffered outputs are available: the crystal fre ‘quency for tuning purposes and the 17th stage 60 Hz ‘output. Mask options are available for use with com monly available, low cost, high frequency crystals Therefore, this design can be “customized” by special ‘order to design specific programmable divider limits whereby the maximum divide-by can be 98,000 and the minimum divideby can be 10,000. The MME369 is available in an 8 lead dual-in-tine epoxy package. features Crystal Oscillator = Two buttered outputs Output 1 eyrstal frequency Output 2 full division High speed (4 MHz at Vop = 10) Wide supply range 3~18V Low Power Fully star eration B lead duat-intine package Low current Standard MM5369N Only = 3.58 MHz (color TV oscillator) input frequency 60 Hz output frequency connection diagram block diagram | sans Tren 1 ow T let sn (Order Number MM5369N ‘See Package 17 69ESNWMM5369 absolute maximum ratings Vottage at Any Pin Operating Temperature Storage Temperature -.3V t0 Vee +0.3V O°C to +70°C 65°C to +150°C Package Dissipation 500 mW Maximum Vcc Voltage 16 Operating Voc Range 3V to 15V Lead Temperature (Soldering, 10 seconds) 300°C electrical characte Ta within operating temperature range, Vss = GND, 3V < Voo S 15V unless otherwise specified. PARAMETER ‘CONDITIONS min | TvP | MAX | UNITS ‘Quiescent Current Drain Vpo= 18V 10 HA Operating Current Drain Voo= 10V, fy = 4.19 MHz 12 25 ma Frequency of Oscillation Voo= 10V oc 45 Miz Voo= 6V pe 2 MHz Output Current Levels Vop= 10V Vour = 5¥ Logical "1" Source 500 uA Logical “0” Sink 500 HA Output Voltage Levels Vop= 10V Jo = 10 ua Logical 90 v Logical “0” 1.0 v functional description A connection diagram for the MMS369 is shown in DIVIDER. Figure 1 and.a block diagram is shown in Figure 2. TIME BASE A precision time base is provided by the interconnection of @ 3,579,545 Hz quartz crystal and the RC network shown in Figure 3 together with the CMOS inverter! amplifier provided between the OSC IN and the OSC OUT terminals. Resistor R1 is necessary to bias the inverter for class A amplifier operation. Capacitors C1 and C2 in series provide the parallel load capacitance required for precise tuning of the quartz crystal. ‘The network shown provides > 100 ppm tuning range when used with standard crystals trimmed for C, 12pF. Tuning to better than 22 ppm is easily ob- sainable ‘A pulse is generated when divider stages 1 through 4, 16 ‘and 17 are in the correct state. By mask options, this pulse is used to set or reset individual stages of the counter, thus varying the modulus of the counter from 10000 ‘to 98000. Figure 4 shows the relationship between the duty cycle and the programmed modulus, OUTPUTS ‘The Tuner Output is a buffered output at the crystal oscillator frequency. This output is provided so that the ‘crystal frequency can be obtained without disturbing the crystal oscillator. The Divide Output is the input fre- quency divided by the mask programmed number. Both ‘outputs are push-pull outputs. A typical application of the MM5369 is shown in Figure 5. 28functional description (cont.) 69ESWAW * ue wow 0 aurv evcie ws FIGURE 3. Crystal Oscillator Network FIGURE 4, Plot of Divide-By Vs Duty Cycle = Uo ff 7 Yeo kl F1QURE 6, cock Radio Gru with Battery BackUp FIGURE 6. Type Currant Orin V Otto Frequency FIOURE 7. Outs veer for tnd MME "To be selected bated on xtal used 29MM5865 ta MM5865 universal timer general description The MMS865 Universal Timer is a monolithic MOS integrated circuit utilizing P-channel low-threshold, enhancement mode and ion-implanted depletion mode devices, The chip contains all the logic required to control the two 4:digit counters, blank leading zeros, ‘compare the two counters and to cascade with another MM5865, Input pins start, stop, reset and set the counters, determine which of the 7 functions is per- formed, the resolution of the display (0.01 sec, 0.1 sec, 1 sec, or external clock} and what modulo the counters divide by. Outputs include the comparator output, multiplexed BCD outputs and digit enables, The BCD outputs interface directly with MM14511, a BCD to 7-segment decoder, which interfaces with a LED display. The digit enable outputs of 2 cascaded MMSB65’s interface directly with a DM8863 LED B-digit driver. A DS8877 or DS75492 Hex Digit Driver may be used with a single MMS865. The digit enable outputs inter: face directly with a DM8863, 2 LED digit driver. The 7 functions include startstap with total elapsed time, start-stop with accumulative event time, split, sequential with total elapsed time, rally with total elapsed time program up count and program down count. The circuit uses a 328 kHz crystal or an external clock and is packaged in a 40-lead dual-in-line package applications Stop watch Kitehen timer ‘Oven timer Rally timer = Event timer/counter = Navigational timer Industrial vimer/eounter Counters/Timers Foe additional application information, see AN-188 and AN-169 at the end of this section. features Function 1:Standard Start-Stop with total elapsed time memory Function 2: Standard Start-Stop with total accumu: lative event time Function 3: Sequential memory with total elapsed time Function 4: Standard split Function 5: Rally with total elapsed time memory Funetion 6: Programmable up count. Repeatable upon command Function 7: Programmable down count Comparator output Crystal controlled oscillator (92.8 kHz) External clock input (option) Provides external clock Select resolution Select count up or down Select modulo 6 oF 10 for digits 2, 3 and 4 Blanking between digits ‘Leading-zer0 blanking Multiplex rate output External multiplex rate input {option) Can be cascaded \Waiting state indicator Simple interface to LED display Elimination of illegal time display at turn-on Wide power supply range 7V-20V block and connection diagrams Dusn-Line Package aan on ee ee age = | 4 oon] scayrge Tt Order Number MMSA65N seu 2 ‘See Package 24 210absolute maximum ratings Voltage at Any Pin Ves + 0.3V to Ves ~ 25V Operating Temperature 28°C to +70°C Storage Temperature 65°C to +150°C Lead Temperature (Soldering, 10 seconds) 300°C electrical characteristics Ta within operating range, 7V < Vag < 20V, Vp = OV, unless otherwise specie. PARAMETER CONDITIONS min | tye | max | units lop Power Supply Current 7 15 mA Input Frequency at OSC IN dc 328 | 60 kHz Multiplex Frequency Ves > 10 de 04 20 kHe Blanking Frequency de 08 10 kHe Clock Frequency Ves = 7V de oa 10 kHz Veg = 10V de 100 kHz Input Levels Input Logic Low Internal Resistor Voo Voo+t v Input Logie High ~100k t0 Vo Vso 1 Ves v OUTPUT CURRENTS Digit and BCD Outputs Ves = 7V Source Current Vour = Vss -2V 1 mA Sink Current Vour * Vss ~ 6.3V 1 HA Blanking Output Vss = 7V Souree Current Vour = Vss ~2V 1 | mA Sink Current Vour * Vss ~ 6.3V 1 BA Multiplex Output Vss = 7V Source Current Vour * Vss ~2.8V 500 HA Sink Current Vour = Vee ~6.3V 8 aA Clock Output Vss = 7V Source Current Vour = Vss ~4V 10 ah Sink Current Vour * Vss -6.3V 5 uA Controt C1, C2 Outputs Ves = 7V Source Current Vour = Ves ~28V 500 HA Control C1, C2 Inputs Sink Current 8 BA Comparator Output Source Current 1 mA Sink Current 1 uA Waiting State Indicator Source Current 1 ma Sink Current 1 aA s9ssWNWMM5865 functional description A tock diagram of the MMS865. Universal Timer is shown in Figure 1.-A connection diagram is shown in Figure 2, Unless otherwise indicated, the following discussions are based on Figure 7. Funetion 1 In Function 1, counters 1 and 2 count up beginning with a transition on the StertStop pin from Vp t© Veg. Counter 2 is shown counting, A second transition from Vo 10 Vss on the StartStop pin inhibits the clack pulses to counter 2, stores and displays the con tents of counter 2. Counter 1 continues to count. The third tansition from Vop t0 Vg on the Start-Stop pin resets counter 2, enables clack pulees to counter 2 and displays counter 2 counting, Subsequent Start Stop transitions repeat this sequence, all this time unter 1 continues to count, At the conclusion of the last event to be timed, a Final Event Stop transition from Vpp 10 Vgg inhibits the clock to both counters and displays counter 2, A Start-Stop transition from Vo 10 Veg switches the display from counter 2 to counter 1, Repetitive Start-Stop transitions switch the display between counter 2 and counter 1 Function 2 In Function 2, counter 1 and 2 count up beginning with a transition on the Start-Stop pin. Counter 2 is displayed counting. A second transition on the Start-Stop pin inhibits the clack pulses to both counter 1 snd counter 2, stores and displays the contents of counter 2. The third transition on the StartStop pin resets counter 2, enables the clock to both counters and displays counter 2 counting, Subsequent Start-Stap transitions repeat this sequence. At the conclusion of the last event to be timed, 2 Final Event Stop transition inhibits the clock to bath counters and displays counter 2. A Start-Stop transition switches the display from counter 2 to counter 1, Repetitive StartStop transitions switch the display between counter 2 and counter 1 Flow Chaet for Function 1 Flow Chart for Function 2 212functional description (con't) Function 3 In Function 3, counter 1 and 2 count up beginning with a transition on the StartStop pin. Counter 2s displayed counting. A second transition on the Start Stop pin stores and displays the contents of counter 2, resets counter 2, and initiates a new up-count in counter 2; however, the new up-count is not displayed, Counter 1 continues to count A transition on the Latch Control pin will display counter 2 counting until another transi tion on the Start-Stop pin. Final Event Stop transition inhibits the clock pulses to both counters 1 and 2 and displays the contents of counter 2. A StartStop transi tion after the Final Event transition switches the display from counter 2 to counter 1. Repetitive Start Stop transitions switch the display between counter 2 and counter 1 Flow Chart for Function 3 Function 4 In Function 4, counter 2 counts up beginning with a transition on the Start-Stop pin. Counter 2 is displayed counting. A second transition on the StartStop pin stores and displays the contents of counter 2. Subse- quent Start-Stop transitions update the display of counter 2. A transition on the Latch Control pin will display counter 2 counting until a transition on the StartStop pin, A Final Event Stop transition inhibits the clack pulses to counter 2 and displays the contents of counter 2. Flow Chart for Function ¢ S98cINNMM5865 functional description (con‘t) Function 5 In Function 5, counter 1 and 2 count up beginning with 2 transition on the Start Stop pin. Counter 2 is displayed counting. A second transition on the Start-Stop pin inhibits the clock pulses to counter 2, and the contents of counter 2 are displayed. Counter 1 continues count. ing, The third Start-Stop transition enables the clock pulses to counter 2 and counter 2 is displayed counting, Subsequent StartStop transitions repeat this sequence, ail the time counter 1 continues counting. At the conclu: sion of the last event to be timed, a Final Event Stop inhibits the clock pulses to both counters 1 and 2, and displays counter 2. A StartStop transition switches the display from counter 2 to counter 1. Repetitive Start-Stop transitions switch the display between counter 2and counter 1. el Function 6 In Funetion 6, counter 1 is displayed at power-on or reset. Counter 1 is set to a specific count by Program Digit 1-4 pins. Then the comparator is enabled. Counter 2 is displayed counting up beginning with a transition ‘on the Start-Stop pin. When counter 2 is coincident with counter 1, the clock pulses to counter 2 are inhibited, the contents of counter 2 are displayed and the Com parator Output is enabled, Upon the transition of Reset, counter 1 is again displayed with the time that was set, and the Comparator Output is disabled, Counter 1 can bbe reprogrammed by the Program Digit 1-4 pins if desiced. A StartStop transition repeats the sequence. If the Comparator Output pin is connected to the Reset pin, Automatic Reset will occur, however, this connection must be broken during digit programming, reno ie (Bee Flow Chart for Function § Flow Chart for Function 6functional description (con't) Funetion 7 In Function 7, counter 1 is displayed all the time, Counter 1 is set to a specific count by Program Digit 1-4 pins. Then the comparator and Control C1 In are enabled. Pin 4 and pin 35 must be floating or con. ected to Voo during digit programming. Counter t counts down from the set count beginning with a transition on the Start Stop 9in, When counter 1 counts down to zero, the clock pulses to counter 1 are inhib, ited and the comparator Output is enabled. This is aot jepeatable without setting a new count into counter 1 The comparator and Control C1 In must be inhibited and a reset pulse must occur before the new count may be entered Flow Chart for Function 7 Reset This input will reset all logic and counters in Functions 1-5 and Furetion 7. In Funetion 6, Reset will reset logic but not counter 1. Reset is internally pulled to Vop, oF logic zero. For 8 reset to occur, the Reset pin must be held t0 Vg, a logic one. Start Stop This input is used to contro! the counters, How it affects the counters is explained in each function. For Start: Stop to affect the counters, it must be held to Ves. 2 logic one. Logic zero results when the pin is tied to Voo oF left floating [internal pull-up to Veo). Final Event Stop/Comparator Output This pin is used to indicate to the circuit that no more events will be timed or counted. Final Event Stop affects the circuit when it is held to Vsg. There is an internal Pullup to Vop. This pin is also an output pin, Veg indicates comparison between the two counters. Divide Scale Inputs These three inputs are used to determine whether the counters witl count in Modulo 6 or Modulo 10. Table | shows the code for which digit will count in Modulo 6 or Modulo 10. A logic one is when the pin is held to Vegs. When the pin is tied t0 Voo oF left floating {inter nal pullxp to Vpp], 2 logie zero results ‘TABLE |. Divide Scater Code DIvIDE oyes counter counter 2 123 | pa 3 02 py os 0 02 oF De © | 0 10 1 10 1 1 10 10 1 0 o | 6 w 9 0 6 0 wm o 1 0 | w 5 0 0 0 6 w w To |e to ee i 0 Gea 0 0 1 | 1 1 10 1 19 1% m9 10 re 1,0 0 we wo wo 0 1 1 | ww © 1% 0 6 0 10 1 | wo we 1 we wo 6 0 Comparator Enable This input enables the comparator. To enable the com parator, the pin is held to Vg oF logic one. To disable the comparator, the pin is tied to Vop oF left floating (intemal pull-up to Vop). Resolution Select Inputs ‘These two inputs are used to select the frequency of the clock pulses to the counters, Table I! shows the code for ‘each frequency. A logic one is when the pin is held to Vg. A logic zero results when the pin is tied 10 Vapor left floating (internal pull-up to Vap). TABLE II, Resolution Select Code PLT” | GEOR | _osrtay ae counters | RESOLUTION 215 sossSWNWMM5865 functional description (con't) Clock In/Out This pin is either an input or output depending on the ‘code at the Resolution Select inputs. If the pin is used as an output pin, it will output the elock frequency the Resolution Select inputs have selected. When used as an input, an external clock is used to clock the counters, Blanking Output This output is used to blank the display at the beginning and end of each digit time to aliow for internal delay between two cascaded chips, see Figure 3. The display is blanked when the Blanking Output is at Vo ee some tT FIGURE 3, Blanking Output Oscillator In and Out A quartz crystal, resonant at 328 kHz, two capacitors ‘and one resistor, together with the internal MOS circuits form a erystal controlled oscillator as shown in Figure 4. Varying one of the capacitors allows precise frequency settings. For test purposes, OSC IN is the input and OSC OUT is the output of an inverting amplifier. aR FIGURE 4. Crystal Oscillator Multiplex Input and Output The Multiplex Input pin allows an external multiplex rate to be Used in the chip, The multiplex rate inside the chip is one fourth the Multiplex Input and Multiplex Output rate, When using the Multiplex Input pin, the Multiplex Output pin must be tied to Vg. The Muiti plex Output pin is four times the internal multiplex To use the Multiplex Output pin, the Multiplex Input pin must be tied to Vop. The Multiplex Input must be used if the oscillator pins are not used. If the Multiplex Input pin is used, OSC IN, OSC OUT and the blanking output are not used, Control C1, C2 In and Control C1, C2 Out ‘These four input pins are used to cascade two chips together. When the Control C1 In pin is floating (inter- nal pull-up to Vgp) or tied t0 Vog, the clock pulses to counter 1 ate inhibited. When Cantrol C1 In is at Veg, counter 1 is enabled. Control C1 Out is at Vss_ when counter 1 is at its maximum count, and it is floating ‘at all other times. The Control C1 In pin must be floating (or connected to Ving) while digit program: ming in Function 7. Control C2 pins operate on counter 2 in a similar manner, Program Digits 1-4 These four input pins are used to program or set any count desired in counter 1 in Functions 6 and 7. When Program Digit 1 is at Vag, the least significant digit of counter 1 advances at 92.5 Hz rate. There is no carry over from digit to digit. Program Digit 1 has no effect if tied to Voo or left floating (internal pull-up to Vp). Only one Program Digit input may be held to Vsg at atime. Program Digit 1/Latch Controt This input has two functions; besides setting a count in digit 1 of counter 1 in Functions 6 or 7, it also affects Functions 3 and 4. In Functions 3 and 4, this input allows the display to show counter 2 counting as des cried in Functions 3 and 4. Program Digit 4/Waiting State Indicator This input besides setting a count in digit 4 of counter 1 in Functions 6 and 7, also indicates that the chip has been reset and is in the stand-by mode at power-on, In Functions 1—5, the Waiting State Indicator is at Vss Until a StartStop transition has occured. Once a Start Stop transition has occured, the output remains at Voo- Leading Zero Blanking In Functions 1-5, leading zeros are blanked for both counters 1 and 2. In Functions 6 and 7, counter 2 has leading zero blanking. At power-on, the display is blank. in Functions 1-5, and all zeros are displayed in Fune: tions 6 and 7. Output Circuits For CD and Digit Outputs, Vsg is a logic one. Figure & iMlustrates the circuit used for all outputs except for Control C1, C2 Out. The Control C1, C2 Out circuit is illustrated in Figure 6, Figure 7 illustrates the simple interface needed for an Bdigit stop-watch. Figure & illustrates the MMS865 being used to count how many events occur in a specified time. Figure 9 shows the MMS865 as a simple industrial counter when the input clock is a constant frequency above 400 He. 216