3.5 CMOS/TTL Interfacing: V V V V
3.5 CMOS/TTL Interfacing: V V V V
5 CMOS/TTL Interfacing
There are several factors to consider in
TTL/CMOS interfacing, the first is noise
margin; the next factor is fanout; the last
factor is capacitive loading.
For example : HC or HCT driving TTL
TTL
CMOS
Considerin
g fanout,
an HC or
HCT
VOL max C 0.33V VIL max T 0.8V
output can
VOH min C 3.84V VIH min T 2.0V
drive 10
LS or only
Next
Return
2 S-TTL
CMOS
TTL
CMOS
R p max
5K
I LeakageHT I IH max C
RP=(3-5)K.
Return
Back