Introduction to

CMOS VLSI
Design

Lecture 17:
Design for Testability
David Harris

Harvey Mudd College

Spring 2004

Outline
q Testing
Logic Verification
Silicon Debug
Manufacturing Test
q Fault Models
q Observability and Controllability
q Design for Test
Scan
BIST
q Boundary Scan
17: Design for Testability

CMOS VLSI Design

Slide 2

Testing
q Testing is one of the most expensive parts of chips
Logic verification accounts for > 50% of design
effort for many chips
Debug time after fabrication has enormous
opportunity cost
Shipping defective parts can sink a company
q Example: Intel FDIV bug
Logic error not caught until > 1M units shipped
Recall cost $450M (!!!)
17: Design for Testability

CMOS VLSI Design

Slide 3

Logic Verification
q Does the chip simulate correctly?
Usually done at HDL level
Verification engineers write test bench for HDL
Cant test all cases
Look for corner cases
Try to break logic design
q Ex: 32-bit adder
Test all combinations of corner cases as inputs:
0, 1, 2, 231-1, -1, -231, a few random numbers
q Good tests require ingenuity
17: Design for Testability

CMOS VLSI Design

Slide 4

Silicon Debug
q Test the first chips back from fabrication
If you are lucky, they work the first time
If not
q Logic bugs vs. electrical failures
Most chip failures are logic bugs from inadequate
simulation
Some are electrical failures
Crosstalk
Dynamic nodes: leakage, charge sharing
Ratio failures
A few are tool or methodology failures (e.g. DRC)
q Fix the bugs and fabricate a corrected chip
17: Design for Testability

CMOS VLSI Design

Slide 5

Shmoo Plots
q How to diagnose failures?
Hard to access chips
Picoprobes
Electron beam
Laser voltage probing
Built-in self-test
q Shmoo plots
Vary voltage, frequency
Look for cause of
electrical failures
17: Design for Testability

CMOS VLSI Design

Slide 6

Shmoo Plots
q How to diagnose failures?
Hard to access chips
Picoprobes
Electron beam
Laser voltage probing
Built-in self-test
q Shmoo plots
Vary voltage, frequency
Look for cause of
electrical failures
17: Design for Testability

CMOS VLSI Design

Slide 7

Manufacturing Test
q A speck of dust on a wafer is sufficient to kill chip
q Yield of any chip is < 100%
Must test chips after manufacturing before
delivery to customers to only ship good parts
q Manufacturing testers are
very expensive
Minimize time on tester
Careful selection of
test vectors

17: Design for Testability

CMOS VLSI Design

Slide 8

Testing Your Chips

q If you dont have a multimillion dollar tester:
Build a breadboard with LEDs and switches
Hook up a logic analyzer and pattern generator
Or use a low-cost functional chip tester

17: Design for Testability

CMOS VLSI Design

Slide 9

TestosterICs
q Ex: TestosterICs functional chip tester
Designed by clinic teams and David Diaz at HMC
Reads your IRSIM test vectors, applies them to
your chip, and reports assertion failures

17: Design for Testability

CMOS VLSI Design

Slide 10

Stuck-At Faults
q How does a chip fail?
Usually failures are shorts between two
conductors or opens in a conductor
This can cause very complicated behavior
q A simpler model: Stuck-At
Assume all failures cause nodes to be stuck-at
0 or 1, i.e. shorted to GND or VDD
Not quite true, but works well in practice

17: Design for Testability

CMOS VLSI Design

Slide 11

Examples

17: Design for Testability

CMOS VLSI Design

Slide 12

Observability & Controllability

q Observability: ease of observing a node by watching
external output pins of the chip
q Controllability: ease of forcing a node to 0 or 1 by
driving input pins of the chip
q Combinational logic is usually easy to observe and
control
q Finite state machines can be very difficult, requiring
many cycles to enter desired state
Especially if state transition diagram is not known
to the test engineer
17: Design for Testability

CMOS VLSI Design

Slide 13

Test Pattern Generation

q Manufacturing test ideally would check every node
in the circuit to prove it is not stuck.
q Apply the smallest sequence of test vectors
necessary to prove each node is not stuck.
q Good observability and controllability reduces
number of test vectors required for manufacturing
test.
Reduces the cost of testing
Motivates design-for-test
17: Design for Testability

CMOS VLSI Design

Slide 14

Test Example
SA1
q
q
q
q
q
q
q
q

SA0

A3
A2
A1
A0
n1
n2
n3
Y

n1

A3
A2

A1

Y
n2

n3

A0

q Minimum set:
17: Design for Testability

CMOS VLSI Design

Slide 15

Test Example
q
q
q
q
q
q
q
q

A3
A2
A1
A0
n1
n2
n3
Y

SA1
{0110}

SA0
{1110}

n1

A3
A2

A1

Y
n2

n3

A0

q Minimum set:
17: Design for Testability

CMOS VLSI Design

Slide 16

Test Example
q
q
q
q
q
q
q
q

A3
A2
A1
A0
n1
n2
n3
Y

SA1
{0110}
{1010}

SA0
{1110}
{1110}

n1

A3
A2

A1

Y
n2

n3

A0

q Minimum set:
17: Design for Testability

CMOS VLSI Design

Slide 17

Test Example
q
q
q
q
q
q
q
q

A3
A2
A1
A0
n1
n2
n3
Y

SA1
{0110}
{1010}
{0100}

SA0
{1110}
{1110}
{0110}

n1

A3
A2

A1

Y
n2

n3

A0

q Minimum set:
17: Design for Testability

CMOS VLSI Design

Slide 18

Test Example
q
q
q
q
q
q
q
q

A3
A2
A1
A0
n1
n2
n3
Y

SA1
{0110}
{1010}
{0100}
{0110}

SA0
{1110}
{1110}
{0110}
{0111}

n1

A3
A2

A1

Y
n2

n3

A0

q Minimum set:
17: Design for Testability

CMOS VLSI Design

Slide 19

Test Example
q
q
q
q
q
q
q
q

A3
A2
A1
A0
n1
n2
n3
Y

SA1
{0110}
{1010}
{0100}
{0110}
{1110}

SA0
{1110}
{1110}
{0110}
{0111}
{0110}

n1

A3
A2

A1

Y
n2

n3

A0

q Minimum set:
17: Design for Testability

CMOS VLSI Design

Slide 20

Test Example
q
q
q
q
q
q
q
q

A3
A2
A1
A0
n1
n2
n3
Y

SA1
{0110}
{1010}
{0100}
{0110}
{1110}
{0110}

SA0
{1110}
{1110}
{0110}
{0111}
{0110}
{0100}

n1

A3
A2

A1

Y
n2

n3

A0

q Minimum set:
17: Design for Testability

CMOS VLSI Design

Slide 21

Test Example
q
q
q
q
q
q
q
q

A3
A2
A1
A0
n1
n2
n3
Y

SA1
{0110}
{1010}
{0100}
{0110}
{1110}
{0110}
{0101}

SA0
{1110}
{1110}
{0110}
{0111}
{0110}
{0100}
{0110}

n1

A3
A2

A1

Y
n2

n3

A0

q Minimum set:
17: Design for Testability

CMOS VLSI Design

Slide 22

Test Example
q
q
q
q
q
q
q
q

A3
A2
A1
A0
n1
n2
n3
Y

SA1
{0110}
{1010}
{0100}
{0110}
{1110}
{0110}
{0101}
{0110}

SA0
{1110}
{1110}
{0110}
{0111}
{0110}
{0100}
{0110}
{1110}

n1

A3
A2

A1

Y
n2

n3

A0

q Minimum set: {0100, 0101, 0110, 0111, 1010, 1110}

17: Design for Testability

CMOS VLSI Design

Slide 23

Design for Test

q Design the chip to increase observability and
controllability
q If each register could be observed and controlled,
test problem reduces to testing combinational logic
between registers.
q Better yet, logic blocks could enter test mode where
they generate test patterns and report the results
automatically.

17: Design for Testability

CMOS VLSI Design

Slide 24

Scan
CLK
Flop

q Convert each flip-flop to a scan register SCAN

Only costs one extra multiplexer
SI
D
q Normal mode: flip-flops behave as usual
q Scan mode: flip-flops behave as shift register

Logic
Cloud

Flop
Logic
Cloud

Flop

Flop

Flop

Flop

Flop

outputs

Flop

inputs

Flop

Flop
Flop

Flop

q Contents of flops
can be scanned
out and new
values scanned
in

Flop

scan-in

scanout

17: Design for Testability

CMOS VLSI Design

Slide 25

Scannable Flip-flops
SCAN
SCAN CLK

(a)

SI

D
0

Flop

Q
SI

(b)

SCAN

SI

(c)
s

17: Design for Testability

CMOS VLSI Design

Slide 26

Built-in Self-test
q Built-in self-test lets blocks test themselves
Generate pseudo-random inputs to comb. logic
Combine outputs into a syndrome
With high probability, block is fault-free if it
produces the expected syndrome

17: Design for Testability

CMOS VLSI Design

Slide 27

PRSG
q Linear Feedback Shift Register
Shift register with input taken from XOR of state
Pseudo-Random Sequence Generator

Q[1]

Flop

Q[0]

Flop

Flop

CLK
Q[2]

Step

111

1
2
3
4
5
6
7

17: Design for Testability

CMOS VLSI Design

Slide 28

PRSG
q Linear Feedback Shift Register
Shift register with input taken from XOR of state
Pseudo-Random Sequence Generator

Q[1]

Flop

Q[0]

Flop

Flop

CLK
Q[2]

Step

111

110

2
3
4
5
6
7
17: Design for Testability

CMOS VLSI Design

Slide 29

PRSG
q Linear Feedback Shift Register
Shift register with input taken from XOR of state
Pseudo-Random Sequence Generator

Q[1]

Flop

Q[0]

Flop

Flop

CLK
Q[2]

Step

111

110

101

3
4
5
6
7
17: Design for Testability

CMOS VLSI Design

Slide 30

PRSG
q Linear Feedback Shift Register
Shift register with input taken from XOR of state
Pseudo-Random Sequence Generator

Q[1]

Flop

Q[0]

Flop

Flop

CLK
Q[2]

Step

111

110

101

010

4
5
6
7
17: Design for Testability

CMOS VLSI Design

Slide 31

PRSG
q Linear Feedback Shift Register
Shift register with input taken from XOR of state
Pseudo-Random Sequence Generator

Q[1]

Flop

Q[0]

Flop

Flop

CLK
Q[2]

Step

111

110

101

010

100

5
6
7
17: Design for Testability

CMOS VLSI Design

Slide 32

PRSG
q Linear Feedback Shift Register
Shift register with input taken from XOR of state
Pseudo-Random Sequence Generator

Q[1]

Flop

Q[0]

Flop

Flop

CLK
Q[2]

Step

111

110

101

010

100

001

6
7
17: Design for Testability

CMOS VLSI Design

Slide 33

PRSG
q Linear Feedback Shift Register
Shift register with input taken from XOR of state
Pseudo-Random Sequence Generator

Q[1]

Flop

Q[0]

Flop

Flop

CLK
Q[2]

Step

111

110

101

010

100

001

011

7
17: Design for Testability

CMOS VLSI Design

Slide 34

PRSG
q Linear Feedback Shift Register
Shift register with input taken from XOR of state
Pseudo-Random Sequence Generator

17: Design for Testability

Q[1]

Flop

Q[0]

Flop

Flop

CLK
Q[2]

Step

111

110

101

010

100

001

011

111 (repeats)

CMOS VLSI Design

Slide 35

BILBO
q Built-in Logic Block Observer
Combine scan with PRSG & signature analysis
D[0]

D[1]

D[2]

Q[0]

PRSG

17: Design for Testability

Logic
Cloud

Flop

Flop

SI

Flop

C[0]
C[1]

Q[2] / SO

Q[1]

Signature
Analyzer

CMOS VLSI Design

MODE
Scan
Test
Reset
Normal

C[1]
0
0
1
1

C[0]
0
1
0
1

Slide 36

Boundary Scan
q Testing boards is also difficult
Need to verify solder joints are good
Drive a pin to 0, then to 1
Check that all connected pins get the values
q Through-hold boards used bed of nails
q SMT and BGA boards cannot easily contact pins
q Build capability of observing and controlling pins into
each chip to make board test easier

17: Design for Testability

CMOS VLSI Design

Slide 37

Boundary Scan Example

PackageInterconnect

CHIP B

CHIP C

Serial Data Out

CHIP A

CHIP D

IO pad and Boundary Scan

Cell
Serial Data In

17: Design for Testability

CMOS VLSI Design

Slide 38

Boundary Scan Interface

q Boundary scan is accessed through five pins
TCK:
test clock
TMS:
test mode select
TDI:
test data in
TDO:
test data out
TRST*:
test reset (optional)
q Chips with internal scan chains can access the
chains through boundary scan for unified test
strategy.
17: Design for Testability

CMOS VLSI Design

Slide 39

Summary
q Think about testing from the beginning
Simulate as you go
Plan for test after fabrication
q If you dont test it, it wont work! (Guaranteed)

17: Design for Testability

CMOS VLSI Design

Slide 40