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Lab Verilog

1. The document provides instructions to design and realize various logic circuits in Verilog HDL including a fire sprinkler system, car alarm, warning light, parity generator, zero/one detector, NAND and NOR gates, full adder, and ripple carry adder. Tests benches are also to be written to verify the functionality of each circuit.

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24 views

Lab Verilog

1. The document provides instructions to design and realize various logic circuits in Verilog HDL including a fire sprinkler system, car alarm, warning light, parity generator, zero/one detector, NAND and NOR gates, full adder, and ripple carry adder. Tests benches are also to be written to verify the functionality of each circuit.

Uploaded by

giligails
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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Design and Realize the following in Verilog HDL .

Also write Test


Bench to verify the functionality
1. A fire sprinkler system should spray water if high heat
is sensed and the system is set to enabled.
(Hint: Let Boolean variable h represent high heat is sensed, e
represent enabled, and F represent spraying water.)
2. A car alarm should sound if the alarm is enabled, and
either the car is shaken or the door is opened
(Hint: Let a represent alarm is enabled, s represent car is
shaken, d represent door is opened, and F represent alarm
sounds.)
3. Design circuit for warning light
Sensors
let

s=1: seat belt fastened

, k=1: key inserted


, p=1: person in seat
(a) Capture Boolean equation
if the person in seat, and seat belt not
fastened, and key inserted

(b) Convert the equation from (a) to circuit


4. Design a 9-bit even and odd parity generator circuit.
5. Design an all-bit zero/one detector circuit for an 8-bit data input and
realize using Verilog HDL

6. Realize a two input NAND gate using two input NOR gates
7. Implement FULL ADDER using only NAND gates
8. Implement FULL ADDER using only NOR gates
9. Design and realize using verilog HDL a logic circuit whose output is
HIGH whenever A and B are both HIGH as long as C and D are either
both LOW or both HIGH.
10. Design a 4 bit RIPPLE CARRY ADDER using 1-bit FULL ADDER.
11. Using the conditional operator , write a module to shift the input
DATA right logically by the number of positions specified by another
input SHIFT, ranging from 0 to 3.

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