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Make The Following Changes To The 299:: 4-Bit Q3 4-Bit Also Make The DS7 Input DS3

This homework assignment asks students to design and simulate a 6-bit 4-bit version of a CD54AC299 chip, modifying the original 8-bit version. Students are to write a testbench, conduct thorough testing, and print the simulator output. The design and testbench code must be turned in along with a timing diagram. An additional 10 bonus points are available for synthesizing the design and demonstrating it on an FPGA board using slide switches as inputs and LEDs as outputs.

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Ryan Harris
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38 views1 page

Make The Following Changes To The 299:: 4-Bit Q3 4-Bit Also Make The DS7 Input DS3

This homework assignment asks students to design and simulate a 6-bit 4-bit version of a CD54AC299 chip, modifying the original 8-bit version. Students are to write a testbench, conduct thorough testing, and print the simulator output. The design and testbench code must be turned in along with a timing diagram. An additional 10 bonus points are available for synthesizing the design and demonstrating it on an FPGA board using slide switches as inputs and LEDs as outputs.

Uploaded by

Ryan Harris
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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ECE 351 HW #4

Due: May 22th


This is the last homework assignment.
You are to design and simulate a CD54AC299. The data sheet is in the homework
folder.
MAKE THE FOLLOWING CHANGES TO THE 299:
1. Implement a 6-bit 4-bit version, not an 8-bit version.
2. Q7 is the MSB output on the 299. Implement a Q5 Q3 output instead because you
are only
making a 6-bit 4-bit version of the devise. Also make the DS7 input DS3.
You will have to write your own testbench. Make sure you conduct a thorough,
comprehensive
test. Print a copy of the simulator output showing some of the tests you ran. Turn in
the timing
diagram and the source code for both design and the testbench.
You will get 10 points if you do the above AND your design EXACTLY implements the
299
(subject to the above changes). Note the data lines are bidirectionalthere are not
separate
inputs for loading data and separate outputs for displaying data.
BONUS: You will get 10 extra points if you synthesize the design and demonstrate
it to the TA.
Input data using the slide switches and display the output in the LEDs. (The pin
assignments on
the FPGA prototype board for switches and LEDs are below.)
NOTES:
1) In the DOWN or OFF position (closest to the board edge), a slide switch provides
a
LOW logic level (0 volts) to the FPGA. In the UP position a switch provides a HIGH
logic level (3.3 volts). Use slide switches to implement the 6-bit 4-bit data input,
OE1#, OE2#, DS0, DS3, S1 and S0.
2) A push-button switch generates an active low signal when pressed, returning to a
high logic
level when released. These push-button switches are debounced so they can be
used for your
MR and a clock for your design.

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