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Configuration Schemes Overview

The document discusses different configuration schemes for FPGAs including active and passive schemes. Active schemes involve the FPGA generating control signals while passive schemes use an external host. Serial and parallel configuration methods are covered along with supporting memory devices and relative speed.

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Amit Patel
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
59 views

Configuration Schemes Overview

The document discusses different configuration schemes for FPGAs including active and passive schemes. Active schemes involve the FPGA generating control signals while passive schemes use an external host. Serial and parallel configuration methods are covered along with supporting memory devices and relative speed.

Uploaded by

Amit Patel
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Configuration Schemes Overview

Active configuration schemes


- Target FPGA generates control & synchronous signals
External
Memory

FPGA

Provides configuration data

Configuration
Controller

Initiates configuration process

Passive configuration schemes


- External host controls the configuration process
Configuration
Device
FPGA

Memory

Initiates configuration process


and provides configuration data Configuration
Controller

Active Configuration Schemes


External
Memory

FPGA

Provides configuration data

Configuration
Controller

Initiates configuration process

Active serial (AS):


- Configuration data gets loaded one bit at the time.
- Supported memory device: serial configuration (EPCS) device.

Active parallel (AP):


- Configuration data gets loaded 16 bits at a time.
- Supported memory device: 16 bit parallel flash memory
- Applicable to Cyclone III and Cyclone IV devices only.

10

Passive Configuration Schemes


n
EPC Device
FPGA

Passive Serial (PS):


-

Memory
Configuration
Controller

Passive parallel schemes:


-

FPGA

JTAG Configuration:
-

External Flash
Memory

FPGA

11

Configuration data gets loaded 8 bits at a time


Supported schemes:
l Fast passive parallel (FPP)
l Passive parallel synchronous (PPS)
l Passive parallel asynchronous (PPA)

MAX II or
External Processor
Configuration
Controller

Configuration data gets loaded one bit at a


time

Developed by Joint Test Action Group as a


specification for boundary-scan testing
Standardized as IEEE Std. 1149.1
Test pin connections and functionality without
using physical probes
Forced test data is serially shifted into
boundary-scan cells
Captured data is serially shifted out
Captured data is compared with the expected
results

Configuration Schemes Comparison


Active or passive
configuration scheme

Configuration
scheme

Serial or parallel
configuration

External memory and/or


configuration device

Width of
configuration
data

Relative
configuration
time

Active

AS

Serial

EPCS device

Moderate

AP

Parallel

Supported common flash interface


(CFI) parallel flash memory

16

Fast

PS

Serial

MAX II, MAX3000A/7000, or


microprocessor with flash memory

Moderate

Serial

EPC device

Moderate

Serial

Download cable

Moderate

Parallel

MAX II, MAX3000A/7000, or


microprocessor with flash memory

Fast

Parallel

EPC device

Fast

PPA

Parallel

MAX II, MAX3000A/7000, or


microprocessor with flash memory

Moderate

JTAG

Serial

MAX II, MAX3000A/7000, or


microprocessor with flash memory

Slow

Serial

Download cable

Slow

Passive

FPP

12

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