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Analog Verification, An Introduction

Analog Verification

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159 views13 pages

Analog Verification, An Introduction

Analog Verification

Uploaded by

mithungn
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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AnalogVerification

KenKundert

Copyright2009,DesignersGuideConsulting,Inc. AllRightsReserved

DesignsTheyAreAChangin

BobDylan,1964

TheComplexityofDesignisGrowingRapidly
AlgorithmicArchitectures
architectures
Autocalibration
Adaptivefiltering
2010
Etc.
2000
1990
Modes&Settings

Size
>100Ktransistors

InMultipleDimensions!
Copyright2009,DesignersGuideConsulting,Inc. AllRightsReserved

Powermodes
Digitaltrimming
Multiplestandards
Etc.

FunctionalErrors
Functionalerrorsareoftenverysimpleerrors

Invertedsignals
Corruptlogic
Flippedbusses
Unaccountedfordependencies(chicken/eggproblem)
Communicationerrors

Butaregenerallycatastrophic

Design

Copyright2009,DesignersGuideConsulting,Inc. AllRightsReserved

InRecentVerificationEfforts
Wefound

swappedinputs
logicerrorthatprecludedsleepmode
bussesswapped
dependencyloop(chicken&eggproblem)
invertedbiascurrent
wiresswapped
invertedinput
swappedreset&resetbar
logiclinescrossingsupplydomainsw/olevelshifters
incorrectRTL
undriven logicsignalinanalogtoplevel
errorsinregistermap
manyspecerrors
Andmore

Copyright2009,DesignersGuideConsulting,Inc. AllRightsReserved

TheThreeBasicIssues
Detailedverificationonlyperformedatblock
level
Allrequiredsignalsareassumedtobepresent
Assumptionsoninterblockdependenciesnever
verified

Verificationonmostmodesneverperformed
Onlytypicalorworstcasemodes
Anycontrollogicthatsupportsuntestedmodecould
containhiddenerror

Noanalog digitalcoverification
5
Copyright2009,DesignersGuideConsulting,Inc. AllRightsReserved

TransistorLevelVerification
Tooexpensiveforfunctionalverification
10Ktransistors,30Kcycles,250modes
Oneweekforonemodewithtimingsimulator

Neednightlyregressiontests
10K speedup
needed

Chiplevelrequires
100K1M speedups
Copyright2009,DesignersGuideConsulting,Inc. AllRightsReserved

WhatsNeeded
Systematicapproachtoverifyingdesign&
specification
Confidencethatallflawshavebeenfound
Moreverification,earlierindesignflow
Errorsareeasiertofix&lessdisruptive

Helpwithperformanceverification
Accuratemodelofmixedsignalsection

Copyright2009,DesignersGuideConsulting,Inc. AllRightsReserved

TheAnswer
Functionalverificationwith
Modelbasedverification
Dramaticallyacceleratesthesimulation
Movesitearlierindesigncycle

Exhaustiveregressiontesting
Checkeverymodeandeverysetting
Automatedpass/failtests(selfcheckingtests)

Creationofaverifiedsignoffqualitytop
levelmodel
OftenmustbepureVerilog orVHDL
Copyright2009,DesignersGuideConsulting,Inc. AllRightsReserved

ThisisAnalogVerification
Exhaustiveregressiontesting
Traceabletotransistorlevel
Verifiesbothmodelsandcircuits
Testbenchesverifybehaviorofmodels
Methodologyassuresmodelsareconsistent
withcircuit

Drivenbyanalogverificationengineer
We can now imagine a future where we are surprised
when an analog chip does not function the first time.
9
Copyright2009,DesignersGuideConsulting,Inc. AllRightsReserved

Conclusions
Complexsystemdesignrequiresa
rigoroussystemverificationmethodology
Chipdesignandanalogimplementation
needstobelinkedforverification
AVcanbedonetoday
ModelingandRegressionTesting

Thebiggerthesystem,themorebenefit
willbederivedfromusingAV
Copyright2009,DesignersGuideConsulting,Inc. AllRightsReserved

DesignersGuideConsulting
Adoptinganalogverificationisadifficult
process,filledwithpotentialpitfalls
Wecanhelpguideyouthroughtheprocess

Teachclasses
Trainingyourverificationengineers
Guideverificationplanning
Consultondifficultmodels&tests
Howtocreateveryfastanalogmodelsinverilog
Howtoovercomeperformanceissues

ProvideAVservices
Copyright2009,DesignersGuideConsulting,Inc. AllRightsReserved

References
H.Chang&K.Kundert.VerificationofComplex
AnalogandRFICDesigns.TheProceedingsoftheIEEE.
March2007.
K.Kundert&H.Chang.VerificationofComplex
AnalogIntegratedCircuits.CICC06.
K.Kundert&O.Zinke.TheDesignersGuidetoVerilog
AMS.2004.
K.Kundert.Principlesoftopdownmixedsignal
design.www.designersguide.org/Design.
A.Meyer.PrinciplesofFunctionalVerification.2003.
AnalogVerificationNewsletter.www.designers
guide.com/newsletters
Copyright2009,DesignersGuideConsulting,Inc. AllRightsReserved

ForMoreInformation

www.designersguide.com

Copyright2009,DesignersGuideConsulting,Inc. AllRightsReserved

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